1

Using a Metadata-based Methodology for

IP Configuration, Intelligent IP Integration and Verification

Tech Symposia 2014

2

IP configurability is evolving because …

Highly complex subsystems

Competitive IP market

IP providers are having to deliver …

Reasonable cost

High quality

Highly configurable IP to meet various end

applications

IP Configurability is Evolving

3

IP Provider

• Needs to create and deliver IP without knowing how that IP will be integrated and configured in the IP consumers system

IP

• Needs to be highly configurable to suit a wide variety of end applications

This Poses Unique Challenges …

4

IP Configurability timeline

TODAY

High level of intricate configurability

on both

the hardware and software sides

TOMORROW

High level of intricate configurability

on all sides …

Hardware, software, verification,

documentation …

YESTERDAY

Simple RTL configurability

for hardware design

ifdef parameters

5

Industry standards do not cover the full scope

Configurability is becoming IP specific

Detailed documentation is required to describe

the IP configurability

Poor adoption of standards and methodologies

for IP configurability is making efficient and

reusable integration more difficult

IP Configuration Challenges

6

An IP that has different

configuration options

Simple configurability example

Configurable port widths

Complex configurability e.g. DMC-400

Configurations of different internal logic, hardware interface and HW/SW interface

Address/bus/ID widths, burst acceptance capability, no. of interfaces present, buffer depths…

Massively configurable IP e.g. NIC-400

IP constructed out of variable number of configurable components and interconnections

What is Configurable IP? ARM CoreLink™ DMC-400 Dynamic Memory Controller

Memory Channel 0 Memory Channel 1

Write

Buffer &

Cache

Read

Queue

Write

Buffer &

Cache

Read

Queue

Memory Interface Memory Interface

Perf

orm

ance

Pro

filin

g

Inte

rfac

e

System I/F System I/F System I/F System I/F Config

I/F

QoS &

QV

N

7

IP configurability

IP quality

Predictable IP integration

What is Needed?

8

IP-XACT: The IP & IP Interface IEEE Standard Interoperable standard format between

IP providers, consumers and EDA vendors

that represents a design

9

Design

IP-XACT Representation of a Design

i_A1 i_A2

Interface X

Interface Y M S M M

Interface on the component boundary

Monitor Interface

Monitor Interconnection

Interconnection

Hierarchical Connection

Component Instance

Port A Port B

Interface Z

adHoc connection

An IP-XACT design element defines a hierarchical structure and associated connectivity “ ”

10

Provides:

Full IP-XACT design environment

Mechanism to configure IP using the IP-XACT approach

Has the ability to:

Define any structured data model

Render command APIs to the model automatically

Render it easily into a GUI for visualization

Run checks using a scriptable API

Generate IP-XACT

Generate other formats for HW, SW, DV & documentation

Generic Ideal Solution

11

XML Tree Structure of a Configuration Model

GIC (Generic Interrupt Controller)

CPU_AXI_ID_Width

Description

Distributor_AXI_ID_Width

Legacy Interrupts Support

Library

Name

NumberOfCPUs

PriorityLevels

PrivateInterrupts

PrivateInterrupt

Registering

Sensitivity

Private_Peripheral_Interrupts

Protocol

…

Example Configuration Model

An ideal solution would be able to take

this defined XML configuration model

and render it automatically into a GUI

to aid in rapid & correct configurability

“

”

12

Automatically Rendered into a GUI to Guide Configurability

13

Metadata-driven

Intelligent IP Integration & Verification

14

IP standardization

Machine-readable IP

Automated system assembly

DRC-clean connectivity

Auto-generated RTL

Intelligent IP Integration requires …

15

Importing ports from RTL

Defining and packaging IP interfaces

Exporting to IP-XACT

Auto-generating IP collateral

IP Standardization process involves …

16

Metadata-driven IP Integration Instructions

i_top

Create Create new Components, Instances,

Ports, Interfaces etc.

Connect Create a connection between two elements

Export From selected elements on component instances, create equivalent elements on the

periphery and connect them

Import From selected elements on the

periphery, create equivalent elements on component instances

and connect them

Tie-off Set a logic value on an input or

mark an output as open

Group/Split Create or dissolve levels of

hierarchy, while maintaining

connectivity

Insert Insert logic or component

instances across connections

Reflect From selected elements on a component

instance, create equivalent elements on another instance and connect them

= Created by instruction

i_1

i_2

i_3

i_4

i_5

i_6 i_7

17

68 instructions produced 1200

lines of Verilog code

Days vs. 6-7 weeks to develop

No connectivity errors

Metadata-driven CoreSight Subsystem Instruction Example

18

ARM Based System 4 processor clusters

3 bus interconnect systems

4 subsystems (DMC, Peripheral, LCD, Interconnect)

12,000+ lines of Verilog code 7+ weeks to develop normally

Many connectivity errors

Metadata-driven Intelligent IP Integration Case Study

CCI Interconnect

NIC Interconnect

Debug Subsystem

LCD Subsystem

DMA/MMU Subsystem

DMC Subsystem

CPU 0..3

CPU 4..7

CPU 8..11

CPU 12..15

CTRL

Bridge

SMC Subsystem

APB Subsystem

Interrupt Video RAM

ARM Based

System

NIC

Subsy

stem

19

Metadata-driven Intelligent IP Integration Case Study

Integration

Task

Sub Task

De

sign

er

1

De

sign

er

2

De

sign

er

3

DMC Subsystem X

SMC Subsystem X

LCD Subsystem X

NIC Subsystem X

Top-Level Instance Creation X

AMBA Connectivity X

Export Connectivity X

Interrupt Connectivity X

Clock/Reset X

Power Connectivity X

CPU Cluster Connectivity X

CCI Interconnect

NIC Interconnect

Debug Subsystem

LCD Subsystem

DMA/MMU Subsystem

DMC Subsystem

CPU 0..3

CPU 4..7

CPU 8..11

CPU 12..15

CTRL

Bridge

SMC Subsystem

APB Subsystem

Interrupt Video RAM

ARM-based

System

NIC

Subsy

stem

20

Chip integration completed within 4 days

Originally took 35+ days

Case Study Results

Integration Task Duration (Days)

DMC Subsystem 1

SMC Subsystem 1

LCD Subsystem 1

NIC Subsystem 2

Top-Level 2

8x improvement in schedule, as well as

increased quality, predictability and better quality of results “

”

21

DMC Subsystem

SMC Subsystem

LCD Subsystem

NIC Subsystem

Top-Level

0

1000

2000

3000

4000

5000

6000

7000

Verilog CodeIntelligent IP

Integration

Instructions

DMC Subsystem

SMC Subsystem

LCD Subsystem

NIC Subsystem

Top-Level

Case Study Metrics

22

Data Rule Checks (DRCs) to validate IP

configuration & implementation

Jump-start verification with auto-generation of

testbench structure

Auto-creation of reports and metrics

Verification

Metrics

Relative Size Indicator summary

Performance report

Deliverables

Reports

Implementation scripts

Metadata

Documentation

23

IP standardization

Guided IP configuration

Auto-generation of system-dependent IP

Automated, data-driven, IP integration & system assembly

How To Overcome Obstacles ?

IP Tooling that delivers IP

Standardization, Configuration

& Intelligent Integration