usb 3.1 and usb type-c functional and test solution update · 2015-01-16 · usb 3.1 and usb type-c...
TRANSCRIPT
USB 3.1 and USB Type-C Functional and Test Solution Update
Francis Liu 劉宗琪
Senior Project Manager
Application Engineer Org.
是德科技
Jan.13 & 14, 2015
Page
Disclaimer
USB3.1 Technical and
Electrical measurement
Challenges 2
Reference Documents
• Universal Serial Bus 3.1 Specification (Revision 1.0, July 26, 2013)
• Universal Serial Bus Type-C Cable and Connector Specification (Revision 1.0, August 11,
2014)
The USB 3.1 compliance test requirements are not final. Therefore, all
opinions, judgments, recommendations, etc. that are presented herein are
the opinions of the presenter of the material and do not necessarily reflect
the opinions of the USB-IF, or other member companies.
Page Agenda
• Introduction
• USB 3.1 Transmitter test Challenges
• USB 3.1 Receiver test Challenges
• USB Type-C Connector and Power Delivery(PD)
• USB 3.1 Cable and Connector Test
• Keysight Total Solution & Summary
USB3.1 Technical
and Electrical
measurement
Challenges 3
Page
Worldwide Shipment of USB-enabled Devices
• USB is the most successful interface in the history of PC
• Device charging over USB has become a major consumer feature
• USB installed base is 10+ billion units and growing at 3+ billion units a year
• Adoption is virtually 100% in PC and peripheral categories
USB3.1 Technical and
Electrical measurement
Challenges 4
Comparison of four USB generations
USB-IF Board Members
Intel, NEC, HP, Microsoft, ST-Ericsson, LSI
Brian Fetz
DisplayPort Phy CTS Editor
VESA Board Member
USB-IF Compliance Committee
USB 3.0 Electrical Test Spec WG
USB 3.1 Transmitter test challenge
USB3.1 Technical and
Electrical measurement
Challenges 5 Page
Page
USB 3.1 Gen1 vs. Gen2 Overview
Gen1 Gen2
Data rate 5Gb/s 10Gb/s
Coding 8b/10b 128b/132b
scrambler: G(X) = X23 + X21 + X16 + X8 + X5 + X2 + 1
SKP K28.1, K28.1 SKPOS with variable number of SKPs
LFPS Training, warm reset or side band
signaling protocol (pwr mgmt)
Device host capability negotiation is done
during LFPS phase using LFPS modulation
schemes (SCD1,SCD2,LBPM)
CDR JTF BW 4.9Mhz JTF BW 7.5Mhz
SSC Slew rate test New df/dt requirement: 1250 (max) ppm/μs
TX EQ Post cursor: -3dB (Normative) Pre cursor: 2.2 +/- 1dB (Normative)
Post cursor: -3.1 +/-1dB (Normative)
RX Ref EQ CTLE CTLE (6 level) + 1 tap DFE
Eye Height, TJ 100mV, 132ps (.66UI) 70mV, 67.1ps (.671UI)
USB3.1 Technical and
Electrical measurement
Challenges 6
Page
TX compliance modes
USB 3.1 LTSSM
USB3.1 Technical and
Electrical measurement
Challenges 7
Page
PING LFPS
Toggles CMM
8
CP1/10
Rj
CP0/9
Dj
USB3.1 Technical and
Electrical measurement
Challenges
TX Testing Requirements: Polling.LFPS to compliance mode
Page
LFPS – SCD1 & SCD2 – tRepeat Modulation
• tRepeat is modulated to express 0
(short) and 1 (long)
• SCD1 0010
SCD2 1101
• LSb first
• SCD1.LFPS (4’b0100), and
SCD2.LFPS (4’b1011)
• SuperSpeed+ identity check
9
USB3.1 Technical and
Electrical measurement
Challenges
Page
LFPS Based PWM Signaling (LBPM) Encoding
• LSb first
• Rate (speed and lane) announcement and negotiation
• Repeater declaration
• Power state transition in repeater
• Can be expanded to:
• VBus control on/off, overcurrent sensing
• Power delivery
• Vendor specific operation
10
USB3.1 Technical and
Electrical measurement
Challenges
Page
Keysight USB 3.1 TX Compliance Application
USB3.1 Technical and
Electrical measurement
Challenges 11
Keysight solution features:
Support USB3.1 Gen1/Gen2
USB-IF Sigtest & Keysight SDA
algorithm
CTLE Adc scan
Support live & saved
waveforms
USB-IF and customer’s
embedded transfer function
External instrument for SCD1/2,
LBPM trigger and Compliance
Pattern toggle
Page
Keysight USB 3.1 TX Compliance Application
USB3.1 Technical and
Electrical measurement
Challenges 12
Gen 1 test items, LFPS, SSC, eye
mask, Jitter
Select/Scan for optimal Adc of CTLE
Eye mask and Jitter test by
SDA algorithm
Eye mask and Jitter test by
SigTest algorithm
SSC test items
Gen2 LFPS, tRepeat, tBurst , tPMW,
tLFPS_0, tLFPS_1
Page
USB3.1 Technical and
Electrical measurement
Challenges
Transmitter test requirements
0.141
0.671
13
Updated by ECN
Ref. test Channel
Ref. cable
DUT
TP1
HOST or DEVICE
Embed ref. Cable Embed Loss Sim. CTLE + DFE De-embed fixture
Measurement +SW
Page
Used to test for worst case channel conditions
• Die to die target is 23 dB @ 5 GHz
• Symmetric loss for host and device
• Host/device exceeding 8.5 dB may need
repeater
USB 3.1 Compliance Channels USB 3.0 Compliance Channels
8.5 dB 8.5 dB 6 dB
Standard connector:
• Channel loss will dominate
• 11” PCB trace for device testing
• 5” PCB trace for host testing
• 3 meter USB 3.0 cable
Micro connector:
• Channel loss will dominate
• 11” PCB trace for device testing
• 5” PCB trace for host testing
• 1 meter USB 3.0 cable
Tethered:
• Channel loss will dominate
• 11” PCB trace for device testing
• 5” PCB trace for host testing
• short USB 3.0 cable
Short Channel:
• no cable and shortest possible PCB traces
Compliance Channels
14
USB3.1 Technical and
Electrical measurement
Challenges
Page
InfiniiSim example: Gen1 Tethered Device Channel • Import channel s-parameters
• Add channel loss –
TopTX_Backpanel.s4p (simulate)
• Remove fixture loss –
U7242_shortcable_forDev.s4p
(measured)
• Result is Tethered TX response
15
Page
Gen2 Reference Receiver Equalization Multi-level CTLE + 1 tap DFE
Eye at end of channel
CTLE (-6dB)
+ 1 tap DFE
• Eye closed at end of channel
• Need equalizer to open eye
• Iterate through multiple CTLE settings for best eye opening
16
USB3.1 Technical and
Electrical measurement
Challenges
Page
Report example
USB3.1 Technical and
Electrical measurement
Challenges 17
10G Eye measurement with Adc scan
Adc=0
Adc=-1
Adc=-3
USB 3.1 Receiver Testing Challenges
• Spec. requirement for Rx Tolerance test • Rx Jitter tolerance Calibration • Loopback sequence • Keysight Receiver test solutions
USB3.1 Technical and
Electrical measurement
Challenges 18 Page
0.1
1
10
100
0.1 1 10 100
Sin
usoid
al Jitte
r [U
I]
Sinusoidal Jitter Frequency [MHz]
Jitter Tolerance USB SuperSpeedDevice
Max PassedJitter
Jitter CapabilityTest Setup
Min Spec
Page
Receiver Jitter Tolerance curve
USB3.1 Technical and
Electrical measurement
Challenges 19
(0.5MHz, 2)
(4.9MHz,0.2)
(50MHz,0.2)
(1MHz,1)
(2MHz,0.5)
0.17
UI
(0.5MHz, 2.56)
(7.5MHz,0.17) (100MHz,0.17)
(1MHz,0.1.28)
(2MHz,0.64)
(4MHz,0.32)
(50MHz,0.17)
0.14
UI
Gen1 vs Gen2
• Rx Jtol RJ & Tx EQ updated by
ECN
• Gen 2 define 7 SJ points in spec.
• Gen 1 define 5 SJ points in Spec,
but 8 points in CTS
RJpp
RJpp
Page
USB 3.0 Jitter Tolerance Calibration
1. De-Emphasis Calibration
• Before Fixture and 3m cable
• Eye diagram, Transition bit vs Non-transition bit
• Either cursor based or histogram based measurement
2. RJ Cal (CP1)
3. SJ Cal (CP0)
• Two step approach via TJ SJ = TJ - TJbase
4. Eye Height Calibration (CP0)
5. TJ Verification (CP0)
Note:
2~5 steps through Fixture and 3m cable &
SIGTEST based measurement
USB3.1 Technical and
Electrical measurement
Challenges 20
Host Cal. setup SigTest measurement
jBERT B or M8020A Device Cal. setup
Page
– Like the calibration for USB 3.0 the calibration for USB 3.1 will most
likely be done using SIGTEST measurements at the end of the test
channel
– Pre-calibration for pre-shoot and de-emphasis, RJ, SJ most likely
will use similar approach
– A calibration which measures eye height (EH) and eye width (EW)
using SIGTEST and adjust EH and EW by tuning stress parameters
is likely
USB 3.1 Gen 2 Receiver Jitter Tolerance
21
Expected changes
USB3.1 Technical and
Electrical measurement
Challenges
Page
Reference Calibration steps (CTS not final)
22
The latest discussion in Oct. 2014
8.5 dB 8.5 dB 6 dB
– Calibrate Vdiff pp 800mV, pre-shoot 2.2dB and de-emphasis -3.1dB using the Clk/64 pattern. All jitter off.
Measure the waveform directly at the output of the generator (TP1).
– Calibrate RJ to 1ps rms using CP10. Measure the waveform directly at the output of the generator (TP1).
– Calibrate SJ (@100MHz) to 17ps using CP9. Measure the waveform directly at the output of the generator
(TP1).
– Connect the 23dB channel and measure EH and EW at its end (TP2) using CP9. Keep the calibrated RJ,
SJ Vdiff, de-emphasis and pre-shoot from the previous calibration
– Adjust Vdiff and de-emphasis until EH is 70mV (@BER 1E-6) and EW is 28.6ps (@BER 1E-12)
– The eye height & eye width value for Compliance Channel 14.5dB is still under development and
discussion
USB3.1 Technical and
Electrical measurement
Challenges
TP1
Page
USB 3.X LTSSM
TX compliance modes
RX testing - loopback
USB3.1 Technical and
Electrical measurement
Challenges 23
Page
Typical USB 3.0 Link Turn-on Sequence
J-BERT’s sequence trigger can be used to trigger scope captures for each trainings step
in combination with scope’s protocol decode very helpful for debugging a trainings
sequence
Power-up
Rx.
Detect.
Reset
Rx.
Detect.
Active
Polling.
LFPS
Polling.
RxEQ
Polling.
Active
Polling.
Config-
uration
Polling.
Idle
Polling.
Config-
uration
Polling.
Idle
Loopback
Loopback
warm
reset
warm reset
de-assert
termination
detected
LFPS
handshake
TSEQ
transmitted
TS1
received
TS2
received if directed
multiple states
Host
Device
LTSSM states:
Compliance
Rx.
Detect.
Reset
Rx.
Detect.
Active
Polling.
LFPS
Polling.
RxEQ
Polling.
Active
Power-up
USB3.1 Technical and
Electrical measurement
Challenges 24
Page
Typical USB 3.1 Link Turn-on Sequence
J-BERT’s sequence trigger can be used to trigger scope captures for
each trainings step very helpful for debugging a trainings sequence
Power-
up
Rx.
Detect.
Reset
Rx.
Detect.
Active
Polling.
LFPS
Polling.
RxEQ
Polling.
Active
Polling.
Config-
uration
Polling.
Idle
Polling.
Config-
uration
Polling.
Idle
Loop-
back
Loop-
back
warm
reset
warm reset
de-assert
termination
detected
SCD1 LFPS
handshake
TSEQ
transmitted
TS1
received
TS2
received if directed
multiple states
LTSSM states:
Comp-
liance
Rx.
Detect.
Reset
Rx.
Detect.
Active
Polling.
LFPS
Polling.
RxEQ
Polling.
Active
Power-
up
Polling.
LFPS
Plus
SCD2 LFPS
handshake
Polling.
LFPS
Plus
Polling.
Port-
match
PHY
Capability
LBPM
handshake
Polling.
Port-
match
Polling.
Port
Config
PHY
Ready
LBPM
handshake
Polling.
Port
Config
SCD1 SCD2 LBPM PHY Capability/ PHY Ready
USB3.1 Technical and
Electrical measurement
Challenges 25
Page
Loopback Training – USB 3.1 LTS tool • USB Link Training
Suite is a trainings sequence generation tool for USB3.1 Gen1/2
• Easy manipulation of
• SCD1/SCD2/LBPM cycles
• TSEQ count
• TS1 count
• TS2 count
• LFPS parameters adjustment:
• tPeriod, tBurst, tRepeat, tPWM….
• Choice of:
• Power On sequence
• Warm Reset sequence
USB3.1 Technical and
Electrical measurement
Challenges 26
Page
Loopback Training – Gen1 in Valiframe
• A trainings
sequence
generation tool is
part of the N5990A
Test Automation SW
for USB 3.0
• Easy manipulation
of
• LFPS cycles
• TSEQ count
• TS1 count
• TS2 count
• Choice of:
• Power On sequence
• Warm Reset sequence
USB3.1 Technical and
Electrical measurement
Challenges 27
Page
USB 3.x 5Gb/s 8b/10b Coding
• 8b/10b coding after scrambling
• Least significant bit first!
• Same scrambler polynomial as PCIE 2.5G & 5G: G(X) = X16 + X5 + X4 + X3 + 1
• Command block scrambler rules
• SKP symbols bypass and do not advance the scrambler
• K symbols are not scrambled but advance scrambler except for the SKP symbol
• D symbols advance scrambler and are scrambled except D symbols within a Training Sequence Ordered Set
• K28.5 (comma) resets scrambler
• K28.5(comma), K28.7 and K28.1 (SKP) can be used to gain symbol lock
• A symbol is always 10 bit long after coding
USB3.1 Technical and
Electrical measurement
Challenges 28
Page
128b/132b Coding
• 4 bit header to avoid link reset problems from PCIe 8G
• 0011 marks a data block and 1100 a command block
• Header and symbols are least significant bit first!
• SYNC block is used to reset scrambler and to gain block alignment
• Same scrambler polynomial as PCIE 8G: G(X) = X23 + X21 + X16 + X8 + X5 + X2 + 1 Block header bypasses scrambler and does not advance scrambler
• Command block scrambler rules
• TS1, TS2, TSEQ
- symbol 0 bypasses but advances scrambler
- symbols 1 to 13 are scrambled
- symbols 14 and 15 bypass scrambler but advance scrambler if used for DC balance otherwise they are scrambled
• SKP OS bypasses scrambler and does not advance scrambler
• SDS OS bypasses scrambler but advance scrambler
• All blocks are 132 bit long except SKP OS which can be shorter or longer
• SKP END symbol is used to regain block alignment
USB3.1 Technical and
Electrical measurement
Challenges 29
Page
M8000 HW coding, Scrambling capability
30
Pattern editor support 8b/10b & 128b/132b coding
USB 3.1 Gen2
USB 3.1 Gen1
SKP
TSEQ
USB3.1 Technical and
Electrical measurement
Challenges
Page
USB 3.1 Independent Clock Domains
– In many standards there is no common clock. Therefore in a communication
system each product has its own oscillator
– Typical host/device configuration in USB 3.0, SATA, SAS, etc:
– Clock A and clock B will never be identical, often SSC is used
– The elastic buffer compensates the slight differences in data rate (i.e.
performs re-timing)
Clock compensation
Device
Receiver
FF EQ
Loop-
back
Device
function
CDR
Transmitter
Host
Loop-
back Device
function
Receiver
FF EQ
CDR
Transmitter
Channel
Elastic
buffer
Elastic
buffer
Clock
B
Clock
A
USB3.1 Technical and
Electrical measurement
Challenges 31
Page
USB 3.1 Independent Clock Domains
fB < fA If clock B is running slower symbols from the incoming data must be dropped. Therefore the incoming data already contains filler primitives
fB> fA If clock B is faster filler primitives must be inserted to prevent the buffer from running empty
Filler Primitives Filler primitives are symbols in
the data stream that carry no
information
Device
Receiver
FF EQ
Loop-
back
Device
function
CDR
Transmitter
Host
Loop-
back Device
function
Receiver
FF EQ
CDR
Transmitter
Channel
Elastic
buffer
Elastic
buffer
Clock
B
Clock
A
data-symbol
filler-primitive
original data and filler symbols sent with fA
Retimed data with fB < fA
fB> fA
USB3.1 Technical and
Electrical measurement
Challenges 32
Page
Gen 1 & Gen 2 Skip Order Set (SKP OS)
• SKP character: K28.1
• Always in pairs: K28.1 K28.1
• Pairs can be attached directly behind each other
• SKP SKP insertion every 354 dwords
33
Gen1: 8b/10b SKP OS symbol is fixed length
• SKP OS: 4n *SKPs + SKPEND symbol + 3 symbols for LFSR seed state;
n = 1 to 9
• SKP..CCh
• SKPEND..33h
• SKP OS in average every 22 blocks
The variable length of SKP OS is challenging for BERT EDs
Gen2: 128b/132b SKP OS symbol is varying length
USB3.1 Technical and
Electrical measurement
Challenges
Page
J-BERT Error Detection Modes Summarized Both N4903B and M8020B, provide error detector options to
deal with clock compensation and SKP OS filtering
USB 3.1 Gen1 encoded data (8b/10b) :
• Filtering of filler primitives, in case of USB 3.x 5G filtering of SKP
(K28.1)
• Expected and received data comparison in 8b domain disparity
errors are not counted as symbol errors but are reported separately
• N4903B-A02 and M8020A-0S2
USB 3.1 Gen2 encoded data (128b/132b) :
• Filtering of SKP OS with variable SKP counts
• Bit error counter
• N4903B-A03 and M8020A-0S2
USB3.1 Technical and
Electrical measurement
Challenges 34
M8020A-0S2
N4903B-A03
N4903B-A02
Page
USB 3.1 Gen1/Gen2 Receiver Test Setup – N4903B/N4916B
Key capabilities:
• Analysis of coded & retimed data with SER/FER analysis (option A02)
• Option A03 support 128b/132b SKP OS filtering for BER testing
• Simplified loopback training with pattern sequencer with 120 blocks ,
• Generates calibrated stress conditions for RX test (SSC, SJ, RJ, De-emphasis, ISI)
• Support LFPS Rx testing by channel add method
• N4788A CDR useful for increased CDR loop bandwidth
N4903B configuration:
• N4903B with C13, J10, J11, A02,
A03, 002
• N4916B, N4915A-010
• N5990A USB Valiframe SW
• BitifEye USB 3.1 LTS
Rx LFPS compliance test Rx tolerance compliance test
Gen 2 test
fixtures/cables are not
ready yet!
USB3.1 Technical and
Electrical measurement
Challenges 35
Page
USB 3.1 Gen1/Gen2 Receiver Test Setup – M8020A
Key capabilities:
• Analysis of coded & retimed data with SER/FER analysis (option 0S2)
• supporting 8b/10b and 128b/132b HW coding and decoding as well as HW scrambling
• Generates calibrated stress conditions for RX test (SSC, SJ, RJ, De-emphasis, ISI)
• Emulate LFPS 3-level signals with built-in electrical idle for loopback training and via channel add of
second output channel (option 0G2) for fast transition into and outof electrical idle for LFPS tests
M8020A jBERT configuration:
• M8020A with M8041A-C16, -
0S2, -0G3, -0G4, (-0G2),
M8070A-0TP and M8020A-BU1
• N5990A USB Valiframe
• BitifEye USB 3.1 LTS
Gen 2 test
fixtures/cables are
not ready yet!
USB3.1 Technical and
Electrical measurement
Challenges 36
Page
USB 3.0 Reciever Test Automation w/ N5990A
Only with channel add
setup for N4903B
USB3.1 Technical and
Electrical measurement
Challenges
37
Page
Receiver Characterization Example
• Automated
instrument
control for:
• Setup calibration
• Compliance test
• Characterization
test
• Support for
debugging
• Operator guidance
• Sophisticated test
reports
• Controls J-BERT,
Oscilloscope.
• Supports full product
characterization
including transmitter
measurements
USB3.1 Technical and
Electrical measurement
Challenges 38
Type C Connector, Power Delivery, and Alt Modes
Source: IDF14 (NETS002), Intel
USB3.1 Technical and
Electrical measurement
Challenges 39 Page
Page
Type C Connector Functional highlights
• Lot of new pins
• Accessory Mode
• Alternate Modes (DP 1.3, MHL 4.0, TBT)
• Two power source, Vbus and Vconn
• Power Delivery to 100 Watts
• Flipping and swapping
Sideband
Use (AUX
+/-for DP Alt
Mode)
USB3.1 Technical and
Electrical measurement
Challenges 40
Page
The Key to the Type C USB Type-C Configuration Channel (CC)
• Detect attach of USB ports
• Resolve cable orientation and twist connections to
establish USB data bus routing
• Establish “host” and “device” roles between two attached
ports
• Discover and configure Vbus: USB Type-C Current
modes or USB Power Delivery
• Configure Vconn
• Discover and configure optional Alternate and Accessory
modes
USB3.1 Technical and
Electrical measurement
Challenges 41
Page
Type C Functional Pin-out
Looking into the product receptacle :
Looking into the cable or product plug :
USB3.1 Technical and
Electrical measurement
Challenges 42
Page
Type-C
Type-C Functional Model – Un-flipped straight through CC wire determines the orientation through the cable: P(1) <->P(1)
USB3.1 Technical and
Electrical measurement
Challenges 43
Page
Type-C
Type-C Functional Model – Un-flipped twisted through CC wire determines the orientation through the cable: P(1) <->P(2)
USB3.1 Technical and
Electrical measurement
Challenges 44
Page
Type-C Functional Model – Direct Connect Un-flipped-Position (1)
Type-C
Plugs Type-C
Plugs Device Device
Flipped-Position (2)
USB3.1 Technical and
Electrical measurement
Challenges 45
Page
Type-C Host Detected Connection states Pull-Up/Pull-Down CC Model
Powered Cables introduce Ra at
the “unwired” CC pins which are
used to indicate the need for Vconn
over one of those pins
USB3.1 Technical and
Electrical measurement
Challenges 46
Page
Device Connection Basic DFP meet Basic UFP
• Rp used to sense device attach
• Advertise Type-C current
• Rd used to sense UFP attach
• Advertise Type-C current
DFP default : Host , Power provider UFP default : Device , Power consumer
USB3.1 Technical and
Electrical measurement
Challenges 47
Page
USB Type-C Power Options
48
Sink/source can be swapped, power direction no longer fixed
USB3.1 Technical
and Electrical
measurement
Challenges
Page
USB Power Delivery Architecture Overview and Signaling Provider Consumer
• Over Vbus for USB Type A and B --- BFSK (Binary Frequency Shift Keying)
• Over CC for USB Type-C --- BMC (Biphase Mark Coding)
• Voltage, Current and Direction negotiated
• Half Duplex, Bitrate=300kbps, 4b/5b coding
USB3.1 Technical and
Electrical measurement
Challenges 49
Page
BFSK and BMC Vbus System BFSK over Vbus (Type A and B), BMC over CC ( Type-C)
USB3.1 Technical and
Electrical measurement
Challenges 50
Page
USB PD Signaling
51
Type-C Connector over CC : Biphase Mark Coding
USB3.1 Technical and
Electrical measurement
Challenges
Page
USB PD Signaling
52
Type-A/B Connector over VBUS : BFSK
• Binary Frequency Shift Keying
• 23.2MHz Carrier
• 150mV AC coupled
• FSK Modulation, Δf =500 KHz
• Bit rate = 300kpbs
• 4b/5b coding
USB3.1 Technical and
Electrical measurement
Challenges
Page
Test solution for Power Delivery Keysight partnering with GRL for PD electrical analysis tool development
• USB-PD eMark Cable Testing
• CC Electrical measurement & Protocol decode testing
• USB-PD Power Provider Stress
• USB-PD Power Consumer test
• Wilder Technologies developing new PD breakout fixture
GRL–USB-PD
USB3.1 Technical and
Electrical measurement
Challenges 53
Page
Test solution for Power Delivery
USB3.1 Technical and
Electrical measurement
Challenges 54
Test Setup 2: CC Electrical & Protocol Decode Testing
10X Passive
or Diff Probe
Note: Scope GND needs to be established on
only one side of link
Keysight Scope
With
GRL-USB-PD
CH1 CH2
USB 3.1 Cable/Connector Compliance test
USB3.1 Technical and
Electrical measurement
Challenges 55 Page
Page
USB 3.1 Cable Assembly
56
Enhanced SuperSpeed signal pairs
•Typically Shielded Differential Pair
(SDP), twisted, or coaxial signal pairs
•Shield needed for signal integrity and
EMI performance
D+/D- signal pair
•Typically unshielded twisted pair (UTP)
•Intended to transmit the USB 2.0
signals
• Backwards compatible with existing USB 3.0 connectors
• Cable assembly insertion loss budget >= -6 dB @ 5 GHz
• Targeted for 1 meter, not 3 meters
• Longer than 1 meter may require an active cable
USB3.1 Technical and
Electrical measurement
Challenges
Page
USB Type-C Cable/Connector Compliance Test Solution Overview
57
• ALL normative and informative parameters specified for USB Type-C
cable/connector compliance testing can be measured with the ENA Option TDR.
Traditional
Solution New Solution
Vector
Network
Analyzer
(VNA)
TDR
Scope
•ALL parameters can
be measured with
ENA Option TDR
One-box
Solution !!
Frequency Domain •D+/D- Pair Attenuation (USB 2.0)
•ILfitatNq, IMR, IXT, IRL, Differential to Common Mode
Conversion, IXT on D+/D-
•Shielding Effectiveness
•Insertion Loss (Informative)
•Return Loss (Informative)
•NEXT/FEXT between Gen2 Pairs (Informative)
•NEXT/FEXT between D+/D- and Gen2 Pairs (Informative)
•[Raw Cable] Insertion Loss (Informative)
•[Mated Connector] Insertion Loss (Informative)
•[Mated Connector] Return Loss (Informative)
•[Mated Connector] NEXT/FEXT between Gen2 Pairs
(Informative)
•[Mated Connector] NEXT/FEXT between D+/D- and Gen2
Pairs (Informative)
•[Mated Connector] Differential to Common Mode Conversion
(Informative)
•Low Speed Signal Requirements
Time Domain •D+/D- Impedance (USB 2.0)
•D+/D- Propagation Delay (USB 2.0)
•D+/D- Intra-pair Skew (USB 2.0)
•Differential Impedance
•[Raw Cable] Characteristic Impedance (Informative)
•[Raw Cable] Intra-Pair Skew (Informative)
•[Mated Connector] Diff. Impedance (Informative)
•Low-Speed Signal Requirements
* Note: Compliance standard tool from USB-IF is required for pass/fail judgment of ILfitatNq, IMR, IXT, IRL and IXT on D+/D- tests
USB Type-C CabCon
Compliance Test
Page
USB Type-C Cable/Connector Compliance Test Configuration
58
www.keysight.com/find/ena-tdr_compliance
www.keysight.com/find/ena-tdr_usb3-cabcon
•Method of Implementation (MOI)
document and state files (4K5)
available for download on
Keysight.com (planned) MOI (Method of Implementation)
Step-by-step procedure on
how to measure the specified
parameters in the specification
document using ENA Option
TDR.
•ENA Mainframe (*1)
•E5071C-4K5: 4-port, 300 kHz to 20 GHz
•Enhanced Time Domain Analysis Option (E5071C-TDR)
•ECal Module (N4433A)
*1: Type-C cable/connector requires measurements up to 15 GHz.
*2: The list above includes the major equipment required. Please contact our sales representative for configuration details.
USB Type-C CabCon
Compliance Test
Test Fixtures
Fixtures for testing USB 3.1/Type-C
connectors and cable assemblies are
available for purchase through
LUXSHAREICT. This information will be
made available through USB-IF web
page.
http://web.luxshare-
ict.com/en/ProductList.php?id1=22&id2=92
Page
USB Type-C Cable/Connector Compliance Test [SS & D+/D-] Measurement Parameters (Normative & Informative)
59
USB Type-C CabCon
Compliance Test
D+/D- Intra-
Pair Skew
(T31, T42)
Time Domain Frequency Domain
Diff. Crosstalk (SS) (Sdd21)
Diff. Crosstalk
(D+/D- & SS) (Sdd21)
Diff. Insertion Loss (Sdd21)
Diff. Return Loss (Sdd11)
D+/D-
Propagation
Delay (Tdd21) Shielding Effectiveness
(Sds21, Scs21)
D+/D- Pair
Attenuation
(Sdd21)
[Raw Cable]
Characteristic
Impedance
(Tdd11, Tdd22)
ILfitatNq, IMR, IXT,
IRL, Mode
Conversion
(s4p files)
[Mated Connector]
Diff. Insertion Loss (Sdd21)
[Mated Connector]
Diff. Return Loss (Sdd11)
[Mated Connector]
Diff. Crosstalk
(SS) (Sdd21)
[Mated Connector]
Diff. Crosstalk
(D+/D- & SS) (Sdd21)
D+/D- Impedance
(Tdd11, Tdd22)
[Raw Cable]
Intra-Pair
Skew
(T31, T42)
[Type-C to Type-C Passive Cable Assemblies]
[Raw Cable]
Diff. Insertion Loss (Sdd21)
[Mated Connector]
Mode Conversion (Scd21)
[Mated Connector]
Diff. Impedance
(Tdd11, Tdd22)
Compliance
Tool
Page
New Compliance Methodology Channel Metrics There are three signal integrity impairments that impact the end-to-end link
performance: attenuation, reflection and crosstalk.
Three parameters are used as the channel metrics to represent these three
impairments:
• Insertion loss fit at Nyquist frequency (ILfitatNq)
• Integrated multi-reflection (IMR)
• Integrated crosstalk (IXT)
60
USB3.1 Technical and
Electrical measurement
Challenges
Page 61
Pass/Fail Criteria
• eH = fH(ILfitatNq, IMR, IXT) > 0
• eW = fW(ILfitatNq, IMR, IXT) > 0
AND
• ILfitatNq ≥ -22 dB
• IMR ≤ 60 mV
• IXT ≤ 25 mV
Reference: USB-IF Technical White Papers http://www.usb.org/developers/docs/whitepapers/
“Methodology Used to Determine SuperSpeed USB 10 Gbps (USB 3.1) - Gen2 Channel and Cable Assembly High Speed Compliance”
New Compliance Methodology Channel Margin
Based on channel eye height (eH) and/or eye width (eW) instead of component S-
parameters profiles.
USB3.1 Technical and
Electrical measurement
Challenges
Page
2. Import the touchstone files into the USB 3.1
Standard Tool to perform pass/fail judgment
for all combinations of reference host and
device.
62
2
2
2
USB 2.0 Pair
Half-Duplex
Gen2 Pair
Full Simplex
Gen2 Pair
Full Simplex
PWR (1), GND (1)
Host CabCon Device
6/ea s4p files
1. Measure S-parameters of all
six combinations of the Gen2
differential pairs.
IXT
IMR
New Compliance Methodology Procedure
USB3.1 Technical and
Electrical measurement
Challenges
Page
Keysight USB 3.1 Total Test Solution Interconnect Test
Receiver Test Transmitter Test
DSOX92504A
Infiniium
Scope
SW
HW
Fixture
DUT
M8020A/N4903B J-BERT
High-Performance Serial
BERT
N5990A
USB Compliance
Test Software
E5071C ENA Option TDR
U7243B
USB Compliance
Test Software
TBD
Tx Test Fixture
TBD
Cable/Connector
Test Fixture
Tx Rx
Tx
TBD
Rx Test Fixture
from USB-IF
Tx
Rx Cable
63
USB3.1 Technical and
Electrical measurement
Challenges
Page
Keysight is the leading USB solution provider to test labs worldwide
Approved labs are listed at www.usb.org/developers/compliance/labs
USA:
• GRL
• Allion
• NTS
• NSTL
• MCCI
• Contech Research
Europe:
• Testronics (Belgium)
Asia:
• GRL (India)
• TTA (Korea)
• Allion (Japan / China / Taiwan)
• XXCAL (Japan)
• ETC (Taiwan)
• SGS (Taiwan)
• STC (Hong Kong)
Note: SuperSpeed certified test labs in RED.
USB3.1 Technical and
Electrical measurement
Challenges 64
Page 65
USB3.1 Technical and
Electrical measurement
Challenges
台灣是德科技股份有限公司 以是為本 以德致遠 專注量測75載
Master the Mobile Computing and MIPI Test Challenges 掌握行動運算科技及克服MIPI測試挑戰
Instructor: 林昭彥
Page
Agenda
Overview
– MIPI PHY roadmap
– PHY electrical review
– TX update
– Return loss update
– RX update
2
Page
MIPI = Mobile Industry Processor Interface -
• Structure the intestines of mobile
devices ranging from smartphones
to wireless-enabled tablets and
netbooks
• Benefit the entire mobile industry by
establishing standards for hardware
and software interfaces
• Enabling reuse and compatibility
making system integration less
burdensome
• The distinctive requirements of
mobile terminals drive the
development of MIPI Specifications
- Power saving / battery life
- Bandwidth on demand
3
Goals
MIPI M-PHY Receiver Test Webinar
August 2013
Page
MIPI’s Layered Approach for Application Standards
4
Page
Google Project ARA
5
Page
ARA Architecture
Legacy Phone Architecture
ARA Phone Architecture
6
Page
Agenda
Overview
– MIPI PHY roadmap
– PHY electrical review
– TX update
– Return loss update
– RX update
7
Page
Why Three Different PHY-layer Standards?
– D-PHY
• Used for camera (CSI-2) and display (DSI) applications
• Source synchronous, forwarded ½ rate clock
• Electrical specifications (parasitic capacitances and return loss (RL)) allow usage of
established, relatively inexpensive semiconductor process
• Complex signaling, different amplitudes and data format for Low Power (LP) and High
Speed (HS) mode and non-differential “pattern sequence” signaling transition from LP
to HS-mode and vice versa
• Rev. 1.0 / 1.1 with a continuous data rate range up to 1.0 / 1.5Gb/s respectively
– M-PHY
• Proposed high BW successor of D-PHY addressing camera and display applications
• Embedded clock and PLL-type CDR
• Discrete data rates (Gears) up to approximately 12Gb/s; sufficient for quite a while
• Differential signaling and same amplitude in both HS- and LP- mode
8
2013 and before
Page
Why Three Different PHY-layer standards?
– M-PHY
• Reluctance of camera group to adapt M-PHY because of
- Specified lower parasitic capacitance / better RL demands more expensive
semiconductor process than for D-PHY
- Discrete instead a “agile” data rates
- 8B/10B coding overhead of 25%
– C-PHY started
• New 3-wire / 3 level data format allowing transmission of >1 bit / symbol
• Embedded clock, CR based on logic and encoding rules
• HS mode w/ toggle rates reaching continuously up to 2.5Gbaud / 5.75Gb/s
• LP mode identical to D-Phy
• Even more complex signaling (HS mode3 w/ 3 wire 3-level signaling) level)
– D-PHY extended
• Rev. 1.2 w/ max data rate 2.5Gbs (achieved through RX deskew)
• Rev. 2.x started, data rate project beyond 4.5 Gb/s (6.5Gb/s)
9
2014 onwards
Page
Agenda
Overview
– MIPI PHY roadmap
– PHY electrical review
– TX update
– Return loss update
– RX update
10
Page
M-PHY Link Example
MIPI M-PHY options
– High speed and (lower speed) low power mode (same as in D-PHY)
– High and low voltage swing operation can be commonly selected for both modes
– Terminated (100 Ohm) or not terminated operation (for power saving purposes) can
individually be selected per mode
11
MIPI M-PHY
• Lanes are unidirectional
• Signaling: differential
• 8B/10B coded
• Transmisssion may appear in burst
• Embedded clock
• PLL type CDR, needs to synch at the beginning of every burst
M-TX
M-TX
M-RX
M-RX
M-TX
M-RX
LA
NE
MA
NA
GE
ME
NT
PINsLINE
LANE
LINK
PINsLINE
PINs
LINE
PINs
PINs
PINs
LA
NE
MA
NA
GE
ME
NT
TXDP
TXDN
RXDP
RXDN
TXDP
TXDN
TXDP
TXDN
RXDP
RXDN
RXDP
RXDN
SUB-LINK
LANE
SUB-LINK
LINK
M-TX PIF
M-TX PIF
M-RX PIF
M-RX PIF
M-RX PIF
M-TX PIF
M-PORT
M-PORT
Page
MIPI M-PHY Data Rates and Module Types
• High Speed Gears / data rates valid for both module types
• Type II module only used for Dig_RF_v4
12
Hig
h S
pee
d M
ode
s
Low
Pow
er
Modes
NT = Not Terminated
RT = Resistively terminated
fref = 19.2, 26, 38.4 or 52 MHz
Page
M-PHY Gear 4 Definitions
• ESG Focus are:
• Channel Loss – keep the same effective trace length as HS-G3
• Channel EQ Proposals:
- 2 tap TX EQ
- RX EQ (CTLE + 1 tap DFE, adaptation preferred, random
training pattern)
• TX/RX eye diagrams (Reference EQ, reference package, BER
target)
• CDR bandwidth requirement
• EMI analysis
13
Page
Outlook MIPI M-PHY / M-PHY Spec Roadmap
– V4.0 WG approved draft October 31st 2014
– V4.0 Spec December 2014
• Aligns with UniPro 1.8 schedule, which depends on 8b10b
– V4.1 Spec proposed for October 2015
• Tighten spec/conformance of digital interface (RMMI)
• Protocol/PHY optimizations
– Next Gen M-PHY spec ~December 2016
• 20Gb/s and 23.2Gb/s data rates per LANE
• Advanced encoding and scrambling
• Optional data rate granularity
• Short channel reach applications (<20dB loss channel)
• Support AC-coupled channels
• Change jitter BER from 1e-10 to 1e-12
14
Page
D-PHY Universal Lane Module Functions
– Lane consisting of 2 wires, Dp and Dn
– TXs and Rxs: Bidirectional
– Contention Detection (LP only)
– Two set‘s of TXs / RXs (HS & LP)
– HS-mode:
• Small Amplitude, terminated (option)
• Data format: NRZ
• Signaling: differential
– LP-mode:
• Large Amplitude, unterminated
• Data format: RZ
• Signaling: non-differential
15
RX
Dp
Dn
TX
LP-TX
HS-RX
CD
PPI(appendix)
RT
Data
Clock
Ctrl
Protocol Side
RTR T
Line Side
LP-RX
LP-CD
Lane
Control
and
Interface
Logic
HS-TX
Page
D-PHY Two Data Lane Phy Configuration
– Source synchronous forwarded double data rate clocking
– Data-rate completely agile, no discrete operating frequencies, continous range
– RX testing is basically stressing set-up- and hold- time conditions
(eye closure mainly due to DDJ and skew between Data and Clock)
16
Ref Clock
D-PHY Master Clock Lane Module
D-PHYMaster Data Lane Module
ClockMultiplier
Unit
PPI
APPI = Abstracted PHY-Protocol Interface (complete PHY, all Lanes)PPI = PHY Protocol Interface (per Lane, some signals can be shared with multiple Lanes)
PHY Adapter
Layer
Master Side
Controls
D-PHYSlave Clock Lane Module
D-PHYSlave Data Lane Module
I Q
Slave Side
D-PHYSlave Data Lane Module
D-PHYMaster Data Lane Module
PPI
PPI
APPI
PHY
PPI
PHY AdapterLayer
PPI
PPI
PHY
APPI
Ref Clock
D-PHY Master Clock Lane Module
D-PHYMaster Data Lane Module
ClockMultiplier
Unit
PPI
APPI = Abstracted PHY-Protocol Interface (complete PHY, all Lanes)PPI = PHY Protocol Interface (per Lane, some signals can be shared with multiple Lanes)
PHY Adapter
Layer
Master Side
Controls
D-PHYSlave Clock Lane Module
D-PHYSlave Data Lane Module
I Q
Slave Side
D-PHYSlave Data Lane Module
D-PHYMaster Data Lane Module
PPI
PPI
APPI
PHY
PPI
PHY AdapterLayer
PPI
PPI
PHY
APPI
Page
D-PHY Physical Layer Timing Diagram
Transition LP to HS mode, HS_clk active earlier / longer
High speed mode,
Differential signaling, 100 ohm termination, source synchronous DDR clocking
Low power mode
Unterminated, not differential, clock embedded within data
17
Page
D-PHY 1.2
18
RX Deskew enables Data Rate up to 2.5 Gbit/s
Skew Calibration Normal Mode
A. HS Sync-Sequence for HS Skew-Calibration
(‘11111111_11111111’)
B. Same as clock lane (‘01010101’)
→ Performs HS Skew-Calibration in RX side
C. HS Sync-Sequence for normal HS mode (‘00011101’)
D. HS payload data
Page
Normal Mode and Skew Calibration
19
000 111 0 1
16'h FFFF
LP-11
THS-ZERO THS-SYNC
TEOT
THS-TRAIL THS-EXIT
Disconnect
Terminator
THS-SKIP
TREOT
THS-SETTLE
TLPX TCLK-PREPARE
TCLK-SETTLE
TCLK-ZERO TCLK-PRE
TLPX THS-PREPARE
TCLK-TERM-EN
TD-TERM-EN
Clock Lane
Dp/Dn
Data Lane
Dp/Dn
TCLK-POST
TCLK-TRAIL
TEOT
TCLK-MISS
LP-11
THS-ZERO
TEOT
THS-TRAIL THS-EXIT
Disconnect
Terminator
THS-SKIP
TREOT
THS-SETTLE
TLPX TCLK-PREPARE
TCLK-SETTLE
TCLK-ZERO TCLK-PRE
TLPX THS-PREPARE
TCLK-TERM-EN
TD-TERM-EN
Clock Lane
Dp/Dn
Data Lane
Dp/Dn
TCLK-POST
TCLK-TRAIL
TEOT
TCLK-MISS
0 1 0 1 0 1 0 1 0 1 0 1
TSKEWCAL-SYNC TSKEWCAL
High-Speed Data Transmission in Normal Mode
High-Speed Skew Calibration
Page
D-PHY Outlook
– D-PHY 2.0 (2015)
• High Frequency Clock(DDR) forwarded architecture targeted at max data rate of 4.5Gbps.
• Transmitter: Faster Rise/Fall times(<115pS),
- De-emphasis(-3.5+/-1dB, -6dB+/-1dB)
- Cpin:3pF
• Spread Spectrum Clocking(SSC) support on clock to mitigate emissions concerning EMI compliance.
• Scrambling support at the controller level to reduce data interference with the radio frequencies.
• Channel Support: 14inch(@4.5Gbps), 21inch(@2.5Gbps)
• PPI(Protocol PHY Interface) to support higher data byte width. 8/16/32 bit
• Support 4K Display with Chip on Glass implementation.
• Test Mode. Informative chapter.
20
Page
C-PHY Universal Lane Module Functions
– TXs and RXs: Bidirectional
– Contention Detection (LP only)
– Two set‘s of TXs / RXs (HS & LP)
– HS-mode:
• Small Amplitude, always 50
W “star-type“ termination
• Data format: 3-phase / 3-level
• Signaling: 3 wires forming a
HS-lane
– LP-mode:
• Large Amplitude, unterminated
• Data format: RZ
• Signaling non-differential
21
A
B
C
HS-TX
HS-RX RT
TX Ctrl Logic
DecoderHS-
Deserialize
State Machine(incl Enables, Selects
and System ctrl)
Error detect
CtrlIF
logic
DataIF
logic
Esc Encoder
HS-Serialize
Sequences
Mapper
Encoder
Data Sampler
Esc Decoder
Ctrl Decoder
Data Out
Data In
TX
RX
CD
Data Out
Data In
Clocks-out
Clocks-in
PPI(appendix)
ProtocolSide Line Side
De-Mapper
LP-TX
LP-RX
LP-CD
Page
Transition HS to LP mode and back
D-PHY
Dp/Dn
Disconnect
Terminator
THS-SKIP
THS-SETTLE
TCLK-POST
TCLK-TRAIL
TEOT
TCLK-MISS
THS-EXIT TLPX TCLK-PREPARE
TCLK-SETTLE
TCLK-ZERO TCLK-PRE
TLPX THS-PREPARE
VIH(min)
VIH(min)
VIL(max)
TCLK-TERM-EN
VIL(max)
TD-TERM-EN
Disconnect
Terminator
Data Lane
Clock Lane
Dp/Dn
Preamble Sync Word
LP-111 LP-001
tLPX t3-PREPARE
t3-SETTLE
A/B/C
t3-TERM-EN
LP-000
t3-PREAMBLE
Preamble is composed of: 3,3,3,3,3,…
Prog. sequence in mid-section is disabled.
Sync Word: 3,4,4,4,4,4,3
(Least SignificantSymbol first)
t3-PREBEGIN t3-PREEND
3 4 4 4 4 4 33 3 3 3 3 3 33 3 3 3 33
PacketData
t3-POST tHS-EXITPost LP-111
tREOT
4 4 4 4 4 4 4 4
Post is composed of multiple of unused code
word: 4,4,4,4,4,4,4
t3-SYNCC-PHY
22
Page
3 Phase Encoding Concept for C-PHY (HS-mode)
– A data encoding technique utilyzing
trios rather than pairs of wires
• 50 Ohm “star-type“ termination
• Utilyzes differential receivers,
rejecting common mode noise
• Drivers work similar to D-PHY but
control 3 instead of 2 outputs
– Both clock and data are encoded
and transported together in a single
trio
• Always a transition at every
symbol boundary, which simplifies
clock recovery and allows data
rate to be completely agile
23
A
B
C
Z0=50 ZID/2=50
+
-
ZID/2=50
ZID/2=50
Z0=50
Z0=50
+
-
+
-
Rx_AB
Rx_BC
Rx_CA
“0”
“1”
“1”+V/4
+V/4
-V/2
Slave side+V
“A”
“B”
“C”
Master side
+V
+V
PU_A
PD_A
PU_B
PD_B
PU_TC
50
50
100
100
“B” to “A” (-x state)
Page
C-PHY Block diagram
– Coding rules and possible
wire states:
• 27 possible wires states
• 6 allowed wire states
(+x, -x, +y, -y, +z, -z)
only those states with
different voltage on each
wire
• From one symbol to the
next symbol only 5 wire
states are possible,
because a transition is
required for CR
• Theoretical coding gain:
log2(5) = 2.32
• Practically usable gain is
2.28 by sending 16 bits in
7 symbols
24
Drawing showing T2 Driver type w/ active mid-level
PD_TC
Positive Polarity States Negative Polarity States
Z0=50 ZID/2=50
+
-
ZID/2=50
ZID/2=50
Z0=50
Z0=50
+
-
+
-
Rx_AB
Rx_BC
Rx_CA
“0”
“1”
“1”+V/4
+V/4
-V/2
Slave side+V
“A”
“B”
“C”
Master side
+V
+V
PU_A
PD_A
PU_B
PD_B
PU_TC
50
50
100
100
“B” to “A” (-x state)
Z0=50 ZID/2=50
+
-
ZID/2=50
ZID/2=50
Z0=50
Z0=50
+
-
+
-
Rx_AB
Rx_BC
Rx_CA
“0”
“0”
“1”+V/2
-V/4
-V/4
Slave side“C” to “A” (+z state)
+V
“A”
“B”
“C”
Master side
+V
+V
PU_A
PD_A
PU_TB
PD_TB
PU_C
PD_C
50
100
100
50
Z0=50 ZID/2=50
+
-
ZID/2=50
ZID/2=50
Z0=50
Z0=50
+
-
+
-
Rx_AB
Rx_BC
Rx_CA
“0”
“1”
“0”-V/4
+V/2
-V/4
Slave side+V
“A”
“B”
“C”
Master side
+V
+V
PU_TA
PD_TA
PU_B
PD_B
PU_C
PD_C
100
100
50
50
“B” to “C” (+y state)
+V
Z0=50“A” ZID/2=50
+
-
“B”
“C”
ZID/2=50
ZID/2=50
Z0=50
Z0=50
+
-
+
-
Rx_AB
Rx_BC
Rx_CA
“1”
“0”
“0”-V/4
-V/4
+V/2
Master side
Slave side
+V
+V
PU_A
PD_A
PU_B
PD_B
PU_TC
PD_TC
“A” to “B” (+x state)
50
50
100
100
Z0=50 ZID/2=50
+
-
ZID/2=50
ZID/2=50
Z0=50
Z0=50
+
-
+
-
Rx_AB
Rx_BC
Rx_CA
“1”
“0”
“1”+V/4
-V/2
+V/4
Slave side“C” to “B” (-y state)
+V
“A”
“B”
“C”
Master side
+V
+V
PU_TA
PD_TA
PU_B
PD_B
PU_C
PD_C
100
100
50
50
Z0=50 ZID/2=50
+
-
ZID/2=50
ZID/2=50
Z0=50
Z0=50
+
-
+
-
Rx_AB
Rx_BC
Rx_CA
“1”
“1”
“0”-V/2
+V/4
+V/4
Slave side“A” to “C” (-z state)
+V
“A”
“B”
“C”
Master side
+V
+V
PU_A
PD_A
PU_TB
PD_TB
PU_C
PD_C
50
100
100
50
Page
C-PHY Signal Characteristics
Unit Intervall #1
A-B = 0.0-0.5
= -0.5 = weak 0
B-C = 0.5 – 1.0
= -0.5 = weak 0
C-A = 1.0 – 0.0
= 1.0 = strong 1
Unit Intervall #2
A-B = strong 1
B-C = weak 0
C-A = weak 0
Unit Intervall #3
A-B = weak 1
B-C = weak 1
C-A = strong 0
High Speed Only
Transmit: A, B and C
Receive: A-B, B-C and C-A
UI#: 1 2 3
0.0
0.5
1.0
-1.0
0.5
1.0
-0.5
25
Page
Eye Diagram, Clock Recovery
• Align waveform to 1st zero crossing at Trigger Point for eye diagram.
• Slave recovers the clock for data sampling by using the guaranteed transitions at each UI boundary
• One or more of the differential receiver outputs in the slave will change at each UI boundary due to the symbol encoding rules.
• When multiple receiver outputs change they are often staggered in time.
• The right-most point of the eye mask is aligned with the first zero crossing trigger point.
oConsistent with sampling the received data just prior to the trigger point.
Trigger, at 1st zero crossing
“strong 1”
“weak 1”
“strong 0”
“weak 0”
Zero Crossing Eye Mask
26
Page
C-PHY Eye Diagram and Mask Test
27
High Speed Only, A-B
• Clock is recovered from the earliest edge of a symbol transition.
• A delay circuit with negative hold time is used to sample data. Supposed to be more resistant to noise and jitter on the system.
Strong-1
Weak-1
Weak-0
Strong-0
0V threshold
Page
Three PHYs “at a glance”
Characteristic M-PHY v3.1 D-PHY v1.2 C-PHY v1.0
Primary use case Performance driven,
bidirectional
packet/network oriented
interface
Efficient unidirectional
streaming interface, with
low speed in-band reverse
channel
Efficient unidirectional
streaming interface, with
low speed in-band reverse
channel
HS clocking method Embedded Clock DDR Source-Sync Clock Embedded Clock
Channel compensation Equalization Data skew control relative
to clock
Encoding to reduce data
toggle rate
Minimum configuration and
pins
1 lane per direction, dual-
simplex, 2 pins each (4 )
1 lane plus clock, simplex,
4 pins
1 lane (trio), simplex, 3
pins
Maximum transmitter swing
amplitude
SA: 250mV (peak)
LA: 500mV (peak)
LP: 1300mV (peak)
HS: 360mV (peak)
LP: 1300mV (peak)
HS: 425mV (peak)
Data rate per lane (HS) HS-G1: 1.25, 1.45 Gb/s
HS-G2: 2.5, 2.9 Gb/s
HS-G3: 5.0, 5.8 Gb/s
(Line rates are 8b10b
encoded)
80 Mbps to ~2.5 Gbps
(aggregate)
80 Msym/s to 2.5 Gsym/s
times 2.28 bits/sym, or
max 5.7 Gbps (aggregate)
Data rate per lane (LS) 10kbps – 600 Mbps < 10 Mbps < 10 Mbps
Bandwidth per Port (3 or 4
lanes)
~ 4.0 – 18.6 Gb/s
(aggregate BW)
Max ~10 Gbps per 4-lane
port (aggregate)
Max ~ 17.1 Gbps per 3-
lane port (aggregate)
Typical pins per Port (3 or 4
lanes)
10 (4 lanes TX, 1 lane RX) 10 (4 lanes, 1 lane clock) 9 (3 lanes)
28
Page
Key Features of PHY-Layer Standards
Rev Max Data
Rate (Gb/s)
Data
format
Clocking Clock
Recovery
EQ
HS LP HS
D-PHY 1.0, 1.1 1.5, continous RZ NRZ Forward Source
Synchronous
(DDR)
NA None
1.2 2.5, continous None
2.0 4.5, continous TX
C-PHY 1.0 2.5, continous RZ 3-ph embedded Logical None
M-PHY 1.0, 2.0 1.5/3 discrete PWM NRZ embedded PPL-based None
3.0 6, discrete TX
4.0 12, discrete TX & RX
29
Page
Release Status of Standards and Related CTSs
Standard version Status CTS Status
D-PHY 1.0, 1.1 released rev 1.0 released
1.2 released wip
2.0 wip not started
C-PHY 1.0 released vers 1.0r0.5 wip
M-PHY 1.0 released vers 1.0r0.95 released
2.0 released vers 1.0r0.95 released
3.0 released ver 3.0r17 wip
4.0 wip not started
30
wip = work in progress
Page
Agenda
Overview
– MIPI PHY roadmap
– PHY electrical review
– TX update
– Return loss update
– RX update
31
Page
M-PHY TX Update
– Jitter tests are made informative if they pass the eye mask tests for
G1, G2 and G3.
• Difficult to de-embed jitter measurements to the TX pins.
– Eye test is updated from BER 1E-10 to BER 1E-6
• 3 million UIs are acquired (95% confidence)
• Mask derated to BER 1E-6
• Mask placement optimization for G1
32
CTS 3.1 update
Page
D-PHY TX Update
– New de-skew tests
33
CTS 1.2 Update
Software update will be
available in Dec.
Please talk to your
customers to get skew
waveforms and send to
OPD.
Page
C-PHY TX Update
– Now available
– Clock tests are removed
– All tests updated to multi-level signaling
– Timing tests require decoding
34
CTS 1.0 Update
C-PHY UDA is
available. Please
contact OPD.
Page
MIPI probing options
– D-PHY and C-PHY probing option:
• Solder down on dynamic load (50-ohm and open)
– M-PHY probing options:
• Solder down on 100-ohm differential load
• Direct into scope
• SMA probe head
35
Page
Agenda
Overview
– MIPI PHY roadmap
– PHY electrical review
– TX update
– Return loss update
– RX update
36
Page
Return Loss / Channel Characterization
37
A portion of the transmitted signal is reflected due to impedance
mismatches. If the signal path is not impedance matched, reflections
can cause eye closure.
Transmitter Impedance Matched Transmitter Impedance NOT Matched
Transmitter Termination Effects
t
Tx Rx
Page
S-parameter and Impedance Measurements
38
Active transmitter characterization.
t
t
The TX is required to transmit a
repetitive pattern when
characterizing its return loss.
Page
Measurement Example Using ENA Option TDR
39
All Measurements in One Screen
TDR application
helps trouble
shooting with
the simple and
intuitive user-
interface.
VBA Macro
automatically
sets the limit
lines, based on
your input
parameters.
Single-ended Impedance 1 Differential Return Loss
Single-ended Impedance 2
Differential Impedance
Common-mode Return Loss
Page
MOI for D-PHY and M-PHY ENA tests
– www.Keysight.com/find/ena-tdr_dphy-txrx
– www.Keysight.com/find/ena-tdr_mphy-txrx
40
Page
Agenda
Overview
– MIPI PHY roadmap
– PHY electrical review
– TX update
– Return loss update
– RX update
41
Page
About Receiver (RX) testing
– RX testing
An RX test is used to determine an RX’s capability to properly
detect the digital signal content, even for worst-case impaired
input signals. For this testing…
1. A Bit Error Ratio Tester’s (BERT) Pattern Generator (BERT PG)
is used to emulate a system’s TX plus channel thus generating
a data signal containing the impairments to be expected at the
RX input when it is operating in a target system.
This signal has to be calibrated according to the specification
2. The input of the RX under test is stimulated with this signal
3. Proper detection of the digital content is monitored in a suitable
fashion to determine performance according to target BER
–
42 MIPI M-PHY Receiver Test Webinar
August 2013
Page
PHY Layer Error Detection
– Challenges with different protocols:
• Asymmetrical lane configuration (e.g. 2x HS upstream / 1x LS
downstream)
• Test modes not mandatory (optional normative / recommendation)
• Specific method defined in protocol spec, not in PHY spec
– Various error detection methods:
• Line Loopback (i.e. bit level loopback)
• Logic Loopback (i.e. protocol layer loopback)
• PPI (=Parallel Processor Interface i.e. parallel data output)
• IBER (=Internal Bit Error Ratio Counter)
– Not all MIPI applications have settled on preferred test option
– Not possible to provide turnkey solution, RX testing always has
a custom portion
43
Page
Measurements According to CTS rev 1.0
Test # Mode Test Parameter
2.1.1 HS_RX HS-RX Differential DC Input Voltage Amplitude Tolerance (VDIF-DC-HS-RX)
2.1.2 HS_RX HS-RX Accumulated Differential Input Voltage Tolerance (VDIF-ACC-HS-RX)
2.1.3 HS_RX HS-RX Common-Mode Input Voltage Tolerance (VCM-RX)
2.1.4 HS_RX HS-RX Differential Termination Enable Time (TTERM-ON-HS-RX)
2.1.5 HS_RX HS-RX Differential Termination Disable Time (TTERM-OFF-HS-RX)
2.1.6 HS_RX HS-RX Lane-to-Lane Skew (TL2L-SKEW-HS-RX)
2.1.7 HS_RX HS-RX Receiver Jitter Tolerance (TJRX, DJRX, RJRX, STTJRX, STDJRX)
2.1.8 HS_RX HS-RX Frequency Offset Tolerance (fOFFSET-RX)
2.1.9 HS_RX HS-RX PREPARE Length Capability Verification (THS-PREPARE-RX)
2.1.10 HS_RX HS-RX Sync Length Capability Verification (TSYNC-RX) 2.2.1 PWM_RX PWM-RX Differential DC Input Voltage Amplitude Tolerance (VDIF-DC-PWM-RX) 2.2.2 PWM_RX PWM-RX Accumulated Differential Input Voltage Tolerance DIF-ACC-PWM-RX) (INFORMATIVE)
2.2.3 PWM_RX PWM-RX Common-Mode Input Voltage Tolerance (VCM-RX)
2.2.4 PWM_RX PWM-RX Differential Termination Enable Time (TTERM-ON-PWM-RX)
2.2.5 PWM_RX PWM-RX Differential Termination Disable Time (TTERM-OFF-PWM-RX)
2.2.6 PWM_RX PWM-RX Lane-to-Lane Skew (TL2L-SKEW-PWM-RX)
2.2.7 PWM_RX PWM-RX Receive Bit Duration Tolerance (TOLPWM-RX, TOLPWM-G1-LR-RX)
2.2.8 PWM_RX PWM-RX Receive Ratio, PWM-G1 and Above (kPWM-RX)
2.2.9 PWM_RX PWM-RX Receive Minor Duration in PWM-G0 (TPWM-MINOR-G0-RX) 2.3.1 SYS_RX SYS-RX Differential Input Voltage Amplitude Tolerance (VDIF-DC-SYS-RX) 2.3.2 SYS_RX SYS-RX Accumulated Differential Input Voltage Tolerance (VDIF-ACC-SYS-RX)
2.3.3 SYS_RX SYS-RX Common-Mode Input Voltage Tolerance (VCM-DC-SYS-RX) 2.3.4 SYS_RX SYS-RX Differential Termination Enable Time (TTERM-ON-SYS-RX)
2.3.5 SYS_RX SYS-RX Differential Termination Disable Time (TTERM-OFF-SYS-RX)
2.3.6 SYS_RX SYS-RX Lane-to-Lane Skew (TL2L-SKEW-SYS-RX)
44
Including rev. 1.x and 2.x of M-PHY Specification
= eye height
= eye width (jitter)
= Focus on
HS_RX
margining
• in red
specifications
describing
transition
between LP
and HS mode
MIPI M-PHY Receiver Test Webinar
August 2013
Page
M-PHY Definition of RX Eye Diagram
– Geometry (channel lengths) supported is identical for all Gears despite increasing loss:
• G3 requires TX de-emphasis (3.5 / 6.0 dB depending on swing and actual channel)
• G4 additionally requires receiver equalization (RX-EQ) with CTLE and one-tap DFE
– Target BER is 10-10: however, to shorten measurement time, calibration is done with 3x106 samples
for BER = 10-6 using “prorated” mask w/ larger eye- width and –height (EW , EH) (CTS 3.0)
– Calibration for G4: post processing of measured data emulating reference package and RX-EQ
– TJ, DJ, STTJ and STDJ are normative with continuous signal
DJ and STDJ are informative with burst using TIEpp method
Gear 3 & 4 3 Gear 1 & 2
45
Page
Custom
Test Board
TP
ISI Conformance Channel
BERT
Pattern
Generator
w/ TTCs
Breakout Trace
ASIC RX
DUT
TX
Ref
Clk
Inte
rnal Loopback
or
Err
or
counte
r
Replica
Trace
Setup for M-PHY RX Test and Calibration
Test board with Replica Traces
– creating test point (TP) for calibration
– equivalent to the ASIC-input pins
Stress Signal Generation and Calibration according to CTS
for Gear_1 to Gear_3 100 Ohm
Differential
Probe
RT-Oscilloscope
Ca
l-pla
ne
46
Page
Custom
Test Board
TP
ISI Conformance Channel
BERT
Pattern
Generator
w/ TTCs
Breakout Trace
ASIC RX
DUT
TX
Ref
Clk
Inte
rnal Loopback
or
Err
or
counte
r
Replica
Trace
Setup for M-PHY RX Test and Calibration
Stress Signal Generation and Calibration
for Gear_4
Test board with Replica Traces
– creating test point (TP) for calibration
– equivalent to the ASIC-input pins
EQ
small EW/EH
larger EW/EH
Ca
l-pla
ne
(1)
(2)
(3)
47
Page
w/ EQ
w/o EQ
w/o EQ
w/ EQ
Gear 4 Stress Calibration using Scope Postprocessing
EH <
40mV!
EW <
0.47UI
EH ~
82mV
EW ~
.53UI
EH<40mV, EW<470mUI EH~82mV, EW~530mUI
48
Page
Overview key topics M-PHY gears
Gear 1 Gear 2 Gear 3 Gear 4
Data rate/Gb/s 1.248 / 1.458 2.496 / 2945 4.992 / 5830 9.984 / 11.661
TTC/ps 220 120 65 tbd
Channel SATA-2 Ref ch 1 / 2 tbd
De-emphasis NA Optional, depends on channel
tbd
Cal-Plane Input pins Inside ASIC
behind EQ
Simulation of RX pack & EQ
N/A SigTest?
RX stress cal DDJ, ST-SJ,
ST-RJ, SJ, RJ
DDJ, ST-SJ,
ST-RJ, SJ, RJ
DDJ, ST-SJ, SJ, RJ, Proprated eye adjusted
using amp and SJ
tbd Same as Gear 3
after EQ using sim?
49
Page
List of Required C-PHY Tests (CTS) and Availability Signal Generation Capabilities M8085A SW rev 1.1, Nov 2014
50
DRAFT Conformance Test Suite for C-PHY
Version 1.0r04, 04 August 2014
CTS-paragraph CTS-page Test pattern Observable Parameter(s) supported by
Number Title device specific device specific variable fixed special SW *) regular
release GROUP 1: LP-RX VOLTAGE AND TIMING REQUIREMENTS 90 Test 2.1.1 LP-RX Logic 1 Input Voltage (VIH) 91 valid LP test pattern BER VOH of Va,Vb, Vc VOL rev 1.0 Test 2.1.2 LP-RX Logic 0 Input Voltage, Non-ULP State (VIL) 93 valid LP test pattern BER VOL of Va,Vb, Vc VOH rev 1.0
Test 2.1.3
LP-RX Input Hysteresis (VHYST)
95
static internal logic state VO rev 1.0 dynamic BER single ended Vnoise VOH, VOL rev 1.2
Test 2.1.4 LP-RX Minimum Pulse Width Response (TMIN-RX) 99 valid LP test pattern BER TLPX VOH, VOL rev 1.0 Test 2.1.5 LP-RX Input Pulse Rejection (eSPIKE) 101 valid LP test pattern BER Tglitch VOH, VOL rev 1.1 Test 2.1.6 LP-RX Interference Tolerance (VINT and fINT) 105 valid LP test pattern BER Fmod,cm and Vmod,cm VOH, VOL rev 1.2 GROUP 2: LP-RX BEHAVIORAL REQUIREMENTS 107
Test 2.2.1 LP-RX Initialization period (TINIT) 108 valid LP or HS test pattern DUT ignores input
signal Tinit LP and/or HS levels rev 1.0
Test 2.2.2 ULPS Exit: LP-RX TWAKEUP Timer Value 110 valid LP-HS sequence with valid HS pattern BER Twake-up (Mark-1 (LP-10)) duration LP and HS levels and data
rates rev 1.0
Test 2.2.3 LP-RX Invalid/Aborted Escape Mode Entry 111 invalid escape mode entry sequences between valid HS bursts BER invalid escape mode entry sequences LP and HS levels, data
rates rev 1.0
Test 2.2.4 LP-RX Invalid/Aborted Escape Mode Command 113 invalid escape mode entry comands between valid HS bursts BER invalid escape mode entry commands LP and HS levels, data
rates rev 1.0
Test 2.2.5 LP-RX Escape Mode, Ignoring of Post-Trigger-Command Extra Bits 116 valid HS bursts with inserted valid Escape Mode Entry sequence +
Reset-Trigger command (01100010) + ULPS command (00011110) BER
LP and HS levels, data
rates rev 1.0
Test 2.2.6 LP-RX Escape Mode Unsupported/Unassigned Commands 118 valid HS bursts with inserted valid Escape Mode Entry sequence +
<Undefined-1, Unknown-3,4,5 , unassigned> BER
undefined/unknown and unassigned
commands LP and HS levels, data
rates rev 1.0
GROUP 3: HS-RX VOLTAGE AND SETUP/HOLD REQUIREMENTS 120
Test 2.3.1 * HS-RX Amplitude Tolerance (VCPRX(DC), VIHHS, VILHS) 121 valid HS patterns BER VIHHS, VILHS resulting in VIDTH and
VIDTL for Va, Vb, Vc patterns and data rate rev 1.0
Test 2.3.2 * HS-RX Differential Input High/Low Thresholds (VIDTH, VIDTL) 124 valid HS patterns BER VIHHS, VILHS resulting in VIDTH and
VIDTL for Va, Vb, Vc patterns and data rate rev 1.0
Test 2.3.3 HS-RX Common-Point Interference 50MHz - 450MHz (ΔVCPRX(LF)) 126 valid HS patterns BER Fmod,cm and Vmod,cm LP and HS levels, data
rates rev 1.2
Test 2.3.4 HS-RX Common-Point Interference Beyond 450MHz (ΔVCPRX(HF)) 128 valid HS patterns BER Fmod,cm and Vmod,cm LP and HS levels, data
rates rev 1.2
Test 2.3.5x * HS-RX Setup/Hold and Jitter Tolerance 130 valid HS patterns BER Hslevels, DCD, ISI (S-params), Vcm,
Fcm patterns and data rate rev 1.2 rev 1.2
GROUP 4: HS-RX TIMER REQUIREMENTS 134
Test 2.4.1 HS-RX T3-TERM-EN Duration 135 valid HS request sequence DSO, "spike" NA LP and HS levels, data
rates rev 1.0
Test 2.4.2 HS-RX T3-PREPARE Tolerance 137 valid HS request sequence BER T3-prepare LP and HS levels, data
rates rev 1.0
Test 2.4.3 HS-RX T3-PREBEGIN Tolerance 139 valid HS request sequence BER T3-prebegin LP and HS levels, data
rates rev 1.0
Test 2.4.4 HS-RX T3-PROGSEQ Tolerance 141 valid HS request sequence containing tbd T3-progseq BER NA LP and HS levels, data
rates rev 1.0
Test 2.4.5 HS-RX T3-POST Tolerance 143 valid HS request sequence cappended by variable T3 Post pattern BER T3-post LP and HS levels, data
rates rev 1.0
*) Test 2.3.5 has NOT yet been updated to C-PHY (skew between clock and data) - will probably be substituted by Ravi's proposal (depending on WG acceptance) *) rev 1 now *) Tests 2.3.2, 2.3.5 and maybe 2.3.1 will probably be combined into one test according to Ravi's proposal (depending on WG acceptance) *) rev 2 Oct-14
Page
How Can All of This Be Tested?
– Modular system in AXI form factor /frame consisting of
• HW modules M8041A and M8051A plus M8070 SW
forming Keysight J-BERT M8020A
• modular up to 4 channels enabling channel skew measurements
• Very much comparable to N4903B
– Very well suited for M-PHY
– Test Automation: SW Keysight N5990A option 165 &
Bitifeye Frame Generator BIT-2060-0001-0
– ...
51
Keysight M8000 Series of BER Test Solutions
Page
• Parameters of
selected item
• Calibrations
• HS, NRZ (RT)
• LP, PWM (NT)
• RX tests
• HS, NRZ (RT)
• LP, PWM (NT)
N5990A Automation Software
Setup of Test Flow
• Parameters of selected item
• Calibrations
- HS, NRZ (RT)
- LP, PWM (NT)
• RX tests
- HS, NRZ (RT)
- LP, PWM (NT)
52
Page
N5990A Automation Software
– Connect (string connection): will be called once at the beginning of the test
run. The connection string can contain a customized address (like a COM
port) to access to the tool which is able to read out the internal counters of
the DUT
– Init (string mode): will be called once at the beginning of each test. This
allows to configure the DUT into the test mode of a particular test (HS or
PWM, Gear, Functional Test)
– ResetDUT (): will be called once at each test point. This allows to reset
error counters, or set the DUT in a defined mode to be ready for the next
test point
– GetCounter (out double errorCounter, out double bitCounter) will be called
after or during a test point execution. The errorCounter value can contain a
CRC- or symbol-error, and the bitCounter can contain a bit or burst
counter. The counters can provide just simple indicators, if errors
happened and if the DUT was able to receive data, or in case of both error
and bit counters being implemented, to calculate BER
– Copy the compiled MPhyBerReader.dll into the ValiFrame Program Files
folder
– A new entry in the BER Reader List will be visible
– After selection of the Custom BER Reader the N5990A automation
software can connect with the DUT
53
DUT Configuration, Integration of IBERReader
Page
How Can All of This Be Tested?
– Modular system in AXI form factor /frame consisting of
• HW modules M8041A and M8051A plus M8070 SW
forming Keysight J-BERT M8020A
• modular up to 4 channels enabling channel skew measurements
• Very much comparable to N4903
– Very well suited for M-PHY
– Test Automation: SW Keysight N5990A option 165 &
Bitifeye Frame Generator BIT-2060-0001-0
– How to address C-PHY / D-PHY ?
• We now integrate Keysight AWG modules
substituting 8041/51A‘s NRZ PGs
while still operating under a typical
BERT use model
54
Keysight M8000 Series of BER Test Solutions
Page
Realization of "C-PHY-GUI" within M8070A SW
Definitions available for:
– Pattern & coding
– Low Power to High
Speed mode
transition
C-PHY Frame Generator integrated M8070 SW / M8000 BER solution
55
Page
Realization of "C-PHY-GUI" within M8070A SW
Definitions available for:
– Pattern & coding
– LP to HS mode
transition
C-PHY Frame Generator integrated M8070 SW / M8000 BER solution
LAB
Parameter editor for
Impairments
56
Page
Setup for C-PHY: M8190A, 5 Slot Frame, Embedded Controller
1-lane
C-PHY
DUT
embedded controller (1 slot)
57
Page
Setup for C-PHY: M8195A, 5 Slot Frame, Embedded Controller
1-lane
C-PHY
DUT
1-lane
C-PHY
DUT
Alternative setup: M8195A, 2 slot frame, embedded Controller
embedded controller (1 slot)
58
Page
Setup for C-PHY: M8195A, 5 Slot Frame, Embedded Controller
3-lane
C-PHY
DUT
3 AWG modules capable of driving up to 12 wires ( up to 4x C-PHY lanes) required synchronization module not shown
59
Page
Keysight / Keysight Solutions for MIPI RX PHY-test
60
2013 and before
2013 2015 2014
M-PHY
D-PHY
J-BERT N4903B
ParBERT 81250
Page
Keysight / Keysight Solutions for MIPI RX PHY-test
61
2015: Complete Solutions
2013 2015 2014
M-PHY
D-PHY
C-PHY
J-BERT N4903B
ParBERT 81250
J-BERT M8020A
AWG M8190A
w/ M8085 special SW
M8000 family of
BER test solutions
AWG M8190A
w/ MATLAB script
J-BERT M8020A /
M8070 / 85A
AWG M8195A /
M8070 / 85A
Page
Keysight MIPI Total Solution Coverage Transmitter
Characterization
DSAQ93204A Infiniium
U7238B D-PHY, U7249B
M-PHY, N5467B C-PHY UDA
InfiniiMax Probes
Switch matrix
N5465A InfiniiSim
N2809A PrecisionProbe
Receiver
Characterization
N4903B/M8020A JBERT
M8190 AWG
81250A ParBERT
N5990A Automated
characterization
Impedance/Return
Loss Validation
E5071C ENA Option TDR
DCA 86100D Wideband
sampling oscilloscope
N1055A
TDR/TDT
54754A
TDR/TDT
Industry’s highest analog
bandwidth, lowest noise
floor/sensitivity, jitter
measurement floor with
unique cable/probe correction
Precision impedance
measurements and
S-Parameter capability
Highest precision jitter lab
source with automated
compliance software for
accurate, efficient, and
consistent measurement
Protocol Stimulus and
Analysis
U4421A D-PHY CSI-2 / DSI
Analyzer and Exerciser
U4431A M-PHY Analyzer (UFS,
UniPro, CSI-3, SSIC, M-PCIe)
Scope Protocol Decoder N8802A CSI-2 / DSI
N8807A DigRF v4
N8808A UniPro
N8818A UFS
N8809A LLI
N8819A SSIC
N8820A CSI-3
N8824A RFFE
Fast upload and display,
accurate capture, intuitive
GUI and customizable
hardware. Correlate physical
and protocol layer.
62