Abstract: RF energy is widely available in urban areas and thus presents a promising ambient energy harvesting source. In this paper, a harvester circuit is modeled and analyzed in detail at low environmental power levels. Based on the circuit analysis, a design procedure is given for a narrowband energy harvester. The antenna and harvester co-design methodology is discussed to improve RF to DC energy conversion efficiency. We demonstrate that it is difficult to harvest RF energy over a wide frequency band if the ambient RF energy sources are weak, owing to the voltage requirements. Since most ambient RF energy lies in a few narrow bands, a dual-/multi-band energy harvester architecture should be able to harvest much of the available RF energy. A dual-band energy harvester is designed and fabricated using an IBM 0.13m process. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (around 900MHz and around 1900MHz) at an input power as low as -19.3dBm. The DC output voltage of this harvester is over 1V, which can be used to recharge the battery to form an inexhaustibly powered communication system.Index Terms—Low power RF harvester, Low power energy solution, Voltage boosting techniques, Voltage Doubler.

I.INTRODUCTION Ambient Radio Frequency (RF) electromagnetic energy is a promising source for harvesting due to its wide availability in urban areas and the amount of power present. RF energy harvesting is a process for converting AC (RF) power into DC power. A widely used AC to DC topology is to utilize a voltage doubler structure, which employs two rectifiers to take advantage of the full RF signal cycle [1]. However, under low input power scenarios (10 W or less), the input signal voltage is much smaller than the typical rectifier (diode) threshold voltage. The low input voltage severely limits the harvester efficiency.

The difficulty for conversion of low input RF power can be addressed in different ways: either by reducing the diode threshold voltage or by boosting the input voltage.

Manuscript received July 20, 2012. This work has been supported by the Laboratory for Physical Sciences, and the Office of Naval Research under grant number N000140911190. Bo Li (liletian@ieee.org), Xi Shao, Negin Shahshahan and Neil Goldsman (neil@umd.edu) are with department of Electrical and Computer Engineering, University of Maryland, College Park, USA. Thomas Salter and George M. Metze are with Laboratory for Physical Sciences, College Park, MD, USA.

A brief review of relevant studies in this area follows. Work by Karthaus et al. [1] utilized low forward threshold (200 mV) Schottky diodes to help turn on the diodes. Zbitou et al. [2] and Olgun et al. [3] obtained 20% efficiency for input power of -20dBm by using low threshold voltage Schottky

diodes. The output voltage of their work for -20 dBm input power is less than 1V. Umeda et al. designed distributor circuits to supply bias voltages for MOSFET-connected diodes to more easily turn on the diodes and thus obtain higher charging current for low input power which achieves 0.75% efficiency for -14dBm input power [4]. Nakamoto et al. implemented floating gate devices to pre-set the biasing voltages at the gates of MOSFET-connected diodes [5] which need an additional procedure to correctly program the biasing voltages. Salter et al. [6] used off-chip high impedance resistor networks to provide different DC biasing voltages at the gates of the MOSFET-connected diodes. This technique does not need a secondary power source. Besides the above approaches for reducing the threshold voltage, there has been another research thrust aimed at boosting input signal voltages. Nakamoto et al. [5], Salter [6] and Le et al. [7] used different matching networks to boost the input signal voltages.

In this work, we build on the previous efforts especially with voltage boosting, power matching and extend it to a multiband system. We first provide detailed modeling and analysis of voltage doubler using MOSFET connected diodes. We then investigate a wideband energy harvesting scheme and demonstrate its theoretical difficulties. A dual-/multi-band architecture is introduced to take full advantage of the available environmental RF energy and a dual-band energy harvester has been designed, fabricated, and measured for performance. Not only is power extracted from multiple bands simultaneously, but at input power that correspond to voltages that are as low as 35mV for standard 50ohm RF loads.

II. DUAL-/MULTI-BAND PARALLEL ENERGY HARVESTER Energy harvesters are emerging as a promising power solution for future low power devices. For this to be feasible, harvesters either need to power the electronics or charge the battery to meet the needs of mobile applications such as wireless sensor networks and remote data loggers. The latest CMOS electronics can be operated with under a 1V DC supply [8]. The minimal charging voltage of new batteries is about 1V as well [9] [10]. Based on these requirements, the harvester system specifications are defined as follows:

A minimum 1V output voltage is required in order to meet battery recharging requirements [9] [10].

The system needs to harvest energy at two or more frequency bands. In this work, the two frequency bands used are at 900MHz and 1900MHz, which correspond to the largest power peaks according to previous surveys [6].

The harvester sensitivity needs to be capable of harvesting RF at power levels that are as low as -19dBm.

The design needs to utilize standard CMOS technology in order to lower the costs.

Figure 1 shows the block diagram of the dual-band energy harvester we pursue to meet the above power charging

AN ANTENNA CO-DESIGN DUAL BAND RF ENERGY HARVESTER

Bo Li, Member, IEEE , Xi Shao, Negin Shahshahan, Neil Goldsman, Member, IEEE, Thomas Salter, George M. Metze

specifications. The two harvester circuits have been connected in parallel and placed on a single chip. The parallel combined harvesters obtain low impedances at their designed frequencies in order to maximize the voltage boosting and power transfer, and have much higher impedances at other frequencies. This allows the system to extract energy at different bands simultaneously, while at the same time minimize losses through non-harvesting parallel paths.

Figure 1 Block diagram of the parallel dual-band energy harvester structure.

RF energy harvester performance is mainly evaluated by efficiency, output voltage, and the minimum input power. The RF energy harvester includes an antenna, matching and boosting circuits, and voltage doubler subsystems. In the following sections, we describe the topologies and theories used to develop the various subsystems of the dual band harvester.

A.Voltage Doubler with Boosting Circuit and Pre-set Biasing Network

Figure 2 Voltage doubler using MOSFET-connected diodes.

Figure 2 shows the circuit schematic of the voltage doubler using MOSFET-connected diodes. In general, an AC voltage Vin gets converted to DC by the MOSFET connected diodes M1 and M2 and the capacitors. The voltage doubler uses currents I1 and I2 to charge capacitors C1 and C2. During the negative part of Vin, M1 is on, and M2 is off and C1 becomes charged. During the positive part of the V in cycle, M1 is off and M2 is on and C2 is charged by Vin and C1. Hence, ideally the output voltage becomes twice the amplitude of the AC input voltage. The C1, C2, C3 and C4 components in Figure 2 function as an AC bypass, DC block and storage capacitors. The resistor RB1, RB2, RB3 and RB4 generate a self-biasing

voltage to increase the currents (I1, I2). The MOSFET connected diode M2 uses PMOS to reduce the body effect. The currents (I1, I2) need to be as large as possible to obtain high AC to DC conversion efficiency.

As mentioned previously, the major difficulty with RF energy harvesting is to generate sufficient voltages from low level ambient power in order to turn on the active devices for rectification. One way to increase the current is to effectively reduce the DC threshold voltage. To effectively reduce the threshold voltage without applying an outside source, a sacrificial current biasing method (pre-set biasing network) is used to reduce the necessary voltage supplied by V in for this design as shown in Figure 2. The biasing resistors RB1, RB2, RB3, RB4 are used to provide DC bias voltage at the gate of the MOSFET connected diodes to increase the charging currents I1, and I2 to improve efficiency. This method has been also be explained previously in [6].

In low RF input power applications, the available ambient energy is around -19dBm level in near-urban locations, which corresponds to a 35 millivolt input voltage for a 50 Ohm matching resistance. However, Vth is a few hundred millivolts for MOSFET connected diodes, and is approximately 200mV for Schottky diodes. Since the AC voltage is smaller than the threshold voltage, the current is exponentially proportional to the applied AC voltages. Hence, the pre-set voltage can increase the current for small AC power as shown in Figure 1.

Another vital to the operation of low power energy harvesting is the method of low power voltage boosting that we use to turn on the MOSFETs. In the following sections, we focus on the voltage boosting techniques.

Boosting Input Voltage This section discusses the voltage boosting techniques for a single stage voltage doubler. This sets the background for our multi-stage doubler that we eventually design and fabricate for this work. Our results show that under low input power condition, the voltage boosting is limited by the quality factor of the on-chip passive inductor in our application. The basic idea behind voltage boosting is to use an LC resonant circuit to generate a large voltage across the MOSFET, thereby turning it on even though the input power is very low. The voltage doubler design has been modified to include voltage boosting circuit components as well as the intrinsic internal resistance of the source Vin (Rs and L1), as shown in Figure 3. Furthermore, the intrinsic gate capacitances Cgs for M1 and M2 (not shown explicitly) are in parallel with the MOSFETs. The inductor L1 and intrinsic MOSFET capacitances form a resonant circuit. The voltage boosting mechanism is analogous to a series RLC network. As explained below, the circuit components in the box of Figure 3 function mainly as a high quality capacitor at low input power level (-19dBm) for AC operation. This effective capacitor experiences a large voltage at resonance, which is in parallel to the MOSFET connected diodes, thereby forward biasing the diodes and increasing the harvesting current. The concept can be explained using the MOSFET connected diode lumped model shown in Figure A.1 (d) in the appendix. To achieve this, we replace the MOSFET-

connected diodes (M1 and M2) by the simplified lumped model shown in Figure A.1 (d) in the Appendix, the AC equivalent for the circuit in Figure 3 can be represented by the one given in Figure 4 (a). At input frequency , the circuit in Figure 4 (a) can be simplified to the circuit in Figure 4 (b) by replacing the AC coupling capacitors (C1, C2) with shorts. The term 2CT in Figure 4 (b) arises from the parallel connection of the two capacitors (CT), where CT is composed largely of Cgs from the MOSFETs as described in the Appendix. During each half cycle, only one diode is turned on, so the average resistance is equal to RCH, where RCH is the MOSFET channel resistance. The boosting voltage Vboost across the capacitor 2CT as shown in Figure 4b at resonant frequency, when RCH is much bigger than the impedance of 2CT, can be described by Equation 1

(1) 2 When Q > 1, the voltage across the capacitor is larger than the input voltage at the resonant frequency. This is also known as voltage boosting, and Q is known as the quality factor of the network. As shown in Figure 4 (b), the circuit in the box of Figure 4 (a) is equivalent to a parallel connected capacitor (2CT) and resistor (RCH). The quality factor of the parallel connected RC network in Figure 4 (b) is defined as the ratio of the current through capacitor (IC) and the current through resistor (IR) in equation 2:

(2)

Figure 3 Voltage doubler with voltage boosting.

Equation 2 indicates that the ratio of the current through the capacitor and the current through the resistor is the quality factor for the parallel connected RC network. The requirement for a high quality parallel RC network is thereby:

(3)

It should be noted that the current Ic is AC and in resonance, and therefore does not give rise to power lost through the boosting capacitors 2CT. Thus, even though Ic is significant compared with IR, it does not give rise to unwanted power losses. In low input power applications (e.g., at -19dBm), the relationship between the current through the capacitor and the channel resistance satisfies this relationship. This statement is validated by the simulation results. Figure 5 (a) and (b) show the simulated current through the capacitor (AC) and the current through channel resistor (DC) of the designed voltage doubler for input power of -19dBm. The resonant AC current in Figure 5 (a) is much larger than the DC current in Figure 5 (b).

Figure 4 (a) Lumped model of the MOSFET connected diode based voltage doubler with boosting network. (b) Simplified lumped model at signal

frequency (). Figure 5 (c) shows the quality factor of the equivalent capacitor for the circuit in the box shown in Figure 3. The quality factor is ~20 at the resonant frequency. At the resonant frequency, the voltage boosting generates high voltage and thus the diode obtains high current. Obviously we want DC current through the diode to be large, which improves the conversion efficiency. However, high DC current will lower the quality factor and thus cause lower boosting voltage and DC current. Thus, there exists an optimal point to maximize the AC to DC power conversion. Furthermore, the boosting voltage decreases as the frequency moves away from the resonant frequency, which causes less current through diode.

In summary, the voltage across the MOSFET at the input signal frequency is boosted through the RLC network because the MOSFET-connected diode contributes a small capacitance as shown in Figure 4 (b). In conclusion, by utilizing the parasitic capacitance of the MOSFET, which is

generally unwanted, we can extract RF power at voltages which are far below the standard diode threshold level.

(a) (b)

(c)

Figure 5 (a) Magnitude of I1 for different input signal frequencies. (b) Magnitude of the DC component of I1 for different input signal frequencies. (c) Ratio of the AC component and the DC component of the current I1 for

different input signal frequencies.

B.Cascaded Voltage Doubler with Boosting Circuit In order to obtain the desired DC output voltage (>1V) at -19dBm power level with high conversion efficiency, a cascaded voltage doubler design with an additional boosting circuit is necessary. Figure 6 shows a simplified cascaded voltage doubler with a boosting circuit as well as pre-set biasing network (RP1, RP2, Rpm and Rn1, Rn2, Rnm). The circuit analysis can be divided into two steps. First, the voltage boosting circuit generates a boosted voltage Vboost; second, the cascaded stages perform DC to DC conversion.

Figure 6 A cascaded voltage doubler with boosting circuit.

The input signal is boosted via the same mechanism used for the single stage voltage doubler with a boosting network. The boosted voltage is given by Equation 4:

(4)

where Rs is the source resistance and Ctotal is the sum of the capacitance of the cascaded multi-stage voltage doublers since C1, C2 and CL functions as AC shorts and all the diode capacitors are in parallel. The output voltage of the cascaded voltage doublers is described by equation 5:

(5)

where Q is the quality factor of the boosting network, n is the number of cascaded stages, Vth is the threshold voltage of the diodes, and Vin is the input voltage. Equation 5 describes the relationship among the output voltage, the input power, diode threshold voltage, the number of the cascaded stages, and the voltage boosting ratio. This analysis shows that (i) the larger the number of stages, the higher the output voltage and (ii) the higher the quality factor, the higher the output voltage. However, as we add stages, power leakage increases and will eventually set an upper limit to the number of cascaded stages.

C. Antenna Coupled Cascaded Voltage Doubler with Boosting Circuit

In additional to boosting, we need power matching between antenna and energy harvester simultaneously. However, this is difficult because the matching for maximum power transfer between the antenna and the harvester, and the voltage boosting for the doubler, is not guaranteed to occur for the same frequency. Simultaneous power matching and boosting can be achieved by the co-design of the antenna and RF energy harvester. The matching impedance of the antenna and the energy harvester is generally designed to be 50 Ohm [4]. Since the antenna can connect to the energy harvester directly, maximum power transfer between antenna and energy harvester can be achieved if the impedance is matched between the antenna and the energy harvester, while at the same time achieving the necessary voltage boosting. The matching impedance of the energy harvester only needs to be the complex conjugate of the antenna impedance and can be used as a system design parameter to optimize the AC to DC conversion efficiency. This idea is depicted in Figure 7 in which the system design allows optimization of the efficiency by varying the antenna impedance. Below is a simple example to show that impedance matching can affect the boosting voltage and thus the conversion efficiency.

The relationship between the input voltage and the input power for the design in Figure 7 below is described by Equation 6:

(6)

where R is the matching impedance of the system and Pin is the signal power at the end of the antenna. The matching (boosting) circuit in Figure 7 is the same as the matching (boosting circuit) in Figure 6. The improvement in this topology is that the matching impedance is an optimization parameter instead of being a standard 50Ohms as discussed earlier. The voltage across the capacitor after the RLC voltage boosting network is applied at the resonant frequency is:

(7) where R is the matching resistance of the system and Pin is the signal power transferred into the harvester.

Figure 7 Antenna coupled cascaded voltage doubler with boosting circuit.

Equations 8 shows that the voltage across the capacitor is inversely proportional to the square root of the matching resistance of the system. The lower the series resistance R, the higher the boosted voltage. For example, if the antenna is designed to work with 10 Ohm instead of 50 Ohm matching, the voltage across the capacitor can be boosted to a voltage

5 times higher. This means the harvesting circuit can

generate the same voltage and obtain the same efficiency with 7dB lower input power than the 50 Ohm matching energy harvester for low power applications. Equation 7 also indicates that the boosted voltage can be infinite if the matching resistance of the system is zero. However, the antenna efficiency decreases to zero with zero-radiation resistance since the antenna efficiency is described by Equation 8 [12]:

(9)

Here , Rrad , and ROhm are the antenna efficiency, antenna radiation resistance, and antenna ohmic resistance, respectively. ROhm represents power losses due to the antenna metal resistance, which is generally less than 1 ohm. R rad

accounts for the radiated power of the antenna and is determined by the geometry and shape of the antenna. In order to achieve sufficient antenna efficiency, the real part of the antenna impedance needs to be larger than a reasonable minimal value. In this design, it has been determined using simulation that the real part of the antenna impedance should be larger than 10Ohms for good antenna efficiency.

D. Wideband Energy Harvesting Limitations This section discusses the design difficulty of the wideband energy harvesting. Due to the presence of multiple power peaks in the frequency domain of ambient RF energy, a particularly attractive RF energy harvesting strategy is wideband energy harvesting. Compared with a narrowband energy harvester, a wideband energy harvester needs to meet both the voltage boosting and wideband matching requirements over a wide frequency range. A wideband matching network is required in order to maximize the power transfer between the antenna and the harvesting circuits over a wide frequency range. The voltage boosting requirement is due to the low input power.

It is possible to obtain power matching over a wide frequency range [13], but this work does not allow for high voltage boosting. It is also possible to obtain voltage boosting through a narrow band high quality factor network [14]. However, it is unlikely that wideband power matching can be attained while also obtaining voltage boosting simultaneously because the bandwidth of the boosting network is described by Equation 9 [14]:

(9)

where BW is the 3dB bandwidth, Q is the quality factor, and resonant is the resonant frequency. This indicates that for higher Q, harvester bandwidth is narrower. At -19dBm power, our analysis and simulation show that a voltage boosting ratio of 8 is required to obtain >10% efficiency at 900MHz. From Equation 9, the bandwidth is ~110MHz, so the wideband design requirement cannot be satisfied. Thus a wideband energy harvesting network design cannot satisfy the above two requirements for low power energy harvesting simultaneously.

E. Analysis of Multiband Energy Harvesting The above discussion shows that a wideband approach is unlikely to meet the dual requirements for low power energy harvesting applications over a wide frequency band. However, the available RF energy is not equally distributed over the whole frequency band, as shown by a prior survey [6]. Much of RF power lies at two primary power peaks (900 and 1900MHz). Thus, a dual-/multi-band energy harvester

takes better advantage of the available RF ambient energy sources. We thus investigated the possibility of using a dual-band energy harvesting network to meet the requirements.

Figure 8 Schematic of the two parallel RLC dual-band boosting networks.

The main idea underlying the dual band energy harvester design is to make the impedance in one branch infinite while the other branch is at resonance, and vice versa. In this way, we obtain both power matching and voltage boosting at two frequencies simultaneously. Figure 8 shows the circuit schematic of the dual-band matching network. Two narrow frequency bands are centered at 900MHz ( ) and 1900MHz ( ), which are the two highest power peaks in [6].

Branches 1 and 2 in Figure 8 are designed to resonate at frequencies (900MHz) and (1900MHz), respectively:

(10)

At frequency , the impedances of the two branches are given by R1,C1,L1 and R2,C2,L2 in series, respectively.

(11) Assuming Q2 is infinite, Equation 11 shows that Zinput2 is equal to infinity. The network is fully described by branch 1 which is a series connected RLC network. In reality, a matching network with quality factor of 8 is achievable, and the signal losses due to branch 2 are virtually negligible. The same argument applies at frequency n other words, the topology in Figure 8 obtains power matching and voltage boosting at two different frequencies, while incurring minimal losses. This approach avoids the limitation on the bandwidth and voltage boosting of the network described by Equation 9 because the bandwidth of the matching network is 80MHz at

each center frequency instead of being 1000MHz (900-1900MHz) wide, as it is for the wideband matching scheme. In summary, our analysis shows that it is possible to have two parallel connected RLC networks that obtain power matching and voltage boosting for different narrow bands. Moreover, the dual-/multi-band energy harvesting scheme is also suitable for power distribution based on the existing ambient RF energy sources. In the next section, we show how we design and implement a multi-band energy harvester.

III. DUAL -BAND ENERGY HARVESTER

A. Design for Dual-/Multi-band Energy Harvesting The minimal input signal power is as low as -19dBm, which corresponds to a 35 mV input voltage using standard 50 Ohm matching. Our design specifications dictate that a minimum of 1V output voltage is necessary. The energy harvester thus needs to have 30-fold AC to DC voltage boosting. In this design, we seek to use on-chip inductors to boost the input signal voltage. Existing on-chip inductors typically have quality factors <10. The maximum DC output voltage of a single-stage voltage doubler with -19dBm input power is well below 1V even with ideal diodes. It is thus necessary to cascade a few voltage doublers together to obtain 1V output voltage. However, having more stages will lead to more power leakage due to the increased parasitic capacitors and resistors. Thus, a minimal number of cascading stages needs be chosen to minimize the signal losses. Due to parasitic losses as well as the threshold voltage of the diodes, simulation results show that a minimum of four voltage doublers is necessary to generate greater than 1V output voltage. While a four-stage cascaded voltage doubler is chosen at 1900MHz to meet the 1V output voltage specification, a five-stage cascaded voltage doubler is chosen at 900MHz. This is due to the fabrication limitations on the large on-chip inductor that is required at the lower frequency (900MHz) for a four-stage cascaded voltage doubler.

After choosing the number of cascaded stages, we used circuit simulation tools (RFDE/ADS) to optimize the harvester impedance at 900 and 1900MHz. Our simulation indicates that 12 Ohm impedance achieves the highest voltage boost and simultaneous power matching with the antenna, and thus the highest conversion efficiency. The voltage boosting is limited by the inductors’ quality factor. Figure 9 shows the circuit diagram of the designed dual-band energy harvester. The upper circuit is comprised of five cascaded voltage doublers to achieve optimized efficiency at 900MHz, while the lower circuit used four cascaded voltage doubler circuits to achieve optimized efficiency at 1900MHz. The optimized output resistors (ROPT and RHOPT) are chosen to maximize the AC to DC conversion efficiency. The gates of the MOSFET-connected diodes are self-biased using the generated output voltage along with off-chip resistor and capacitor networks. The self biasing voltage is optimized using Cadence software. Figures 10 and 11 show the post-layout simulated output voltage and efficiency of the dual-band energy harvester around two centered frequencies, 900 and 1900MHz, respectively. The results account for the circuit devices as

well as the parasitic components introduced when the integrated circuitry is laid out on a silicon substrate. The optimized load resistors ROPT and RLOPT are 1.5Mohms and 1Mohms, respectively. The source voltage and impedance represents our designed dual band antenna. The simulation results show the harvester output voltage is 1.448V@900MHz and 1.12V@1.9GHz for input power of -19dBm. The simulated efficiencies are 14%@900MHz and 11.4%@1.9GHz for input power of -19dBm. The conversion efficiency of the harvester is given by the ratio of the output harvested power to the input power:

(12)

where Vout, Rload, and Pin are the output voltage, load impedance, and input power respectively.

Figure 9 Circuit schematic of the designed dual-band energy harvester.

Figure 10: (a) The post-layout simulated output voltage for an input power of -19dBm near 900MHz and 1900MHz.

(a) (b)Figure 11: The post-layout simulated power conversion efficiency for an input

power of -19dBm near 900MHz and 1900MHz.

B. Dual-band Monopole Antenna DesignBased on the dual-band harvester system requirements, the harvester antenna requires:

1. A monopole antenna due to the single end energy harvester design;

2. An antenna impedance of 50Ohm at 900MHz and 12Ohm at 1900MHz to maximize the power transfer between the antenna and the harvester;

3. High efficiency (>90%). We build on previous investigators’ work in order to design our dual band antenna [15] and [16]. In our work, we developed a modification in which a dual-band antenna is designed to meet the above requirements. Figure 12 shows the layout of the monopole antenna. The long arm resonates at 900MHz with 50Ohm radiation resistance, while the two short arms resonate at 1900MHz with 12 Ohm radiation resistance. Figure 13 shows the HFSS S-parameter simulation results of the designed monopole antenna. They show that the antenna S11 is less than -10dB at 900MHz for a 50 Ohm load. They also show the antenna S11 is less than -12dB at 1900MHz for a 12 Ohm load. The reflection power is fairly low according to the simulated S11, indicating that the antenna is well matched to the designed dual-band harvester.

Figure 12 Layout of the monopole dual-band antenna.

Figure 13(top): Simulated S11 of the dual-band antenna with 50 Ohm impedance. (bottom): Simulated S11 of the dual-band antenna with 12 Ohm

impedance.

IV. MEASUREMENT Figure 14 shows a photograph of the fabricated dual-band energy harvester chip. The harvester is fabricated using an eight metal layer CMOS process and the chip die is 2x2 mm 2. The chip is packaged using quad flat no leads (QFN) technology. The packaged chip die has 28 pins and the size is 5x5 mm2.

The packaged energy harvester chip is mounted on the surface of the designed PCB board. Figure 15 is a photograph of the fabricated dual-band energy harvester, which includes the chip, the self-biasing network and the integrated antenna

Figure 16 shows that the measured output voltage of the dual-band energy harvester which agrees well with the values predicted by our design methodologies. The output voltage yields two peaks, with values of more than 1.0volt at the desired frequencies around 900MHz and 2000MHz. The conversion efficiency of the dual-band energy harvester varies with frequency and is greater than 9% at the desired bands. The input signal that gives rise to these results is -19.3dBm at 900MHz and -19dBm at 2000MHz. The small frequency difference (1900MHz to 2000MHz) between simulation and measurement is due to the parasitic extraction accuracy. These results are obtained for direct injected signals. In addition, the harvester generated similar output values when we used in when simply walking outdoors in free space on the University of Maryland campus. Table 1 summarizes this work as compared to previous published work.

Figure 15 Photograph of the fabricated energy harvester with integrated antenna.

(b)Figure 16 (a): The measured output voltage of the dual-band energy harvester varies with frequency (the input signal is -19.3dBm at 900MHz and -19dBm

at 2000MHz); (b): The measured conversion efficiency of the dual-band energy harvester varies with frequency (the input signal is -19.3 at

900MHz and -19dBm at 2000MHz).

V. SUMMARY

Harvested RF energy is a promising source to power mobile devices directly or charge a battery or significantly extend battery lifetime. In this paper, we first model and analyze the voltage doubler composed of MOSFET-connected diodes. Detailed analysis of the voltage doubler was given. Following the analysis results of the voltage doubler, we discussed how to use antenna impedance as a system parameter to improve the cascaded voltage doubler

efficiency. Our study shows that it is extremely unlikely to achieve high voltage boosting over a wide frequency region even with ideal circuit components because of both the voltage boosting and the wide bandwidth requirements of the matching network. We conclude that wideband energy harvesting is not optimal for low power ambient energy harvesting. Instead, we use a multiband approach. Survey results show that there are power peaks at different frequency bands [6]. Even though, the ambient RF energy is relatively low, by using voltage boosting and power matching techniques, a useful amount of RF energy can be extracted from the environment. Multi-band energy harvesting schemes can harvest much of the ambient RF energy. By studying the characteristics of the available RF energy and the power solution requirements for low power mobile applications, a design specification for the RF harvester is determined. Two parallel narrow band harvesters have been connected to achieve both power matching and voltage boosting in two different bands, simultaneously. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (900MHz and 2000MHz) at an input power as low as -19dBm. Power is extracted both by direct injection in the laboratory, as well as in free space. The DC output voltage of this harvester is over 1V, which can be used to recharge the battery to form an inexhaustibly powered communication system.

APPENDIX: MODEL OF THE MOSFET CONNECTED DIODE

MOSFET-connected diodes are easy to fabricate in a standard CMOS process and thus are preferred devices in order to lower chip costs. In this appendix we explain how we obtained the MOSFET equivalent circuit components in Figure 4 that we used to analyze and design the RF harvester. Figure A.1 (a) shows the MOSFET-connected diode. When a negative voltage is applied between source and gate in Figure A.1 (a) (Vin is negative), then Vgs is positive and there is current is flowing up from the drain to the source. It is also worth mentioning that, even though we employ a resonant voltage boosting strategy as discussed earlier, Vgs is typically smaller than the MOSFET threshold voltage and thus the MOSFET operates in subthreshold in our application. Under these conditions, current voltage characteristics can reflect gated diode-type operation thus making the equivalent circuit more intuitive. When a positive voltage is applied between source and gate (Vin is positive) Vgs is negative as shown in Figure A.1 (a),

Design This work [4] [5] [1] [7] [3] [2]

Technology 0.13m 0.30 m 0.35 m CMOS FERAM

0.5m 0.25 m Schottky diode Schottky diode

Efficiency 9.1%@900MHz-19.3dBm

8.9%@2.0GHz-19dBm

1.2%@950MHz-14dBm

15%@953MHz-9dBm

14.5%@869MHz-20dBm

5%@2.45GHz@-13.5dBm

8.6%@906MHz-20dBm(5.6MOhm)

22%@906MHz-20dBm(optimal)

20%@2.45GHz-20dBm

20%@2.45GHz-20dBm

Output voltage

1.15V@900MHz -19.3dBm

1.05V@2.0GHz-19dBm

1.5V-14dBm

>1V-9dBm

1.5V 2.2V (5.6Mohm)N/A (optimal)

Less than 1V Less than 1V

Bandwidth 870- 940MHz N/A N/A N/A 902-928MHz N/A N/A

Dual /Multi band

Yes No No No No No No

the channel is depleted of mobile electrons and thus has little current(close to zero current). Since the circuit in Figure A.1 (a) has current flowing when Vin is negative and close to zero current when Vin is positive. This mechanism can be modeled by an ideal diode and channel resistance (RCH). The channel resistance RCH is a function of the input signal voltage Vin

(voltage between gate and source), and the diode would typically be reverse biased under these conditions.

We also must include the MOSFET capacitances since they are vital to the operation, especially the voltage boost, of the circuit. The source to body capacitance is modeled as CSB. The gate to source capacitance is modeled as CGS and RG

models the gate polysilicon resistance of the MOSFET. The lumped model is shown in Figure A.1 (b). In our designed circuit, the gate voltage is preset to a DC biasing voltage. It can increase the current flowing from G to S and has a similar mechanism.

Figure A.1 (c) shows the simplified circuit of the original circuit shown in Figure A.1 (b), where a transformation of series RC network to parallel RC network is performed. The series connected components RG and CGS in Figure A.1 (b) can be transformed to be parallel connected, leading to the terms CGSp and RGp, as provided below. Finally, we combine the parallel capacitors CSB and CGSp into a single equivalent capacitor CT, and we obtain the relatively simple diode connected MOFET equivalent circuit in Figure A.1 (d), which we insert in Figure 4 to help design and analyze the energy harvester.

(A.1)

(a) (b)

(c) (d)

Figure A.1 Model of the CMOS connected diode. (a) Diode-connected

MOSFET. (b) Lumped model of the diode-connected MOSFET. (c) Lumped model of the diode-connected MOSFET after series to parallel transformation.

(d) Simplified lumped model of diode-connected MOSFET.

In order to obtain good conversion efficiency, the power loss due to the gate impedance needs to be minimized. The power loss due to gate impedance is described by Equation A.2:

(A.2)The power through the diode is used for energy harvesting

is described by equation A.3:

(A.3)The power loss due to gate resistance needs to be much

less than harvesting power:

(A.4) From Equation A.2, A.3 and A.4, we can obtain equation

A.5:

(A.5)

Equation A.5 can be further simplified to Equation A.6, which indicates that the parasitic gate resistance needs to be sufficiently small to satisfy Equation A.6, and thereby use the presented MOSFET model in our design process for obtaining high conversion efficiency at low ambient power levels. By using multi-finger layout technique, Equation A.6 can be satisfied at the power level around -19dBm.

(A.6) Figure A.1 (c) can be further simplified to Figure A.1 (d) by combining the parallel connected capacitors (CSB and CGS) to CT and ignore the gate resistor. The non-linearity of the diodes is described by the ideal diodes and RCH in the lumped model, as shown in Figure A.1 (d).

ACKNOWLEDGMENT

This study has been supported by the Laboratory for Physical Sciences, and the Office of Naval Research under grant number N000140911190.

REFERENCES

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[3] Olgun, U.; Chi-Chih Chen, “Investigation of Rectenna Array Configurations for Enhanced RF Power Harvesting ”, IEEE Antennas and Wireless Propagation Letters, pp262-265, 2011.

[4] T. Umeda, H. Yoshida, S. Sekine, Y. Fujita, T. Suzuki and S. Otaka, a 950MHz rectifier circuit for sensor network tags with 10-m distance, IEEE Journal of Solid-State Circuits, Volume 41, issue 1, Jan 2006. (first paper on floating gate recitifier)

[5] Nakamoto, H.,  Yamazaki, D. , Yamamoto, T. , Kurata, H. , Yamada, S. , Mukaida, K. , Ninomiya, T. , Ohkawa, T. , Masui, S. , Gotoh, K. , A passive UHF RFID Tang LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35um FeRam Technology, IEEE International Solid-State Circuits Conference, 2006, pp 1201-1210, Feb. 6-9, 2006 

[6] T. S. Salter. "Low Power Smartdust Receiver with Noval Applications and improvements of an RF Power Harvesting Circuit", PhD Theisis, University of Maryland, College Park, 2009.

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Bo Li received his Ph.D. degree in electrical engineering with the University of Maryland, College Park in 2012.

His academic research includes analog integrated circuit design such as continuous filter, analog to digital converter, novel RF circuits, and ambient RF energy harvesting. He had published over ten journal and conference papers on low-power analog/RF circuits, including low-noise amplifiers, low power mixer, phase locked loop, low power transceiver, and RF energy harvester. He had interned with Integrated Device Technology (IDT) and Broadcom in 2011. He is currently an analog/RF design engineer in Texas Instruments. He also has one pending patent.

Xi Shao received the B.S. degree in Space Physics from the University of Science and Technology of China (1996), the Ph.D. degree in Astronomy (2001), and the M.S. degree in Electric Engineering with Microelectronics major, both from the University of Maryland (2004). He is currently a research associate at Department of Astronomy, University of Maryland. He has authored/co-authored over 30 scientific publications in various areas. He is experienced in antenna design for various RF communication applications. He is member of IEEE, American Geophysical Union, and American Physical Society.

Negin Shahshahan received her master degree in microelectronics from University of Maryland college park. She is currently working toward her PhD degree.

Neil Goldsman received the Ph.D. degree in electrical engineering from Cornell University, Ithaca, NY, in 1989.

He is currently a Professor with the Department of Electrical and Computer Engineering, University of Maryland, College Park. He directs the Mixed Signal VLSI Design Laboratory and the Semiconductor Device Simulation Laboratory, University of Maryland. He is an originator of the Legendre polynomial/spherical harmonic Boltzmann approach to device simulation. He has written two educational texts in electronics, which were used at the University of Maryland, and has published more than 100 technical papers. He has recently focused on mixed-signal VLSI, radio-frequency CMOS circuit design, wideband-gap semiconductors, and nanoscale devices, including carbon nanotubes. His research interests are device, material, and circuit modeling and design. Dr. Goldsman was the recipient of the National Science Foundation’s Research Initiation Award, the University of Maryland IEEE Professor of the Year Award, the George Corcoran Award for Contributions to Education, and the IEEE Benjamin Dasher Award.

Thomas Salter received his PhD from University of Maryland College Park in 2008. His research interests focus on low power RF receiver and energy harvester. He is currently a research scientist in Laboratory for Physical Sciences. He has authored or coauthored more than 10 papers or conference proceedings, and has one pending patents. George Metze (SM’00) received the B.S. degree in electrical engineering from the University of California at Berkeley, the M.S. degree in electrical engineering from the University of Illinois, Urbana-Champaign, IL, and the Ph.D. degree in electrical engineering from Cornell University, Ithaca, NY, in 1972, 1974, and 1981, respectively. From 1981 to 1987, he was a Member of the Technical Staff at the Massachusetts Institute of Technology, Lincoln Laboratory, where he conducted research on novel microwave and mm-wave semiconductor devices. From 1987 to 1994, he was a Senior Member of the Technical Staff, as well as Department Manager, at the Communications Satellite Corporation. During this period, he lead COMSAT’s efforts to produce some of the world’s best performing low noise, high speed MIMICs available. In 1995, he joined the University of North Carolina at Charlotte as an Associate Professor, where he continued his research on mm-wave components until 1998. In 1998, he joined the Laboratory for Physical Sciences, University of Maryland, College Park, where he is Senior Scientist and Program Manager for the laboratories’ 3DI effort. He has authored or coauthored more than 100 papers or conference proceedings, and has four patents.Dr. Metze is a former IEEE Distinguished Lecturer.

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