unit v cmos testing final

8/13/2019 Unit v Cmos Testing Final

1/76

Unit VMOS TestingV.Vaithianathan, M.Tech, (Ph.D)

Assistant Professor/ECE

SSN College of Engineering


2/76

Discussion

Lecture 1Need for Testing

Lecture 2 Manufacturing TestPrinciples

Lecture 3 Design Strategies for Test

Lecture 4Chip Level Test Techniques

Lecture 5 System Level TestTechniques


3/76

Lecture 1Need for Testing

Objectives of Testing

TestCategories


4/76

Why Testing?

Testing is one of the most expensive parts

of chips Logic verification accounts for > 50% of

design effort for many chips

Debug time after fabrication has enormousopportunity cost

Shipping defective parts can sink a company

Example: Intel FDIV bug

Logic error not caught until > 1M unitsshipped

Recall cost $450M (!!!)


5/76

Why Testing? Yield = Number of good die / Total number of die

per wafer. Because of the complexity of the manufacturing

process, not all die on a wafer function correctly.

Dust particles and small imperfections in

starting material or photo masking can result ina bridged connections or missing features andthese imperfections are called faults.

Testing a chip can occur at

Wafer level Packaged chip level

Board level

System level

Field level.


6/76

Why Testing?

By detecting a malfunctioning chip early, themanufacturing cost can be kept low.

The approximate cost to a company of detecting a fault atthe various levels is

Level Approximate Cost

Wafer Level $0.01 - $0.10

Packaged Chip Level $0.10 - $1

Board Level $1 - $10

System Level $10 - $100

Field Level $100 - $1000


7/76

Testing at Various Levels


8/76

Objectives of Testing Two primary objectives

Fault Detection & Fault location

FaultAny condition that causes a device tofunction improperly.

Fault Detection Testing

The process of determining whether or nor a fault ispresent in a given device.

A set of inputs to a circuit that can be used to detect afault in the circuit is a Fault Detection Test Set (FDTS)

Fault Location Testing The process of determining which fault is present in a

faulty device.

A set of inputs that can be used to locate a fault is a

Fault Location Test Set (FLTS)


9/76

TestCategories

Functionality Tests(Logical Verification)

Silicon Debug

Manufacturing Tests


10/76

Logical Verification

Does the chip simulate correctly? Usually done at HDL level

Verification engineers write test bench for

HDL Cant test all cases

Look for corner cases

Try to break logic design

Ex: 32-bit adder Test all combinations of corner cases as

inputs:

0, 1, 2, 231-1, -1, -231, a few random numbers


11/76

Silicon Debug

Confirm that the chip operates as it was

intended and help debug any discrepancies.

Run on the first batch of the chips that return

from the fabrication.

If you are lucky, they work the first time, If not???

Much more extensive than the first one because

the chip can be tested at a full speed in a

system.

Required to locate the cause of failures because

the designer has less visibility into the

fabricated chip compared to during design

verification.


12/76

Silicon Debug

Logic bugs vs. electrical failures

Most chip failures are logic bugs frominadequate simulation

Some are electrical failures

Crosstalk Dynamic nodes: leakage, charge sharing

Ratio failures

A few are tool or methodology failures (e.g.DRC)

Fix the bugs and fabricate a correctedchip


13/76

Manufacturing Tests

Verify that every transistor, gate and

storage element in the chip functionscorrectly.

Conducted on the manufactured chip

before shipping to the customer to verifythat the silicon is completely intact.

A speck of dust on a wafer is sufficient to

kill chip Yield of any chip is < 100%

Must test chips after manufacturing beforedelivery to customers to only ship good parts


14/76

Manufacturing Tests

Manufacturing testers

are very expensive Minimize time on tester

Careful selection of

test vectors

Same tests can be used for all three steps It is easier to use one set of tests to chase down

the logic bugs and another, separate setoptimized for manufacturing defects.


15/76

Lecture 2

Manufacturing TestPrinciples

Fault ModelsObservability & Controllability

Fault Coverage

Automatic Test Pattern Generation (ATPG)Delay Fault Testing


16/76

Combinational Circuit Testing


17/76

Types of Faults

FaultAny condition that causes a device to

function improperly. Solid or Permanent Fault

A faulty condition that does not change with time.

Intermittent Fault A faulty condition that appears and disappears with

time.

Logical Faults Faults that cause a given logical device to function

entirely different logic device. Non Logical Faults

All faults other than logical faults


18/76

Stuck-at Fault Model

A popular and useful

model for representingfaults in the logicdevice.

Types of model Stuck-at logic zero (s-a-0) Stuck-at logic one (s-a-1)

These faults are due to Gate oxide shorts

Metal-to-metal shorts


19/76

Short-Circuit Faults Other Names: Stuck-

closed faults or Bridgingfaults

The short S1 results in anS-A-0 fault at input A

The short S2 modifies the

function of the gate. To ensure the most

accurate modeling, faultsshould be modeled at the

transistor level becausethe complete circuitstructure is known only atthis level.


20/76

Identifying Stuck-closedFaults By observing static current (IDD)

while applying test vectors A 2-input NOR gate

FaultThe drain connection on apMOS transistor is shorted to VDD.

This fault occurs due to theoverlapping of stray metal on theVDDline and drain connections.

Identifying the faults Apply the test vectors 01 or 10 to the

A and B inputs Measure the static IDD Notice that it rises to some value

determined by size of the nMOStransistors.


21/76

OpenCircuit Faults

Convert a combinational

logic circuit into asequential logic circuit.

A 2-input NOR gate.

One of the transistors

rendered is ineffective.If the nMOS transistor Ais stuck open, then thefunction displayed by

the gate will be

where Z is the previousstate of the gate.

Z = A + B + B Z'


22/76

Observability & Controllability

Observability Ease of observing a node by watching external output

pins of the chip

Controllability

Ease of forcing a node to 0 or 1 by driving input pinsof the chip

Combinational logic is usually easy to observeand control

Finite state machines can be very difficult,requiring many cycles to enter desired state

Especially if state transition diagram is not known tothe test engineer


23/76

To increase Testability

Increase Observability Add more pins (?!)

Add small probe bus, selectively enable different values

onto bus

Use a hash function to compress a sequence of values

(e.g., the values of a bus over many clock cycles) into a

small number of bits for later read read-out

Cheap read read-out of all state information

Increase Controllability Use muxes to isolate sub sub-modules andselect sources of

test data as inputs

Provide easy setup of internal state


24/76

Fault Coverage A measure of goodness of a set of test vectors.

What percentage of the chips internal nodes were

checked?

Should be excess of 98.5% fault coverage.

Procedure

Take each circuit node in sequence.

Held to 0 (S-A-0)

Identify the faults

Held to 1 (S-A-1)

Identify the faults

Total nodes detected as faultyFault Coverage =

Test vectors applied


25/76

Test Pattern Generation

Manufacturing test ideally would checkevery node in the circuit to prove it is notstuck.

Apply the smallest sequence of testvectors necessary to prove each node isnot stuck.

Good Observability and controllability

reduces number of test vectors requiredfor manufacturing test.

Reduces the cost of testing

Motivates design-for-test

A t ti T t P tt


26/76

Automatic Test PatternGeneration (ATPG)

For given fault, determine excitation vector

(called test vector) that will propagate error to

primary (observable) output.

Majority of available tools: combinationalnetworks only

Sequential ATPG available from academic

research.


27/76


Most ATPG approaches have been based onsimulation.

A five vale logic is used to implement test

generation algorithms

1 Logic One

0 Logic Zero

X Unknown or Dont Care ConditionD Logic 1 in good machine. Logic 0 in faulty

machine

D Logic 0 in good machine. Logic 1 in faulty

machine


28/76


Truth Table for Inverter

A Z

0 1

1 0

X X

D D

D D


29/76


Truth Table for 2-inpt AND gate

A \ B 0 1 X D D

0 0 0 0 0 0

1 0 1 X D D

X 0 X X X X

D 0 D X D 0D 0 D X 0 D


30/76


Truth Table for 2-inpt OR gate

A \ B 0 1 X D D

0 0 1 X D D1 0 1 1 1 1

X X 1 X X X

D D 1 X D 1D D 1 X 1 D


31/76


32/76


33/76

Delay Fault Testing

Timing is alsoincluded.

Still works withincreased tpdf.

Fault becomesequential as thedetection of the faultdepends on theprevious state of thegate.

Occurs due tocrosstalk.

Occurs in SOI due tohistory effect.


34/76

Fault Sampling Used in circuits where it is impossible to fault

every node in the circuit. Nodes are randomly selected and faulted. The resulting fault detection rate may be

statistically inferred from the number of faultsthat are detected in the fault set and size of the

set. It is important that the randomly selected faults

be unbiased. This approach does not yield specific level of

fault coverage but it will determine whether thefault coverage exceeds a desired level. The level of confidence may be increased by

increasing the number of samples.


35/76

Design for Testability

Ad hoc Testing

Scan Based Test TechniquesSelf Test Techniques

IDDQ Testing

Lecture 3Design Strategies for Test


36/76

Design For Testability (DFT)

Two concepts Controllability & Observability

Design for Testability

Ad hoc testing

Scan based approaches

Self test and built-in testing

Adh T ti


37/76

Adhoc Testing

Ad Ad-hoc test techniques are acollection of ideas aimed at reducingthe test time.

Common techniques are:

Partitioning large sequential circuits

Adding test points

Adding multiplexers

Providing for easy state access

Adh T ti


38/76

Adhoc Testing

Adh T ti


39/76

Adhoc Testing Bus Oriented technique

Adh T ti


40/76

Adhoc Testing Multiplexer based testing

S D i


41/76

Scan Design

To provide observability & controllability

to each register.

Convert each flip-flop to a scan register

Only costs one extra multiplexer

Normal mode: flip-flops behave as usual

Scan mode: flip-flops behave as shift

register

Contents of flops can be scanned out and

new values scanned in.


42/76

Scan Design

S D i S i l S


43/76

Scan DesignSerial Scan

S D i P ll l S


44/76

Scan DesignParallel Scan

B ilt i S lf T t (BIST)


45/76

Built in Self Test (BIST)

BIST lets blocks test themselves.

Generate pseudo-random inputs tocombinational logic.

Combine outputs into a syndrome.

With high probability, block is fault-free ifit produces the expected syndrome

Rapidly becoming more important with

increasing chip-complexity and largermodules


46/76

Built in Self Test (BIST)

P d R d S


47/76

Pseudo Random SequenceGenerator (PRSG)

Linear Feedback Shift Register

Shift register with input taken

from XOR of state

Step Q

0 111

1 110

2 101

3 010

4 100

5 001

6 011

7 111

Pseudo Random Sequence


48/76

Pseudo Random SequenceGenerator (PRSG)

IDDQ Testing


49/76

IDDQ Testing

A method of detectingbridging faults (shorts).

CMOS logic should drawno current when its not

switching. When a bridging fault

occurs, for somecombination of the input,a measurable IDD flows.

IDDQ Testing


50/76

IDDQ Testing Testing Sequence

Apply normal vectorsAllow the signals to settleMeasure IDD.

Suitable for testing only one gate

High test time

IDDQ testing can be performed

Externally to the chip by measuring the current

drawn on the VDDline

Internally using specially constructed testvectors.


51/76

Lecture 4Chip Level Test Techniques

Regular Logic Arrays

Memories

Random Logic


52/76

Regular Logic Arrays

Parallel Scan or Series Scan

Input busses may be driven by aserially loaded register.

These in turn may be used to load the

internal data path registers. These data path registers may be

sourced onto a bus, and this bus may

be loaded into a register that may beserially accessed.

All of the control signals to the datapath are also made scannable.


53/76

Memories

Use self testing techniques.

Alternatively, the provision of multiplexers ondata inputs and addresses and convenientexternal access to data outputs enables the

testing of embedded memories. It is a mistake to have memories indirectly

accessible.

Because memories have to tested exhaustively

and any overhead on writing and reading thememories can substantially increase the testtime.


54/76

Random Logic

Probably best tested via full serial scan orparallel scan.


55/76

Lecture 5

System (Board) LevelTest Techniques

Boundary Scan

Boundary Scan


56/76

Boundary Scan

System (Board) Level Defects

Open and shorted PCB traces and incompletesolder joints.

Bed-of-nails Testers

At the board level, chips obeying the standardmay be connected in a variety of series and

parallel combinations for board testing (replacing

bead of nails)

The IEEE 1149.1 boundary scan architectureprovides a standardized serial scan path

through the I/O pins of a chip (also called

JTAGJoint Test Access Group)

Boundary Scan Architecture


57/76

Boundary Scan Architecture

Boundary Scan


58/76

Boundary Scan

All the I/O pins are connected serially in astandardized chain accessed through theTest Access Port (TAP).

Every pin can be observed and controlled

remotely through the scan chain. Standardized tests:

Connectivity tests between components

Sampling and setting chip I/Os

Distribution an collection of self self-test or

built-in test results

Test Access Port (TAP)


59/76


TAP has four or five single-bit connections.

TCKTestClock

InputClocks tests into and out of thechip

TMSTestMode

Select

Input Controls test operations

TDITestData In

Input Test Data into the chip

TDOTestDataOut

OutputTest data out of the chip. Drivenonly when TAP controller isshifting out test data .

TRST

(optional)

TestReset

InputReset the TAP controller if noreset signal is generatedautomatically by the chip.



60/76




61/76

It consists of

TAP Interface Pins

A set of two or more test-data registers (DR)to collect data from the chip.

An instruction register (IR) specifying the typeof test to perform.

A TAP controller, which controls the scan bitsthrough the instruction and test-data registers

Two modes of operation It scans an instruction into the IR specifying

what boundary scan should do

It scan data in and out of the DR.


Test Access Port


62/76

The specification requires at least two

test-data registers. Boundary Scan Register

Associated with all the inputs and outputs on thechip so that boundary scan can observe and

control the chip I/Os.

Bypass Registers

A single FF used to accelerate testing by avoidingshifting data into the boundary scan registers of

idle chips when only a single chip on the board isbeing tested.

Internal Scan Chain or BIST are optionaladditional DRs.

Test Access Port

TAP Controller


63/76

TAP Controller

TAP Controller


64/76

TAP Controller A 16-state FSM that proceeds from state to state

based on the TCK and TMS signals. It provides signals that control the DR and IR.

It is initialized to Test-Logic-Reset by TRST or byinternal signal.

It moves from one state to the next state on therising edge of the TCK signal based on TMS.

Typical test sequence

Give TCK - Perform TRSTGive TCK - Perform

operation based on TMS

Operations

Serially loading IR

Serially loading or reading DR

Instruction Registers


65/76


At least two bits long. Boundary scan requires at least two DRs.

IR specifies which DR will be placed in thescan chain when the DR is selected.

IR determines where the DR will load itsvalue from in the Capture-DR state andwhether the values will be driven to output

pads or core logic.



66/76

Instruction Registers The following instructions are required

BYPASS Places the Bypass Register in the DR chain so thatthe path from TDI to TDO involves only by a single FF.

Allows specific chips to be tested in a serial scanchain.

Represented with all 1s in the IR.

SAMPLE/PRELOAD

Places the Boundary Scan Register in the DR chain

In Capture-DR state, it copies the I/O values into DRs.

EXTEST Allows for the testing of off-chip circuitry.

Similar to SAMPLE/PREOAD, but also drives values

from DRs on to the output pads.INTEST(optional)

Allows a single step testing of internal circuitry viaboundary scan registers.

RUNBIST

(optional)

Used to activate internal self testing procedures withina chip.



67/76

Instruction Registers A typical IR bit is shown in figure.

In the Capture-IR state, data is given and then shiftedout in the shift-IR when new vales are shifted in.

In the Update-IR state, the contents of shift register arecopied in parallel to the IR output to load the entireinstruction at once.

Data Registers


68/76

Data Registers

Data Registers


69/76

Data Registers

Used to set the inputs of the modules to be

tested and collect the results of running tests. Consists of boundary scan register and a

bypass register.

Represents the scan chain within the chip.

MUX selects which DR is routed to the TDO pin.

When internal DRs are added, the IR decodermust produce extra control signals to select

which one is in the DR chain for the particularinstruction.

Boundary Scan Register


70/76




71/76


Connects all the I/O circuitry.

Consists of a shift register for the scan chainand an additional bank of FFs to update theoutputs in parallel.

MUX allows to override the normal path throughthe I/O pad.

Can be configured as input or output.

Bypass Register


72/76

Bypass Register

When executing the BYPSS instruction, the

single-bit bypass register is connected betweenTDI & TDO.

A single FF, cleared during Capture-DR andScanned during Shift-DR.

TDO Driver


73/76

TDO Driver TDO pin shifts out the LSB of IR during Shift-IR

or the LSB of DR during Shift-DR. TDO change on the falling edge of the TCK.

Multiplexers choose among instruction register,boundary scan register or bypass register.

Complete Boundary Scan


74/76

p yImplementation

Complete Boundary Scan


75/76

p yImplementation

A complete boundary scan for a chip with 4 inputs {a[1], a[2], a[3], a[4]} and

4 outputs {y[1], y[2], y[3], y[4]}.

It consists of

TAP controller state machine & state controller

A 3-bit IR with instruction decode.

Bypass register

4 boundary scan output pads.


76/76

Queries ?????

[email protected]

unit v cmos testing final

Documents