unit i: ic fabrication and circuit configuration for...

EC2254 –LINEAR INTEGRATED CIRCUITS – II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 1

UNIT – I: IC FABRICATION AND CIRCUIT CONFIGURATION FOR LINEAR IC

PART -A (2 Marks)

1. State the advantages of Integrated circuits over discrete components[AUC NOV 2013]

Reduced size.

Low power consumption.

High speed of operation.

2. Define offset voltage of an operational amplifier[AUC NOV 2013]

A small voltage applied to the input terminals to make the output voltage as zerowhen the two input terminals are grounded is called input offset voltage.

3. What are the two requirements to be met for a good current source? [AUC MAY 2012]

The output current Io should not be dependent on β.

The output resistance of the current source should be very high.

4. List the various methods of realizing high input resistance in a differential amplifier. [AUC MAY 2012]

Use of darlington pair.

Use of FET.

Use of swamping resistance.

5. What are the applications of current source.[AUC MAY 2011]

Transistor current sources are widely used in analog ICs both as biasingelements and as load devices for amplifier stages.

6. Define slew rate. [AUC MAY 2011]

The slew rate is defined as the maximum rate of change of output voltage causedby a step input voltage.An ideal slew rate is infinite which means that op-amp’s outputvoltage should change instantaneously in response to input step voltage.

7. What is the need for frequency compensation in practical op-amps? [AUC MAY 2011]

Frequency compensation is needed when large bandwidth and lower closed loopgain is desired. Compensating networks are used to control the phase shift and henceto improve the stability.

8. What is the need for constant current source in differential amplifier? [AUC MAY 2011]

superior insensitivity of circuit performance to power supply variations and temperature.

more economical than resistors in terms of die area required to provide bias currents of small value.

When used as load element, the high incremental resistance of current source results in high voltage gain at low supply voltages.

9. Justify the statement: CMRR value of an ideal op-amp should be infinite. [ AUC MAY 2011]

CMRR ρ = Ad / Ac For an op-amp Ad is large and Ac is zero . Hence CMRR is infinite.


10. Define CMRR. [AUC April 2004,MAY2010]

The relative sensitivity of an op-amp to a difference signal as compared to acommon –mode signal is called the common –mode rejection ratio. It is expressedin decibels. CMRR= Ad/Ac

11. What is the reason for drop in gain at high frequencies in op-amp?[AUC MAY2010]

The open-loop gain of op-amp decreases at higher frequencies due to thepresence of parasitic capacitance. The closed-loop gain increases at higher frequenciesand leads to instability.

12. Draw a neat sketch showing the frequency response of μA741 OP AMP.[AUC Nov 2004]

13. Write down the characteristics of ideal operational amplifier.[AUC May 2005,Nov 2006]

Open loop voltage gain Zout 0

Output impedance Zin Infinity

Input offset current Ios 0

Bandwidth BW 0

CMRR ρ Infinity

Slew rate S Infinity

PSRR PSRR 0

14. Draw the equivalent circuit of an ideal amplifier.[AUC June 2006]


15. An opamp circuit shown in figure has differential gain Ad=5mv.Calculate V0. [AUC Nov 2006]

Vo = -5v2 + 5 V1= 5(V1-V2)

16. Compare the ideal and practical characteristics of op-amp.[Nov 2006]

17. What does the term linear circuits generally convey?[Nov 2007]

In linear circuits the output electrical signals vary in proportion to the applied input signal.


18. Give the circuit schematic of simple current mirror circuit.[AUC Nov 2007]

19. Define unity gain bandwidth of an Op-Amp.[AUC April 2008]

Unity gain bandwidth is defined as the bandwidth of an Op-Amp when the voltage gain is unity.

20. Define slew rate. What causes it ?[AUC May 2008,May2009]

The slew rate is defined as the maximum rate of change of output voltage caused by a

step inputvoltage.An ideal slew rate is infinite which means that op-amp’s output voltage

should changeinstantaneously in response to input step voltage.

21. State the applications of band gap reference circuit[AUC Nov 2008]

Voltage regulator

ADC and DAC circuits

V-F and F-V converters

22. What is a current mirror circuit? What are its advantages?[AUC Nov 2008]

The circuit in which the output current is forced to equal the input current is called as current mirror circuit.

Advantages:

Requires less components than constant current bias circuits.

Circuit is simple and easy to fabricate.

Using matching transistors, thermal stability is achieved.

23. Define current mirror.[AUC May 2009]

The circuit in which the output current is forced to equal the input current is called as current mirror circuit.

0

R2

1k

Q1

Q2N3721

0

Q2

Q2N3721


24. List the basic blocks of an op-amp. [AUC Nov2009]

Input stage

Intermediate stage

Level shifting stage

Output stage

25. How can you increase the input resistance of an op-amp.[AUC Nov2009]

Use of darlington pair.

Use of FET.

Use of swamping resistance.

PART-B

1. Explain the construction of a monolithic bipolar transistor [AUC NOV 2013] Step -1 Wafer preparation

P-type silicon wafer is prepared.

The wafers are usually of 10cm diameter and 0.4 mm thickness.

The resistivity of the wafer is 10 Ω -cm Step -2 Epitaxial Growth

An n type epitaxial film is grown over p- type substrate.

All active and passive components are fabricated wiyhin this layer.

The resistivity of n – type epitaxial layer is 0.1 to 0.5 Ω -cm


Step -3 Oxidation

A Sio2 layer of thickness of the order of 0.02 to 2 µm is grown on the n-epitaxial layer.

Step -4 Isolation Diffusion

The integrated circuits contains many transistors .

The collectors of all transistors are electrically connected together.

Hence , it is necessary to isolate one from another.

This is done by forming two windows in the Sio2 by means of photolithography and etching.

The P+ material is diffused through this windows until it reaches the substrate.

This process establishes an isolation island.

Step -5 Base Diffusion

The wafer is again covered by an Sio2 layer.

The base mask is used to form windows into which the p-type bases are diffused.

The base must be aligned so that it does not touch the isolator.

Step -6 Emitter Diffusion

A Sio2 layer is grown over to cover the wafer surface and an emitter mask is used to form the wndows.

The masking and etching process removes the Sio2 .

A heavily doped N-region is diffused through the windows.

The N+ region improves current gain and minimizes emitter resistance.

The base under the emitter diffuses into other region.


Step -7 Contact mask

The contact mask cuts holes in the sides to allow electrical connection of the wire.

Step -8 Metallization The metallization is used to interconnect components and to provide external

access to the integrated circuits. Step -9 Passivation The entire surface is covered by a passivation layer for long term stability.

2. i)With neat diagrams ,explain the operation of voltage reference circuit using temperature compensation , voltage reference circuit using avalanche diode reference.(16) [AUC MAY 2012]

Voltage Reference circuit using temperature compensation scheme: The voltage reference circuit using basic temperature compensation scheme is shown below.

This design utilizes the close thermal coupling.

A constant current I is supplied to the avalanche diode DB and it provides a bias voltage of VB to the base of Q1.

The temperature dependence of the VBE drop across Q1 and those across D1 and D2 results in respective temperature coefficients.

Hence, with the use of resistors R1 and R2 with tapping across them at point N compensates for the temperature drifts in the base-emitter loop of Q1 .

This results in generating a voltage reference VR with normally zero temperature coefficient.


Applying KCL at node N, we get

=

Assuming VBE(Q1)= VBE(D1)=VBE(D2)=VBE

Then Eq can be expressed as

(V B -2V BE - V R)/ R1 = (V R -V BE) / R2

Therefore, the voltage level VR is given by

V R =R2V B +V BE (R1 - 2R2) / R1 + R2

Differentiating VB and VBE in eq(2) partially with respect to temperature, we get

0 =R2 / (R1 + R2) V B / T +( R1 - 2R2 / R1 + R2) V BE / T V B / T R2 / (R1 + R2) = (R1 - 2R2 / R1 + R2 ) V BE / T

That is,

R1-2R2 / R2 =

Therefore, it can be inferred that eq(3) is to be satisfied for obtaining zero temperature coefficient.


Voltage Reference circuit using Avalanche Diode Reference:

A voltage reference can be implemented using the breakdown phenomenon condition of a

heavily doped PN junction.

The zener breakdown is the main mechanism for junctions, which breakdown at a voltage of 5V

or less. For integrated transistors , the base-emitter breakdown voltage falls in the range of 6 to

8V.

Therefore, the breakdown in the junctions of the integrated transistor is primarily due to

avalanche multiplication.

The base bias for transistor Q1 is provided through register R1 and it also provides the dc

current needed to bias DB, D1and D2 .

The voltage at the base of Q1 is equal to the zener voltage VB added with two diode drops due

to D1 and D2 .

The voltage across R2 is equal to the voltage at the base of Q1 less the sum of the base –

mitter voltages of Q1 and Q2 .

Hence, the voltage across R2 is approximately equal to that across DB = VB . Since Q2 and Q3

act as a current mirror circuit, current I0 equals the current through R2 .

Therefore, I 0 = V B / R2

It shows that, the output current I0 has low temperature coefficient, if the temperature coefficient

of R2 is low, such as that produced by a diffused resistor in IC fabrication.

The zero temperature coefficient for output current can be achieved, if diodes are added in

series with R2 , so that they can compensate for the temperature variation of R2 and VB .

The temperature compensated avalanche diode reference source circuit is shown in figure.


The transistor Q4 and Q5 form an active load current mirror circuit. The base voltage of Q1 is the voltage VB across zener DB . Then, VB = (VBE * n) +VBE across Q1 + VBE across Q2 + drop across R2 . Here, n is the number of diodes. It can be expressed as V B = Io R2 +( n+2) VBE Differentiating for VB , I0 , R2 and VBE partially, with respect to temperature T, we get


Therefore, zero temperature coefficient of I0 can be obtained, if the following condition is satisfied, That is,

3. a) Explain the working of a current source with a circuit diagram.[AUC Apr 2005] CURRENT MIRROR CIRCUIT:

DEFINITION: The circuit in which the output current is forced to equal the input current

is called as current mirror circuit.

Block diagram :

Analysis :

Circuit consists of two transistors q3 & q4.

The base emitter voltages and base currents of two transistors are same.

Vbe3=vbe4, ib3=ib4.

Similarly ic3=ic4.

CURRENT MIRROR

I source V0

I sink

Isource =Isink

0

R2

1k

Q1

Q2N3721

0

Q2

Q2N3721

i2 ib3

ic3=i2

Vbe3

Vbe4

-vee

ib4

To diff.

amp

Ic4


Applying KCL at node a:

I2=ic4+i

Applying KCL at node b:

I2=ib3+ib4

I=2ib3=2ib4

I2=ic4+2ib4

I2 =ic3+2ib3

We have ib3 =ic3 /β

I2=ic3 + 2ic3/ β

I2 =ic3(1+2/ β) = ic3+ic3(2/ β)

Β >> 2/ β

Hence i2 ~ ic3

The collector current of q3 is nearly equal to current i2 .hence current mirror circuit provides

constant current bias to the differential amplifier.

Advantages:




Uses:

Used in differential and operational amplifiers.

4. Explain the operation of a basic differential amplifier. [AUC Apr 2005,2006] (or)

Draw the circuit diagram of a symmetrical emitter coupled difference amplifier and show that a very high CMRR will result if the diff.amp is supplied by a constant current bias.[AUC Nov 2004]

Differential amplifier: The function of a differential amplifier is to amplify the difference between two signals. The need for differential amplifier arises in many physical measurements where response from dc to many MHz of frequency is required. This forms the basic input stage of an integrated amplifier.


The basic differential amplifier has the following important properties of 1. Excellent stability 2. High versatility and 3. High immunity to interference signals The differential amplifier as a building block of the op-amp has the advantages of 1. Lower cost. 2. easier fabrication as IC component. 3. closely matched components.

The two transistors Q! and Q2 have exactly matched characteristics.

The two collector resistances Rc1 and Rc2 are equal.

The differential amplifier can be obtained by using two emitter biased circuits .

This is done by coupling emitter of two transistors together.

Rc1 = Rc2 = Rc and RE1 =RE2 = RE .

The transistor Q1 is biased by supply voltage VS1 and Q2 by VS2. Operation The operation of differential amplifier is explained in two modes.

1.Differntial mode operation. 2.Common mode operation.

Differential Mode


In a differential mode ,the two input signals are different from each other.

Consider the two signals which are same in magnitude but 180°out of phase.

Signals with opposite phase are obtained from centre tap transformer.

V0 is taken across collector of Q1 and collector of Q2.

The V0 is twice as large as the input signal voltages .

Common mode operation

The signals applied to base of transistors Q1 and Q2 are obtained from the same

source.

The two input signals are equal in magnitude and phase.

The output voltage is the difference between the two collector voltages which

equals to zero.

5. a)Define CMRR ,PSRR and slew rate of an op-amp. [AUC Dec 2006]

CMRR : CMRR is defined as the ratio of differential gain to common mode gain. CMRR is ∞ for an ideal op –amp.

PSRR : PSRR is defined as the ratio of the change in input offset voltage due to the

change in supply voltage producing it.

Slew Rate : Slew rate is defined as the maximum rate of change of output voltage with

respect to time ,usually specified in V/µs.

b) Find the slew rate of a frequency compensated op-amp at room temperature

which has a unity cross-over frequency of 5MHz.

Slew Rate = 2 *π * Vm * fm = 2 *π * 1* 5*106 =31.4 V/µs.


6. a) Explain the working of a simple current source.[AUC Nov 2006]

CURRENT MIRROR CIRCUIT:

DEFINITION: The circuit in which the output current is forced to equal the input current

is called as current mirror circuit.

Block diagram :

Analysis :

Circuit consists of two transistors q3 & q4.

The base emitter voltages and base currents of two transistors are same.

Vbe3=vbe4, ib3=ib4.

Similarly ic3=ic4.

Applying KCL at node a:

I2=ic4+i

CURRENT MIRROR

I source V0

I sink

Isource =Isink

0

R2

1k

Q1

Q2N3721

0

Q2

Q2N3721

i2 ib3

ic3=i2

Vbe3

Vbe4

-vee

ib4

To diff.

amp

Ic4


Applying KCL at node b:

I2=ib3+ib4

I=2ib3=2ib4

I2=ic4+2ib4

I2 =ic3+2ib3

We have ib3 =ic3 /β

I2=ic3 + 2ic3/ β

I2 =ic3(1+2/ β) = ic3+ic3(2/ β)

Β >> 2/ β

Hence i2 ~ ic3

The collector current of q3 is nearly equal to current i2 .hence current mirror circuit provides

constant current bias to the differential amplifier.

Advantages:




Uses:

Used in differential and operational amplifiers.

b .Write notes on dominant –pole compensation used in op-amps.


The principle of dominant pole compensation is to create a pole at a sufficient low

frequency fd to force the gain roll off at a rate of -20 dB/decade.

The dominant pole compensation raises the phase margin to a positive value and

improves stability.

Implementation of dominant pole compensation

The loop gain A of the op-amp having three break frequencies is given by

Where Av=open loop gain of op-amp and f1 ,f2 ,f3 are break over frequencies.

The external RC network has been introduced in order to obtain the dominant pole at a

much lower frequency fd as compared to f1.

Let the transfer function of the RC compensating network be denoted by A’

=

The RC network forms a voltage divider across V01

V0 = Voltage across C =

A’= =

Let fd = be the break frequency of the compensating network

The transfer function of the compensated op-amp will be product of A and A’

A1 = AA’

Advantages

The stability of op-amp is improved.

Due to reduced bandwidth , the noise immunity is improved.


c) Explain the concept of widlar current source used in op amp circuits.

Widlard current source :

Currents of low magnitude are obtained by using widlar current source.

Analysis :

The two transistors are identical but due to emitter resistance Re,Vbe1 & Vbe2 are different.

Applying KVL to the base emitter loop

Vbe1=vbe2+(iB2+ic2)Re----------------1

Vbe1-Vbe2=(iB2 +ic2) Re---------------2

By assumption

iC1=i3.eVbe1/vT

iC2=i3. eVbe2/vT

where “Is” is the reverse saturation current

iC1/ic2= e (Vbe1-Vbe2) / vT

ib1

R3

1k

Q3

Q2N3721

ic2=i2

vbe1

vcc

iref

ib2

b

vbe2

0

ic1

Re

1k

Q1

Q2N3721


taking natural logarithm on both sides we get

ln(ic1/ic2) = Vbe1- Vbe2/ Vt

Vbe1 – Vbe2 = Vt ln (iC1/ic2)-------------------3

Equating 2 and 3 we get

Vt ln(ic1/ic2) = (ib2+ic2) Re

Due to large value of β ,iB2 can be neglected

Ic2Re= Vt ln(ic1/ic2)-------------4

Equation 4 is called transcendental equation

7. Describe the cause of slew-rate limiting and its effect on the highest frequency of

undistorted sinusoidal output.[AUC Dec 2007]

Reason for Slew rate: There is usually a capacitor within 0, outside an op-amp oscillation. It is this capacitor which

prevents the o/p voltage from fast changing input. The rate at which the volt across the

capacitor increases is given by

\dVc/dt = I/C --------(1)

I -> Maximum amount furnished by the op-amp to capacitor C.

Op-amp should have the either a higher current or small compensating capacitors.

For 741 IC, the maximum internal capacitor charging current is limited to about 15μA. So the

slew rate of 741 IC is

SR = dVc/dt |max = Imax/C .

For a sine wave input, the effect of slew rate can be calculated as consider volt follower -The

input is large amp, high frequency sine wave .

If Vs = Vm Sinwt then output V0 = Vm sinwt . The rate of change of output is given by

dV0/dt = Vm w coswt.


The max rate of change of output across when coswt =1

(i.e) SR = dV0/dt |max = wVm.

SR = 2ΠfVm V/s = 2ΠfVm v/ms.

Thus the maximum frequency fmax at which we can obtain an undistorted output volt of

peak value Vm is given by

fmax (Hz) = Slew rate/6.28 * Vm .called the full power response.

It is maximum frequency of a large amplitude sine wave with which op-amp can have without

distortion.

b)Explain how the feed-forward compensation extends the BW of an OPAMP.

Feed forward compensation creates a high frequency by pass and increases the phase

margin.

Overall gain of A of the uncompensated op-amp is expressed as the product of A1 and

gain of the A2 .

At low frequency f =0 and h(if)=0

At high frequency f=∞ and h(if)=1


Thus the system behavior is completely controlled by a2 and the effect due a1(jf) is

completely eliminated. The frequency response obtained is given below

Disadvantages :

At the time of transistion from anew(jf) to a2 (jf) the phase of anew(jf)may approach to -180°

before transition and this may produce excessive ringing effect.

If phase lag -180° occurs at transition ,signal cancellation results which produces a notch

in the compensated response.

The capacitor Cc is connected between the terminal 2 and terminal 1.

A small capacitor Cf is needed across Rf to ensure frequency stability.

The frequency f0 of the bypass function is

This type of compensation gives high slew rate of about 10V/µs and full power bandwidth over

200 KHz


8. What is a current mirror circuit? Discuss in detail the widlar current source.[AUCApril

2008]

DEFINITION: The circuit in which the output current is forced to equal the input current is

called as current mirror circuit.

Widlard current source :

Currents of low magnitude are obtained by using widlar current source.

Analysis :

The two transistors are identical but due to emitter resistance Re,Vbe1 & Vbe2 are different.

Applying KVL to the base emitter loop

Vbe1=vbe2+(iB2+ic2)Re----------------1

Vbe1-Vbe2=(iB2 +ic2) Re---------------2

By assumption

iC1=i3.eVbe1/vT

iC2=i3. eVbe2/vT

where “Is” is the reverse saturation current

ib1

R3

1k

Q3

Q2N3721

ic2=i2

vbe1

vcc

iref

ib2

b

vbe2

0

ic1

Re

1k

Q1

Q2N3721


iC1/ic2= e (Vbe1-Vbe2) / vT

taking natural logarithm on both sides we get

ln(ic1/ic2) = Vbe1- Vbe2/ Vt

Vbe1 – Vbe2 = Vt ln (iC1/ic2)-------------------3

Equating 2 and 3 we get

Vt ln(ic1/ic2) = (ib2+ic2) Re

Due to large value of β ,iB2 can be neglected

Ic2Re= Vt ln(ic1/ic2)-------------4

Equation 4 is called transcendental equation

9. Explain a) Band gap reference b) Methods of improving slew rate.[AUC April

2008,may2010]

10. Band Gap references :

It is not possible to use zener reference circuits in the lower supply voltage circuits using

operating supply voltage as 5v or less. In such cases band gap reference circuits can be

used.

It uses a widlard current source with transistors q1 and Q2 where q1 and Q2 are

matched npn transistor.

Current density of q1 is 10 times higher than q2 thus q1 is operating at high current

density

Applying KVL to basr emitters of q1 & q2 thro’ R3 we get

Vr3= Vbe1-Vbe2=ΔVbe

According to Ebers moll equation

Ic1=Is . eVbe1/vT

Ic2=Is . eVbe2/vT


Vcc

Ic1/Ic2= e (Vbe1-Vbe2) / vT

ln(ic1/ic2)=Vbe1-Vbe2 / VT

Vbe1 –Vbe2 = Vt ln (ic1 / ic2)

Vr3 = Vt ln (ic1 / ic2)

Neglecting base current of q2

Ic2= Ic3

Ir3= Vr3/r3 = Vt ln(Ic1/ Ic2) / r3

Ic2= Vt ln[ ic1 /ic2]

Ic2 is directly proportional to vt

ic2

0

R9

1k

vbe3

ic3

Q7

Q2N3721

vref

R8

1k

R

1k

vbe2

io

vbe1

Q1

Q2N3721

Q6

Q2N3721


Method of improving slew rate

Slew rate is given by S= Imax / C

From fig ,we can write

I01(sat) = C dv02 /dt

dv02 /dt = I01(sat) / C

Now the gain of third stage a3 =1 hence V0 = V02

dv0 / dt = dv02 /dt = I01(sat) / C

But maximum rate of change of output voltage is the slew rate.

S= I01(sat) / C

The relation between input voltage and output current for an amplifier is

Output current = gm (differential input)

Op –amp gain (a )= Vo / Vp – Vn = gm1 / 2 πf C

a f = gm1 / 2 π C

C= gm1 / 2 π ft

S= 2 π ( Io1 / gm1) ft

Hence methods of improving slew rate are

i. Increasing ft

By reducing the value of the internal capacitor ft can be increased.

ii. Increasing Io1

by providing additional input transistor we can able to increase I01.

iii .Reducing gm1

By adding resistances in series with the emitters of the differential input transistors.


V2

FREQ = VAMPL = VOFF =

I2

0

vcc

0

I10Adc

-vee

V1

FREQ = VAMPL = VOFF =

Rs1

1k

I1

Q5

Q2N2907/TEMP

0

Q4

Q2N2907/TEMP

Rs2

1kQ1

Q2N3721

Q2

Q2N3721

11. a)What is an active load? Explain the CE amplifier with active load.[AUC Dec2008]

ANALYSIS OF DIFFERENTIAL AMPLIFIER WITH ACTIVE LOADS

The differential mode gain Ad is proportional to the collector resistance Rc.

Disadvantages when selecting maximum value of Rc

Large value of resistance requires large chip area.

For large Rc, drop across it increases and hence a large power supply will be required

to maintain a given collector current.

Iee

Generally current mirror circuit has very low dc resistance (dv/di) and higher ac

resistance (dv/di).

Hence the dc conditions should not get disturbed by the collector resistance .but it must

provide large resistance for ac conditions.

Hence the current mirror circuit can be used as a collector load instead of Rc. Such load

is called as an active load.

The drop across current mirror circuit is the function of the supply. This eliminates the

need of high biasing supply voltage. It basically acts as a current source and provides

large ac resistance.

Under ac condition Vs1=vs2=0

As T1 and T2 are marched transistors hence i1=i2=Iee/2 where base currents of t1 and

t2 are neglected .Transistors t3 & t4 form a current repeater hence i=i1=i2.


The load current Il entering the next stage is IL=I-I2=0

When vs1 increases over vs2 current I1 increases whereas I2 decreases as i1+i2=iee.

Also current I remains equal to i1 due to current mirror action.

Thus active load provides very high ac resistance and hence high differential mode

voltage gain.

b)Explain the pole –Zero compensation.






=

Let z1=R1 , Z2 =R2-jxc2 the output voltage Vo across Z2 is

V0 = Z2 /( Z1+Z2) = =

.Vo1

A’ = = =f1



A1 = AA’

12. Define slew rate and explain the methods to improve slew rate[AUC Nov09]

Slew Rate : Slew rate is defined as the maximum rate of change of output voltage with respect

to time ,usually specified in V/µs.




dv02 /dt = I01(sat) / C


dv0 / dt = dv02 /dt = I01(sat) / C


S= I01(sat) / C





a f = gm1 / 2 π C

C= gm1 / 2 π ft

S= 2 π ( Io1 / gm1) ft


i. Increasing ft


ii. Increasing Io1

By providing additional input transistor we can able to increase I01.

iii .Reducing gm1

By adding resistances in series with the emitter of the differential input transistors

13. Explain the working principle of monolithic IC op-amp. [AUC Nov09]

IC 741 Bipolar operational amplifier:

The op-amp circuit consists of three stages.

1. the input differential amplifier

2. The gain stage

3. the output stage.

A bias circuit is used to establish the bias current for whole of the circuit in the IC. The op-amp is

supplied with positive and negative supply voltages of value • 15V, and the supply voltages as

low 5V can also be used.


Bias Circuit:

The reference bias current IREF for the 741 circuit is established by the bias circuit

consisting of two diodes-connected transistors Q11 and Q12 and resistor R5. The widlar

current source formed by Q11 ,Q10 and R4 provide bias current for the differential

amplifier stage at the collector of Q10.

Transistors Q8 and Q9 form another current mirror providing bias current for the

differential amplifier.

The reference bias current IREF also provides mirrored and proportional current at the

collector of the double –collector lateral PNP transistor Q13.

The transistor Q13 and Q12 thus form a two-output current mirror with Q13A providing

bias current for output stage and Q13B providing bias current for Q17. The transistor

Q18 and Q19 provide dc bias for the output stage.

Q14 and Q20 and they establish two VBE drops of potential difference between the

bases of Q14 and Q18 .

Input stage:

The input differential amplifier stage consists of transistors Q1 through Q7 with biasing

provided by Q8 through Q12.

The transistor Q1 and Q2 form emitter – followers contributing to high differential input

resistance, and whose output currents are inputs to the common base amplifier using Q3

and Q4 which offers a large voltage gain.

The transistors Q5, Q6 and Q7 along with resistors R1, R2 and R3 from the active load

for input stage.

The single-ended output is available at the collector of Q6. the two null terminals in the

input stage facilitate the null adjustment. The lateral PNP transistors Q3 and Q4 provide

additional protection against voltage breakdown conditions.

The emitter-base junction Q3 and Q4 have higher emitter-base breakdown voltages of

about 50V. Therefore, placing PNP transistors in series with NPN transistors provide

protection against accidental shorting of supply to the input terminals.


Gain Stage:

The Second or the gain stage consists of transistors Q16 and Q17, with Q16 acting as

an emitter – follower for achieving high input resistance.

The transistor Q17 operates in common emitter configuration with its collector voltage

applied as input to the output stage.

Level shifting is done for this signal at this stage.

Internal compensation through Miller compensation technique is achieved using the

feedback capacitor C1 connected between the output and input terminals of the gain

stage.

Output stage:

The output stage is a class AB circuit consisting of complementary emitter follower

transistor pair Q14 and Q20 . Hence, they provide an effective loss output resistance and

current gain.

The output of the gain stage is connected at the base of Q22 , which is connected as an

emitter – follower providing a very high input resistance, and it offers no appreciable

loading effect on the gain stage.

It is biased by transistor Q13A which also drives Q18 and Q19, that are used for

establishing a quiescent bias current in the output transistors Q14 and Q20.

14. Explain briefly the necessary functions of different stages of op-amp with respect to

its block schematic. [AUC MAY 2010]

IC 741 Bipolar operational amplifier:

The op-amp circuit consists of three stages.

1. the input differential amplifier

2. The gain stage

3. the output stage.

A bias circuit is used to establish the bias current for whole of the circuit in the IC. The op-amp is

supplied with positive and negative supply voltages of value • 15V, and the supply voltages as

low 5V can also be used.


Bias Circuit:

The reference bias current IREF for the 741 circuit is established by the bias circuit

consisting of two diodes-connected transistors Q11 and Q12 and resistor R5. The widlar

current source formed by Q11 ,Q10 and R4 provide bias current for the differential

amplifier stage at the collector of Q10.

Transistors Q8 and Q9 form another current mirror providing bias current for the

differential amplifier.

The reference bias current IREF also provides mirrored and proportional current at the

collector of the double –collector lateral PNP transistor Q13.

The transistor Q13 and Q12 thus form a two-output current mirror with Q13A providing

bias current for output stage and Q13B providing bias current for Q17. The transistor

Q18 and Q19 provide dc bias for the output stage.

Q14 and Q20 and they establish two VBE drops of potential difference between the

bases of Q14 and Q18 .

Input stage:

The input differential amplifier stage consists of transistors Q1 through Q7 with biasing

provided by Q8 through Q12.

The transistor Q1 and Q2 form emitter – followers contributing to high differential input

resistance, and whose output currents are inputs to the common base amplifier using Q3

and Q4 which offers a large voltage gain.

The transistors Q5, Q6 and Q7 along with resistors R1, R2 and R3 from the active load

for input stage.


The single-ended output is available at the collector of Q6. the two null terminals in the

input stage facilitate the null adjustment. The lateral PNP transistors Q3 and Q4 provide

additional protection against voltage breakdown conditions.

The emitter-base junction Q3 and Q4 have higher emitter-base breakdown voltages of

about 50V. Therefore, placing PNP transistors in series with NPN transistors provide

protection against accidental shorting of supply to the input terminals.

Gain Stage:

The Second or the gain stage consists of transistors Q16 and Q17, with Q16 acting as

an emitter – follower for achieving high input resistance.

The transistor Q17 operates in common emitter configuration with its collector voltage

applied as input to the output stage.

Level shifting is done for this signal at this stage.

Internal compensation through Miller compensation technique is achieved using the

feedback capacitor C1 connected between the output and input terminals of the gain

stage.

Output stage:

The output stage is a class AB circuit consisting of complementary emitter follower

transistor pair Q14 and Q20 . Hence, they provide an effective loss output resistance and

current gain.

The output of the gain stage is connected at the base of Q22 , which is connected as an

emitter – follower providing a very high input resistance, and it offers no appreciable

loading effect on the gain stage.

It is biased by transistor Q13A which also drives Q18 and Q19, that are used for

establishing a quiescent bias current in the output transistors Q14 and Q20.

15. a)Write down the ideal characteristics of op-amp [MAY 2010,NOV 2013]


b) Explain in detail about frequency compensation applied in operational amplifier.

[ AUCMAY 2010]

Pole – zero compensation






=

Let z1=R1 , Z2 =R2-jxc2 the output voltage Vo across Z2 is

V0 = Z2 /( Z1+Z2) = =

.Vo1

A’ = = =f1


A1 = AA’


Dominant Pole Method






=

The RC network forms a voltage divider across V01

V0 = Voltage across C =


A’= =

Let fd = be the break frequency of the compensating network


A1 = AA’

Advantages

The stability of op-amp is improved.

Due to reduced bandwidth , the noise immunity is improved.

16. With a neat sketch explain the operation of a differential amplifier with Constant

current source. [AUC MAY 2011,NOV 2013]

.


The differential gain Ad is given by Ad = hfe.Rc /(Rs+hie)

To improve Ad it is necessary to increase the value of Rc .

To increase Rc we have to increase Vcc in order to keep Ic constant.

Higher value of Rc needs larger chip area .

Hence current mirror is used in place of Rc.

Dc Analysis

Assume all transistors are matched

IQ is divided equally between Q1 and Q2

I1 =I2 = IQ/2

From diagram

IE5 = IB3 +IB4

= I3 /β + I4 /β

IB5 = IE5 /(1+β) = I3+I4 /β(1+β)

If the base currents are small I3+I4 = IQ

IB5 =IQ/ β(1+β)

From diagram

I3 +IB5 = I1 and I4+Io=I2

Since I1=I2

I3 +IB5 = I4+I0

But I3 =I4

IB5 = Io

Substituting the value of IB5 we get

Io= IQ/ β(1+β)


17. Explain the following i) DC characteristics ii) AC characteristics of an op-amp. [AUC

MAY 2011]

DC Characteristics of op-amp: Current is taken from the source into the op-amp inputs respond differently to current and

voltage due to mismatch in transistor.

DC output voltages are,

1. Input bias current

2. Input offset current

3. Input offset voltage

4. Thermal drift

Input bias current:

Input bias current is the average of the currents flowing into the two input terminals of the op-

amp.

IB=IB1+IB2/2

Ideally IB1 and IB2 must be zero

But in practical op-amp they are not same due to finite value of input resistance.

Bias current compensation

Current IB+ flowing through the compensating resistor Rcomp, then by KVL we get,

-V1+0+V2-Vo = 0 (or)

Vo = V2 – V1

By selecting proper value of Rcomp, V2 can be cancelled with V1 and the Vo = 0. The value of

Rcomp is derived as

V1 = IB+ Rcomp (or) IB+ = V1/Rcomp


The node ‘a’ is at voltage (-V1). Because the voltage at the non-inverting input terminal is (-V1).

So with Vi = 0 we get,

I1 = V1/R1

I2 = V2/Rf

For compensation, Vo should equal to zero (Vo = 0, Vi = 0). i.e. from equation (3) V2 = V1. So

that,

I2 = V1/Rf

KCL at node ‘a’ gives,

IB- = I2 + I1

I B- =V 1/R f +V 1/R1

I B- = V 1[R1 + R f/R1 R f]

Assume IB- = IB+

V 1[R1 + R f/R1 R f]

V 1/Rcomp

Rcomp = R1 || Rf

i.e. to compensate for bias current, the compensating resistor, Rcomp should be equal to the

parallelcombination of resistor R1 and Rf.

Input offset current:

Bias current compensation will work if both bias currents IB+ and IB- are equal.

Since the input transistor cannot be made identical. There will always be some small

difference between IB + and IB-. This difference is called the offset current

|Ios| = IB+ - IB-

Input offset voltage:

Inspite of the use of the above compensating techniques, it is found that the output voltage may

still not be zero with zero input voltage [Vo ≠ 0 with Vi = 0]. This is due to unavoidable

imbalances inside the op-amp and one may have to apply a small voltage at the input terminal

to make output (Vo) = 0.

This voltage is called input offset voltage Vos. This is the voltage required to be applied at

the input for making output voltage to zero (Vo = 0

Thermal Drift:

The input offset voltage is dependent on the changes in temperature .This is expressed

mathematically as TC ( Vios) = ∂Vios /∂T

Where T= Temperature in °K


AC Characteristics :

Frequency Response:

The variation in operating frequency will cause variations in gain magnitude and its phase angle.

The manner in which the gain of the op-amp responds to different frequencies is called the

frequency response.

Op-amp should have an infinite bandwidth Bw =∞ (

There is one pole due to R0 C and one -20dB/decade. The open loop voltage gain of an op-

amp with only one corner frequency is obtained from above fig.

V 0 =-jX C [ AOL Vd / R0-jX C]

V 0= 1/j2πfc / R0+ 1/j2πfc (Aol .Vd)

Vo= (Aol .Vd) /1/j2πfcR0

Aol(f) = Vo/Vd = Aol /1/j2πfCR0

f0 = 1/2πCR0

Aol(f) = Vo/Vd = Aol /1/j(f/f0)

MOD (Aol(f)) = Aol /√1/j(f/f0)2

The magnitude and phase angle characteristics from eqn (29) and (30)

For frequency f<< f1 the magnitude of the gain is 20 log AOL in dB.

At frequency f = f1 the gain in 3 dB down from the dc value of AOL in dB. This

frequency f1 is called corner frequency.

For f>> f1 the fain roll-off at the rate off -20dB/decade or -6dB/decade.


Circuit Stability:

A circuit or a group of circuit connected together as a system is said to be stable, if its o/p

reaches a fixed value in a finite time.

A system is said to be unstable, if its o/p increases with time instead of achieving a fixed value.

The criterian gn is used when the system is to be tested practically.

Any system whose stability is to be determined can represented by the block diagram.

The block between the output and input is referred to as forward block and the block between

the output signal and f/b signal is referred to as feedback block. The content of each block is

referred“Transfer frequency’ From fig we represented it by AOL (f) which is given by

AOL (f) = V0 /Vin if Vf = 0. -----(1)

where AOL (f) = open loop volt gain. The closed loop gain Af is given by

AF = V0 /Vin

AF = AOL / (1+(AOL ) (B) ----(2)

B = gain of feedback circuit.

B is a constant if the feedback circuit uses only resistive components. Once the magnitude Vs

frequency and phase angle Vs frequency plots are drawn, system stability may be determined

as follows


1. Method:1:

Determine the phase angle when the magnitude of (AOL ) (B) is 0dB (or) 1. If phase angle is > .-

1800 , the system is stable. However, the some systems the magnitude may never be 0, in that

cases method 2, must be used.

2. Method 2:

Determine the phase angle when the magnitude of (AOL ) (B) is 0dB (or) 1. If phase angle is > .-

1800 , If the magnitude is –ve decibels then the system is stable. However, the some systems

the phase angle of a system may reach -1800 , under such conditions method 1 must be used

to determine the system stability.

SLEW RATE

Slew Rate : Slew rate is defined as the maximum rate of change of output voltage with respect

to time ,usually specified in V/µs.




dv02 /dt = I01(sat) / C


dv0 / dt = dv02 /dt = I01(sat) / C


S= I01(sat) / C




a f = gm1 / 2 π C

C= gm1 / 2 π ft

S= 2 π ( Io1 / gm1) ft



i. Increasing ft


ii. Increasing Io1

By providing additional input transistor we can able to increase I01.

iii .Reducing gm1

By adding resistances in series with the emitter of the differential input transistors

unit i: ic fabrication and circuit configuration for...

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