Central Processing UnitUNIT-2

* / 44Register setCUCPU Introduction

Introduction

3 major parts of CPU :Register Set ALU Control Unit

IntroductionThe central processing unit (CPU) of a computer is the main unit that dictates the rest of the computer organization

1. Register set: Stores intermediate data during the execution of instructions;2. Arithmetic logic unit (ALU): Performs the required micro-operations for executing the instructions;3. Control unit: supervises the transfer of information among the registers and instructs the ALU as to which operation to perform by generating control signals.

General Register OrganizationMemory locations are needed for storing pointers, counters, return address, temporary results, and partial products during multiplication.Memory access is the most time-consuming operation in a computer More convenient and efficient way is to store intermediate values in processor registers

General Register Organization* / 44R1R2R3R4R5R6R7MUXMUXALU3 x 8 DecoderLDSELDSELASELBOPRInputAB

General Register Organization2 MUX : select one of 7 register or external data input by SELA and SELB BUS A and BUS B : form the inputs to a common ALU ALU : OPR determine the arithmetic or logic microoperation The result of the microoperation is available for external data output and also goes into the inputs of all the registers 3 X 8 Decoder : select the register (by SELD) that receives the information from ALU

General Register OrganizationBinary selector input : 1) MUX A selector (SELA) : to place the content of R2 into BUS A2) MUX B selector (SELB) : to place the content of R3 into BUS B3) ALU operation selector (OPR) : to provide the arithmetic addition R2 + R4) Decoder selector (SELD) : to transfer the content of the output bus into R15)Control Word 14 bit control word (4 fields) : SELA(3 bits) : select a source register for the A input of the ALUSELB(3 bits) : select a source register for the B input of the ALUSELD(3 bits) : select a destination register using the 3 X 8 decoderOPR(5 bits) : select one of the operations in the ALU

Examples of ALU Microoperations

General Register Organization* / 44Examples:

OPROperation00000Transfer A00001Increment A00010Add A + B00101Subtract A B00110Decrement A01000AND A and B01010OR A and B01100XOR A and B01110Complement A10000Shift right A11000Shift left A

MicrooperationSELASELBSELDOPRR1 R2 R301001100100101R4 SHL R410000010011000

8.3 Stack OrganizationStack: A storage device that stores information in such a manner that the item stored last is the first item retrieved.Also called last-in first-out (LIFO) list. Useful for compound arithmetic operations and nested subroutine calls. Stack pointer (SP): A register that holds the address of the top item in the stack.SP always points at the top item in the stack Push: Operation to insert an item into the stack. Pop: Operation to retrieve an item from the stack.

REGISTER STACK A stack can be organized as a collection of a finite number of registers.In a 64-word stack, the stack pointer contains 6 bits.The one-bit register FULL is set to 1 when the stack is full; EMPTY register is 1 when the stack is empty.The data register DR holds the data to be written into or read from the stack.

Initialization SP 0, EMPTY 1, FULL 0 Push

SP SP + 1 M[SP] DR If (SP = 0) then (FULL 1) Note that SP becomes 0 after 63 EMPTY 0The following are the micro-operations associated with the stack

DR M[SP]SP SP - 1If (SP = 0) then (EMPTY 1)FULL 0PopThe following are the micro-operations associated with the stack

Stack OrganizationLIFOLast In First Out* / 44SPStack BottomCurrent Top of Stack TOS0 0 5 50 0 0 80 0 2 50 0 1 50 1 2 3FULLEMPTY

Stack OrganizationPUSHSP SP 1M[SP] DRIf (SP = 0) then (FULL 1)EMPTY 0* / 44SPStack BottomCurrent Top of Stack TOS0 0 5 50 0 0 80 0 2 50 0 1 50 1 2 3FULLEMPTY1 6 9 01 6 9 0Current Top of Stack TOS

Stack OrganizationPOPDR M[SP]SP SP + 1If (SP = 11) then (EMPTY 1)FULL 0* / 44SPStack BottomCurrent Top of Stack TOS0 0 5 50 0 0 80 0 2 50 0 1 50 1 2 3FULLEMPTY1 6 9 01 6 9 0Current Top of Stack TOS

Stack OrganizationMemory StackPUSHSP SP 1M[SP] DRPOPDR M[SP]SP SP + 1* / 44012102202201200100101PCARSP

Reverse Polish NotationInfix Notation:A + BPrefix or Polish Notation:+ A BPostfix or Reverse Polish Notation (RPN):A B +Evaluation procedure of RPN:Scan the expression from left to right.When an operator is reached, perform the operation with the two operands found on the left side of the operator.Replace the two operands and the operator by the result obtained from the operation. * / 44A B + C DA B C D +RPN(2) (4) (3) (3) +(8) (3) (3) +(8) (9) +17

Reverse Polish NotationExample Conversion of RPN(A + B) [C (D + E) + F]* / 44(A B +)(D E +)C F +

Reverse Polish NotationStack Operation(3) (4) (5) (6) +* / 44PUSH 3PUSH 4MULTPUSH 5PUSH 6MULTADD3412563042

CPU OrganizationSingle AccumulatorResult usually goes to the AccumulatorAccumulator has to be saved to memory quite oftenGeneral RegisterRegisters hold operands thus reduce memory trafficRegister bookkeepingStackOperands and result are always in the stack* / 44

Instruction FormatsThree address instructions: Three address registers or memory locations are specified, one for the final result. It is also called general address organization.ADDR1, R2, R3 R1 R2 + R3

Two address instructions: Two address registers or two memory locations are specified, one for the final result. ADDR1, R2R1 R1 + R2

One address instructions: AC and memory. Since the accumulator always provides one operand, only one memory address needs to be specified. ADDMAC AC + M[AR]

Zero address instruction: Stack is used. Arithmetic operation pops two operands from the stack and pushes the result. ADD TOS TOS + (TOS 1)

Instruction FormatsExample: Evaluate X=(A+B) (C+D)Three-AddressADDR1, A, B; R1 M[A] + M[B]ADDR2, C, D; R2 M[C] + M[D]MULX, R1, R2; M[X] R1 R2* / 44

Instruction FormatsExample: Evaluate X= (A+B) (C+D)Two-AddressMOVR1, A; R1 M[A]ADDR1, B; R1 R1 + M[B]MOVR2, C; R2 M[C]ADDR2, D; R2 R2 + M[D]MULR1, R2; R1 R1 R2MOVX, R1; M[X] R1* / 44

Instruction FormatsExample: Evaluate X=(A+B) (C+D)One-AddressLOADA; AC M[A]ADDB; AC AC + M[B]STORET; M[T] AC LOADC; AC M[C]ADDD; AC AC + M[D]MULT; AC AC M[T]STOREX; M[X] AC* / 44

Instruction FormatsExample: Evaluate X=(A+B) (C+D)Zero-AddressPUSHA; TOS APUSHB ; TOS BADD; TOS (A + B)PUSH C; TOS CPUSHD; TOS DADD; TOS (C + D)MUL; TOS (C+D)(A+B)POPX; M[X] TOS* / 44

Instruction FormatsExample: Evaluate X=(A+B) (C+D)RISCLOADR1, A; R1 M[A]LOADR2, B; R2 M[B]LOADR3, C; R3 M[C]LOADR4, D; R4 M[D]ADDR1, R1, R2; R1 R1 + R2ADDR3, R3, R4; R3 R3 + R4MULR1, R1, R3; R1 R1 R3STOREX, R1; M[X] R1* / 44

Addressing ModesImpliedIn this mode the operands are specified implicitly in the definition of the instruction.For example, the instruction complement accumulator is an implied-mode instruction because the operand in the accumulator register is implied in the definition of the instruction.ImmediateThe operand is specified in the instruction itself. In immediate-mode instruction has an operand field rather than address field.The use of a constant in MOV R1, 5, i.e. R1 5RegisterOperands are in resister that reside within the CPU.* / 44

Addressing ModesRegister IndirectIn this mode register contains the address of the operand rather than the operand itself.Autoincrement / AutodecrementIncrement/decrement the register after every access of the table.Direct AddressUse the given address to access a memory location* / 44

Addressing ModesIndirect AddressIndicate the memory location that holds the address of the memory location that holds the data* / 44AR = 1010 1 0 41 1 0 A

Addressing ModesRelative AddressEA = PC + Relative Addr* / 44AR = 1001 1 0 APC = 2+Could be Positive or Negative (2s Complement)

Addressing ModesIndexedEA = Index Register + Relative Addr* / 44AR = 1001 1 0 AXR = 2+Could be Positive or Negative (2s Complement)Useful with Autoincrement or Autodecrement

Addressing ModesBase RegisterEA = Base Register + Relative Addr* / 44BR = 1000 0 0 AAR = 2+Could be Positive or Negative (2s Complement)Usually points to the beginning of an array0 0 0 50 0 1 20 1 0 70 0 5 9

ADDRESSING MODES - EXAMPLES -AddressingModeEffectiveAddressContentof ACDirect address500/* AC (500) */ 800Immediate operand -/* AC 500 */ 500Indirect address800/* AC ((500)) */ 300Relative address702/* AC (PC+500) */ 325Indexed address600/* AC (XR+500) */ 900Register -/* AC R1 */ 400Register indirect400 /* AC (R1) */ 700Autoincrement400 /* AC (R1)+ */ 700Autodecrement399 /* AC -(R) */ 450

Load to AC ModeAddress = 500Next instruction200201202399400450700500800600900702325800300MemoryAddressPC = 200R1 = 400XR = 100AC

CISCComplex Instruction Set ComputerLarge number of instructions with a complicated ALUSome instructions perform specialized tasks and are used infrequentlyLarge variety of addressing modesVariable length instruction formatsInstructions can manipulate operands in memory* / 44

RISC RISC Characteristics Advantages of RISC- VLSI Realization- Computing Speed- Design Costs and Reliability- High Level Language Support- Relatively few instructions- Relatively few addressing modes- Memory access limited to load and store instructions- All operations done within the registers of the CPU- Fixed-length, easily decoded instruction format- Single-cycle instruction format- Hardwired rather than microprogrammed control

CISC versus RISC

CISC RISC Emphasis on hardware Emphasis on software Includes multi-clock complex instructions Single-clock, reduced instruction only Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Register to register: "LOAD" and "STORE" are independent instructions Small code sizes, high cycles per second Low cycles per second, large code sizes Transistors used for storing complex instructions Spends more transistors on memory registers

Homework* / 44

8-1A bus-organized CPU has 16 registers with 32 bits in each, an ALU, and a destination decoder.a. How many multiplexers are there in the A bus, and what is the size of each multiplexer?b. How many selection inputs are needed for MUX A and MUX B?c. How many inputs and outputs are there in the decoder?d. How many inputs and outputs are there in the ALU for data, including input and output carries?e. Formulate a control word for the system assuming that the ALU has 35 operations.

Solution

Homework* / 44

8-7Convert the following arithmetic expressions from infix to reverse Polish notation.a. A B + C D + E Fb. A B + A (B D + C E)c. A + B [C D + E (F + G)] A * [B + C (D + E)]d. F (G + H)

Homework* / 44

8-9Convert the following numerical arithmetic expression into reverse Polish notation and show the stack operations for evaluating the numerical result.(3 + 4) [10 (2 + 6) + 8]

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