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August 2001 Lesson 2 1
Lesson 2
Uninterruptible Power Supply Multi-LoopControl Employing Digital Predictive
Voltage and Current Regulators
Lesson 2Lesson 2
Uninterruptible Power Supply Multi-LoopControl Employing Digital Predictive
Voltage and Current Regulators
August 2001 Lesson 2 2
Goal of the workGoal of the work
Investigation of digital predictive voltage andcurrent regulators in multi-loop configuration forUPS’sMotivations:• high dynamic performance (i.e. low THD with
distorting loads, low overshoot under stepload changes, etc…);
• simple control design and implementation
Investigation of digital predictive voltage andcurrent regulators in multi-loop configuration forUPS’sMotivations:• high dynamic performance (i.e. low THD with
distorting loads, low overshoot under stepload changes, etc…);
• simple control design and implementation
August 2001 Lesson 2 3
Presentation outlinePresentation outlinePresentation outline
• Control technique derivation:• current loop• voltage loop
• Design criteria and implementationissues• Simulation results• Experimental results
•• Control technique derivation:Control technique derivation:•• current loopcurrent loop•• voltage loopvoltage loop
•• Design criteriaDesign criteria and implementation and implementationissuesissues•• SimulationSimulation results results•• ExperimentalExperimental results results
August 2001 Lesson 2 4
UPS system structure and modelUPS UPS system structure and modelsystem structure and model
Single-phase schemeSingle-phase schemevvoo++
--
LLCC iioo
VVdcdc
VVdcdc
iiLL
Averaged modelAveraged modeliioo
iiLL
LLCC
vvoo
++
--
vvmm++
August 2001 Lesson 2 5
The control equation assumes that:The control equation assumes that:
)]k(v)k(v[LT)k(i)1k(i o
sLL
−−−−⋅⋅⋅⋅++++====++++ )]k(v)k(v[LT)k(i)1k(i o
sLL
−−−−⋅⋅⋅⋅++++====++++ + one sample delay+ one sample delay
The model works properlyin the UPS case if thesampling frequency ismuch higher (e.g. 15-20times) than the resonancefrequency of the output LCfilter.
The model works properlyin the UPS case if thesampling frequency ismuch higher (e.g. 15-20times) than the resonancefrequency of the output LCfilter.
Simple load modelSimple load model
+ one sample delay+ one sample delay
Current control loopCurrent controlCurrent control loop loop
++vOvvOO
LLL
August 2001 Lesson 2 6
iiLL(k)(k)
**
LL
Current control loopReview of deadbeat controlCurrent controlCurrent control loop loop
Review of deadbeat controlReview of deadbeat control
current referencecurrent reference
inverter currentinverter current
instantaneousinstantaneousinverter voltageinverter voltage
iiLLii
Dead-Beat Current Control Equation (DBCCE)Dead-Beat Current Control Equation (DBCCE)
vvkTkTkT (k+1)T(k+1)T(k+1)T (k+2)T(k+2)T(k+2)T
iii***LLL iiiLLL
vvv
TsTTss
[[[[ ]]]] )1k(v)k(v)k(v)k(i)k(iTL)1k(v oomL
*L
Sm ++++++++++++−−−−−−−−====++++ [[[[ ]]]] )1k(v)k(v)k(v)k(i)k(i
TL)1k(v oomL
*L
Sm ++++++++++++−−−−−−−−====++++
iiiLLL(k+2)(k+2)(k+2)
August 2001 Lesson 2 7
0 0.2 0.4 0.6 0.8 10
0.2
0.4
0.6
0.8
1
[ms]
Step response ofthe closed-loopcurrent control.Samplingfrequency: 15 kHz
Step response ofthe closed-loopcurrent control.Samplingfrequency: 15 kHz
Two sample delayTwo sample delayTwo sample delay
Current control loopCurrent controlCurrent control loop loop
August 2001 Lesson 2 8
Voltage control loopVoltage controlVoltage control loop loop
•• The The same same reasoning used for dead-beat currentreasoning used for dead-beat currentloop can be applied loop can be applied also to the voltage loop.also to the voltage loop.
•• A A key pointkey point is to make the is to make the sampling periodsampling period of ofthe the voltage controlvoltage control equal to equal to TWICETWICE the thesampling periodsampling period of the of the current loop.current loop.
•• Thus, Thus, the current closed loop the current closed loop control can becontrol can bemodeled as a modeled as a simple delaysimple delay (i.e. a two sampling (i.e. a two samplingperiod delay).period delay).
August 2001 Lesson 2 9
Voltage control loopVoltage controlVoltage control loop loop
)1k(i)k(i)k(i)]k(v)k(v[T2
C)1k(i ooLo*o
S
*L ++++−−−−−−−−−−−−−−−−⋅⋅⋅⋅
⋅⋅⋅⋅====++++ )1k(i)k(i)k(i)]k(v)k(v[
T2C)1k(i ooLo
*o
S
*L ++++−−−−−−−−−−−−−−−−⋅⋅⋅⋅
⋅⋅⋅⋅====++++
Dead-Beat Voltage Control Equation (DBVCE)Dead-Beat Voltage Control Equation (DBVCE)
)]k(i)k(i[CT2)k(v)1k(v oL
soo −−−−⋅⋅⋅⋅⋅⋅⋅⋅++++====++++
Simple load modelSimple load modelSimple load model iiooCCvvoo
++
--
ii LL
Load current sensingLoad current sensingLoad current sensing
The control equation assumes that:The control equation assumes that:
+ one sample delay+ one sample delay
August 2001 Lesson 2 10
Voltage control loopVoltage controlVoltage control loop loop
0 0.2 0.4 0.6 0.8 10
0.2
0.4
0.6
0.8
1
[ms]
Step response ofthe closed-loopvoltage control.Samplingfrequency: 7.5 kHz
Step response ofthe closed-loopvoltage control.Samplingfrequency: 7.5 kHz
Two sample delayTwo sample delayTwo sample delay
August 2001 Lesson 2 11
Voltage control loopLoad current estimation
Voltage controlVoltage control loop loopLoad current estimationLoad current estimation
•• The load current The load current does not needdoes not need to be measured to be measured•• The following The following dead-beatdead-beat (system poles in the (system poles in the
origin) origin) estimationestimation is derived is derived (DBEE):(DBEE):
)1k(i)]1k(v)k(v[TC)1k(i~ Loo
So −−−−−−−−−−−−−−−−⋅⋅⋅⋅====−−−− )1k(i)]1k(v)k(v[
TC)1k(i~ Loo
So −−−−−−−−−−−−−−−−⋅⋅⋅⋅====−−−−
•• Estimation with Estimation with system poles away from thesystem poles away from theoriginorigin implies a implies a IIR low-pass filterIIR low-pass filter on the on theestimated current (*)estimated current (*)
•• Practically,Practically, a moving average a moving average (FIR) filter with 4(FIR) filter with 4taps was usedtaps was used
(*)(*)(*)
August 2001 Lesson 2 12
Voltage control loopControl refinements
Voltage controlVoltage control loop loopControl refinementsControl refinements
•• Feedforward of capacitor current referenceFeedforward of capacitor current reference(obtained from output voltage reference).(obtained from output voltage reference).
•• Feedforward of the estimated load current.Feedforward of the estimated load current.•• Interpolation between samplesInterpolation between samples
(reduction of oscillations on inverter voltage at half of the(reduction of oscillations on inverter voltage at half of thesampling frequency).sampling frequency).
•• Detuning of voltage controlDetuning of voltage control(voltage estimation at instant k+1 with system pole away(voltage estimation at instant k+1 with system pole awayfrom the origin from the origin (low-pass filtering action)(low-pass filtering action) - lower- lower sensitivitysensitivity totonoise).noise).
August 2001 Lesson 2 13
Voltage control loopControl refinements
Voltage controlVoltage control loop loopControl refinementsControl refinements
FeedforwardFeedforward of the estimated of the estimated load currentload current (DBEE) (DBEE)allows the allows the voltage dynamic equationvoltage dynamic equation to re-written: to re-written:
)]k(i)k(i[CT2)k(v)1k(v oL
soo −−−−⋅⋅⋅⋅⋅⋅⋅⋅++++====++++ )]k(i)k(i[
CT2)k(v)1k(v oL
soo −−−−⋅⋅⋅⋅⋅⋅⋅⋅++++====++++
)1h(iCT2)h(v)1h(v *
Cs
oo −−−−⋅⋅⋅⋅++++====++++ )1h(iCT2)h(v)1h(v *
Cs
oo −−−−⋅⋅⋅⋅++++====++++
h is the index for 2Tswsampling periodh is the index for 2Tswsampling period
August 2001 Lesson 2 14
Voltage control loopControl refinements
Voltage controlVoltage control loop loopControl refinementsControl refinements
FeedforwardFeedforward of also the capacitive current allows of also the capacitive current allowsDBVCEDBVCE to be re-written: to be re-written:
)1h(i)]h(v)h(v[T2
C)h(i *Co
*o
s
*C −−−−∆∆∆∆−−−−−−−−⋅⋅⋅⋅
⋅⋅⋅⋅====∆∆∆∆ )1h(i)]h(v)h(v[
T2C)h(i *
Co*o
s
*C −−−−∆∆∆∆−−−−−−−−⋅⋅⋅⋅
⋅⋅⋅⋅====∆∆∆∆
Where Where ∆∆∆∆∆∆∆∆iicc** stands for the stands for the deviation deviation of the of the iicc**
current from its current from its feed-forwarded value.feed-forwarded value.
August 2001 Lesson 2 15
��������
������������
���� −−−−−−−−−−−−⋅⋅⋅⋅++++====++++ )2h(i21)1h(i
25
CT)h(v)1h(v *
C*C
soo ��������
������������
���� −−−−−−−−−−−−⋅⋅⋅⋅++++====++++ )2h(i21)1h(i
25
CT)h(v)1h(v *
C*C
soo
Voltage control loopControl refinements
Voltage controlVoltage control loop loopControl refinementsControl refinements
Linear interpolationLinear interpolation can be used to can be used to re-constructre-constructthe the ”missing” current sample.”missing” current sample. This modifies This modifiesagain the again the voltage dynamic equation:voltage dynamic equation:
and generates the followingand generates the following control equation: control equation:
)2h(i51)1h(i
54)]h(v)h(v[
TC
52)h(i *
C*Co
*o
S
*C −−−−∆∆∆∆++++−−−−∆∆∆∆−−−−−−−−⋅⋅⋅⋅====∆∆∆∆ )2h(i
51)1h(i
54)]h(v)h(v[
TC
52)h(i *
C*Co
*o
S
*C −−−−∆∆∆∆++++−−−−∆∆∆∆−−−−−−−−⋅⋅⋅⋅====∆∆∆∆
August 2001 Lesson 2 16
Voltage control loopControl timing
Voltage controlVoltage control loop loopControl timingControl timing
t = n ⋅⋅⋅⋅TSk-2 k-1 k k+1 k+2
t = m ⋅⋅⋅⋅TVh-1 h h+1TV
TS
i*C(h+1)
i*C(h)
i*C(h-1)
iC(h+1)
iC(h)
iC(h-1)
InterpolatedInterpolatedsamplesample
v*o(h)
v*o(h-1) vo(h+1)
vo(h)
vo(h-1)
Voltage controlVoltage control
vm(k+1) vm(k+2)vm(k)vm (k-1)vm(k-2)
Inverter voltageInverter voltage
Current controlCurrent control
August 2001 Lesson 2 17
Voltage control loopEffects of Interpolation
Voltage controlVoltage control loop loopEffects of InterpolationEffects of Interpolation
0 0.005 0.01 0.015 0.02
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
[s]
Average voltage generated by VSIAverage voltageAverage voltage generated by VSI generated by VSI
withoutinterpolation
withoutwithoutinterpolationinterpolation
August 2001 Lesson 2 180 0.005 0.01 0.015 0.02
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
[s]
withinterpolation
withwithinterpolationinterpolation
Voltage control loopEffects of Interpolation
Voltage controlVoltage control loop loopEffects of InterpolationEffects of Interpolation
Average voltage generated by VSIAverage voltageAverage voltage generated by VSI generated by VSI
August 2001 Lesson 2 19
0.01 0.015 0.02 0.025 0.03
-10
-5
0
5
10[A]
[s]
Voltage control loopLoad current estimation
Voltage controlVoltage control loop loopLoad current estimationLoad current estimation
Actual and estimated load currentActual and estimated Actual and estimated load currentload current
Zohapproximation
ZohZohapproximationapproximation
August 2001 Lesson 2 20
0.01 0.015 0.02 0.025 0.03
-10
-5
0
5
10[A]
[s]
Voltage control loopLoad current estimation
Voltage controlVoltage control loop loopLoad current estimationLoad current estimation
Actual and estimated load currentActual and estimated Actual and estimated load currentload current
Fohapproximation
FohFohapproximationapproximation
August 2001 Lesson 2 21
Voltage control loopDe-tuning
Voltage controlVoltage control loop loopDe-De-tuningtuning
To improve theTo improve the controller’s robustness controller’s robustness it isit ispossible topossible to de-tune de-tune the voltage loop. This impliesthe voltage loop. This impliesthethe allocation allocation of the controllerof the controller pole away pole away from thefrom theorigin origin of the complex plane.of the complex plane.
)1h(iCT2)h(v)1h(v *
Cs
oo −−−−∆∆∆∆⋅⋅⋅⋅++++∆∆∆∆====++++∆∆∆∆ )1h(iCT2)h(v)1h(v *
Cs
oo −−−−∆∆∆∆⋅⋅⋅⋅++++∆∆∆∆====++++∆∆∆∆
Voltage dynamic equation for the Voltage dynamic equation for the deviationsdeviations from fromthe ideal the ideal trajectory.trajectory.
August 2001 Lesson 2 22
)1h(vT2C)h(i o
S
*C ++++∆∆∆∆−−−−====∆∆∆∆ )1h(v
T2C)h(i o
S
*C ++++∆∆∆∆−−−−====∆∆∆∆
Voltage control loopDe-tuning
Voltage controlVoltage control loop loopDe-De-tuningtuning
The The control lawcontrol law which ensures a which ensures a dead-beat responsedead-beat responseis simply given by:is simply given by:
where where ∆∆∆∆∆∆∆∆vvoo represents the represents the estimatedestimated output voltage output voltagedeviation (due to deviation (due to calculation delaycalculation delay we can’t use the we can’t use theactual deviation).actual deviation).
^
August 2001 Lesson 2 23
(((( )))))h(v)h(vK)1h(iCT2)h(v)1h(v ooS
*C
soo ∆∆∆∆−−−−∆∆∆∆++++−−−−∆∆∆∆⋅⋅⋅⋅++++∆∆∆∆====++++∆∆∆∆ (((( )))))h(v)h(vK)1h(i
CT2)h(v)1h(v ooS
*C
soo ∆∆∆∆−−−−∆∆∆∆++++−−−−∆∆∆∆⋅⋅⋅⋅++++∆∆∆∆====++++∆∆∆∆
The The estimator estimator can have the classicalcan have the classical Luenberger Luenbergerstructure. Kstructure. Kss allows to select theallows to select the pole location. pole location.
Voltage control loopDe-tuning
Voltage controlVoltage control loop loopDe-De-tuningtuning
If the If the polepole is located in the is located in the originorigin (dead-beat (dead-beatestimator) we have the usual estimator) we have the usual DBVCE for theDBVCE for thedeviation.deviation. Otherwise we have a Otherwise we have a de-tunedde-tuned controller controllerwith a with a first order response.first order response.
August 2001 Lesson 2 24
Control block diagramControl block diagramControl block diagram
Output filter capacitor and load modelOutput filter capacitor and load modelOutput filter capacitor and load model
+- ZC(z)
iL
io
iC
vo
Zo(z)
August 2001 Lesson 2 25
Deadbeat current controlDeadbeat current controlDeadbeat current control
Control block diagramControl block diagramControl block diagram
iL*
Currentcontrol +
- ZC(z)iL
io
iC
vo
Zo(z)
August 2001 Lesson 2 26
Control block diagramControl block diagramControl block diagram
Feedforward of the estimated load currentFeedforwardFeedforward of the estimated load current of the estimated load current
iL*
Currentcontrol
Load currentestimator
+- ZC(z)
iL
io
iC
vo
Zo(z)
io++
August 2001 Lesson 2 27
Control block diagramControl block diagramControl block diagram
Feedforward of capacitor current referenceFeedforward of capacitor current referenceFeedforward of capacitor current reference
iL*
Currentcontrol
Load currentestimator
+- ZC(z)
iL
io
iC
vo
Zo(z)
io++vo
*
Feed-forward ofcapacitive current
+iC
August 2001 Lesson 2 28
Control block diagramControl block diagramControl block diagram
Deadbeat voltage controlDeadbeat voltage controlDeadbeat voltage control
iL*
Currentcontrol
Load currentestimator
+- ZC(z)
iL
io
iC
vo
Zo(z)
io++vo
*
Feed-forward ofcapacitive current
+iC
T = 2 T
+-
Voltagecontrol
∆∆∆∆iC*
August 2001 Lesson 2 29
Control block diagramControl block diagramControl block diagram
iL*
Currentcontrol
Load currentestimator
+- ZC(z)
iL
io
iC
vo
Zo(z)
io++vo
*
Feed-forward ofcapacitive current
+iC
T = 2 T
+-
Voltagecontrol
∆∆∆∆iC*Current reference
interpolation
Capacitor current reference interpolationCapacitor current reference interpolationCapacitor current reference interpolation
August 2001 Lesson 2 30
Control block diagramControl block diagramControl block diagram
iL*
Currentcontrol
Load currentestimator
+- ZC(z)
iL
io
iC
vo
Zo(z)
io++vo
*
Feed-forward ofcapacitive current
+iC
T = 2 T
+-
Voltagecontrol
∆∆∆∆iC*Current reference
interpolation
Final schemeFinal schemeFinal scheme
August 2001 Lesson 2 31
Control implementationControl implementationControl implementation
•• The control program is implemented by means ofThe control program is implemented by means ofa a floating point DSP:floating point DSP:
−− ADSP21062: 33 Mips, 30 ns instruction cycleADSP21062: 33 Mips, 30 ns instruction cycle
•• The power converter is controlled by a motionThe power converter is controlled by a motioncontrol oriented control oriented fixed point DSP:fixed point DSP:
−− ADMC401: 26 Mips, 38.5 ns instruction cycleADMC401: 26 Mips, 38.5 ns instruction cycle
•• The two units are interfaced by means of a The two units are interfaced by means of a dualdualport RAMport RAM (1kword). A suitable (1kword). A suitable communicationcommunicationprotocolprotocol is implemented. is implemented.
August 2001 Lesson 2 32
Control implementationControl implementationControl implementation
ADSP21062ADSP21062
16 bit16 bit
16 bit16 bit
ADMC401ADMC401
Dual Port Dual Port RAMRAM
PowerPowerConverterConverter
PWMSYNCPWMSYNC00
22
1616
33
[µµµµs][µµµµs]
44
A/DA/DconversionconversionEOCEOCRAM write RAM write EOWEOW
ControlControlprogramprogramδδδδδδδδ readyready
1717
RAM read RAM read
1818PWM write PWM write
WAITWAIT1919
A/DA/DPWMPWM
RAM writeRAM writeEOWEOWRAM read RAM read
Scheme andtiming of thecontrol system
Scheme andtiming of thecontrol system
August 2001 Lesson 2 33
Control implementationControl implementationControl implementation
•• The The control programcontrol program is written in is written in C language,C language, and andthe AD the AD C-compilerC-compiler for the ADSP 21062 is used. for the ADSP 21062 is used.
•• Given the very high performance of the DSP unit,Given the very high performance of the DSP unit,no no timing problemtiming problem is encountered, even for very is encountered, even for verycomplex algorithmscomplex algorithms and 20 kHz operating and 20 kHz operatingfrequency.frequency.
•• Data exchangeData exchange between the two units is dealt with between the two units is dealt withby means of simple by means of simple data memory writedata memory write (DM)(DM)instructions.instructions.
August 2001 Lesson 2 34
50% increase compared to PI control
50% increase 50% increase compared to PI controlcompared to PI control
0
12 [µµµµs]
A/Dconversion
t = kTS
k is evenyes
Eq. 11
no
Interpolation
DBEE
Feed-forward of Ci
DBCCE
∆∆∆∆ i*C(h)
vm(k+1)Dead time compensation
DC link feed-forward
Dead-beat voltage controlinterpolation
Dead-beat voltage controlDead-beat voltage controlinterpolationinterpolation
Load current estimationLoad current estimationLoad current estimationCapacitor current estimationCapacitor current estimationCapacitor current estimation
Dead-beat current controlDead-beat current controlDead-beat current control
Timing of the controlalgorithm
Timing of the controlTiming of the controlalgorithmalgorithm
August 2001 Lesson 2 35
Experimental resultsExperimental resultsExperimental results
ooNominal output powerNominal output power PP 11 [kVA][kVA]
Nominal output voltageNominal output voltage VVoRMSoRMS 115115 [V][V]
Minimum load DFMinimum load DF coscos φφφφφφφφ 0.80.8DC link voltageDC link voltage VVDCDC 250250 [V][V]
Output frequencyOutput frequency ff oo 5050 [Hz][Hz]Output inductorOutput inductor LL 1.81.8 [mH][mH]Output capacitorOutput capacitor CC 120120 [[µµµµµµµµF]F]Switching frequencySwitching frequency ffss 1515 [kHz][kHz]
Experimental prototype’s parametersExperimental prototype’s parametersExperimental prototype’s parameters
August 2001 Lesson 2 36
Experimental resultsExperimental resultsExperimental results
Step loadvariations100% - 0%
Step loadStep loadvariationsvariations100% - 0%100% - 0%
Output voltage[100V/div]
Output voltageOutput voltage[100V/div][100V/div]
Current reference[10A/div]
Current referenceCurrent reference[10A/div][10A/div]
Actual current[10A/div]
Actual currentActual current[10A/div][10A/div]
August 2001 Lesson 2 37
Experimental resultsExperimental resultsExperimental results
Output voltage[100V/div]
Output voltageOutput voltage[100V/div][100V/div]
Load current[10A/div]
Load currentLoad current[10A/div][10A/div]
Estimated current[10A/div]
Estimated currentEstimated current[10A/div][10A/div]
Reference voltage[200V/div]
Reference voltageReference voltage[200V/div][200V/div]
Step loadvariations100% - 0%
Step loadStep loadvariationsvariations100% - 0%100% - 0%
August 2001 Lesson 2 38
Experimental resultsExperimental resultsExperimental results
Output voltage[100V/div]
Output voltageOutput voltage[100V/div][100V/div]
Load current[10A/div]
Load currentLoad current[10A/div][10A/div]
Estimated current[10A/div]
Estimated currentEstimated current[10A/div][10A/div]
Reference voltage[200V/div]
Reference voltageReference voltage[200V/div][200V/div]
Distorting loadDistorting loadDistorting load
THD=3.4%THD=3.4%
August 2001 Lesson 2 39
Experimental resultsExperimental resultsExperimental results
Distorting loadDistorting loadDistorting load
THD=3.4%THD=3.4%
Output voltage[100V/div]
Output voltageOutput voltage[100V/div][100V/div]
Current reference[10A/div]
Current referenceCurrent reference[10A/div][10A/div]
Actual current[10A/div]
Actual currentActual current[10A/div][10A/div]
August 2001 Lesson 2 40
Experimental resultsExperimental resultsExperimental results
Distorting loadPI control
Distorting loadDistorting loadPI controlPI control
THD=6.0%THD=6.0%
Output voltage[100V/div]
Output voltageOutput voltage[100V/div][100V/div]
Current reference[10A/div]
Current referenceCurrent reference[10A/div][10A/div]
Actual current[10A/div]
Actual currentActual current[10A/div][10A/div]
August 2001 Lesson 2 41
ReferenceReferenceReference
S. Buso, S.Fasolo, P. Mattavelli, “Uninterruptible PowerSupply Multi-Loop Control Employing Digital PredictiveVoltage and Current Regulators”, Applied PowerElectronics Conference (APEC) Proc., Anaheim,California, 4-8 March, 2001, pp. 907-913.
S. Buso, S.Fasolo, P. Mattavelli, “Uninterruptible PowerSupply Multi-Loop Control Employing Digital PredictiveVoltage and Current Regulators”, Applied PowerElectronics Conference (APEC) Proc., Anaheim,California, 4-8 March, 2001, pp. 907-913.