ultra low power jan 15
DESCRIPTION
low power techniquesTRANSCRIPT
Ultra low power
Low power hand
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Ultra low power techniques
• Subthreshold operation• Encoding• Parallel processing• Balance computation and communication • Reduce the amount of information to be processed• Operate slowly and adiabatically• feed forward information reduction• Dynamic Voltage and Frequency Scaling (DVFS)• Dynamic Power Switching (DPS)
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Subthreshold operation
Advantages:• The gm/I ratio is maximum such that speed per watt or precision per watt is
maximized.• for a given VDD, the on–off current ratio is maximized in this regime.• enable VDD minimization• velocity saturation effects and thermal noise are nonexistent in the Subthreshold
regime and improve energy efficiency in the analog and digital domains.• resistive and inductive drops due to parasitic that can degrade gm are minimized
Disadvantages:• highly sensitive to transistor mismatch, power-supply noise, and temperature.• Linearization is more difficult
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ULP techniques…
• Encoding• Efficient encoding minimizes switching and leakage power
• Parallel processing• High speed, low power but area increased
• Balance computation and communication (data compression)• Less computation, more transmission• More compuatation, less transmission
• Reduce the amount of information to be processed• Using AGC circuits/ learning circuits to accumulate knowledge • Needs knowledge of algorithms, signal processing, architecture, circuit topology,
device physics
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ULP techniques…
• Operate slowly• Operate five times below fT
• Minimizes the voltage drop• Minimizes power dissipation
• Adiabatic switching• Reuse the signal energy• When voltage between drain and source exists, don’t on or off the transistor• The transistor must not be turned off when there is a significant current
flowing between its source and drain
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ULP techniques…
• feed forward information reduction• Clock gating• Wake up circuits
• Dynamic Voltage and Frequency Scaling (DVFS)• Dynamic Power Switching (DPS)
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REVERSIBLE LOGIC
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Gates
• Feynman gate• Toffoli gate• Fredkin gate• Double Feynman Gate (F2G) • Peres Gate • TSG gate • Sayem gate
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Feynman gate (controlled NOT gate)
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Toffoli gate (controlled-controlled NOT gate)
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Fredkin gate (Controlled swap gate)
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Double Feynman Gate (F2G)
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Peres Gate
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TSG gate
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Sayem gate
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REVERSIBLE BASIS
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REVERSIBLE SIMULATION OF CLASSICAL GATES
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Using Fredkin gate
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• Garbage bit• Non constant output line that is not part of the desired result
• Ancilla bit• Bit assured to be constant at both input and output
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References
• Universal Principles for Ultra Low Power and Energy Efficient Design by Rahul Sarpeshkar, Senior Member, IEEE, TCAS II Vol 59, no.4,April 2012• Design of Reversible logic circuits using standard cells-standard cells and
functional programming by Michael Kirkedal Thomsen, ISSN: 0107-8283• Introduction to Reversible Logic Gates & its Application by Sujatha.S.Chiwande,
NCICT 2011
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