ULTRA LOW POWER FULL ADDER IC DESIGN PROGRESS REPORT

Submitted to Dr. Baris Taskin and the ECE Senior Design Committee of Drexel University

Submitted in partial fulfillment of the requirements for Senior Design Project, ECE 492

Drexel University Ultra Low Power Full Adder Senior Design Team Revision: 1.0 Kevin Daly – Elec. & Comp. Engineering Tiffany Lakins – Elec. & Comp. Engineering Date: March 2, 2011 Ramen Tieu – Computer Engineering Team Number: ECE01 Website: ece.drexel.edu/ece01 Page: 0 of 19

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1 ABSTRACT One of the key issues in modern Integrated Circuit (IC) design is the considerable amount

of power being dissipated in the circuits. Although we are capable of placing hundreds of

millions of transistors on a single chip, their use is restricted due to these power limitations.

Hence, research and innovation in IC design must be done, so that we are not bound by the ever-

growing power concerns.

The objective of this project is to utilize low power circuit techniques on typical IC

components and subsystems. In particular, we propose to implement adiabatic logic into a CLA

Full Adder to obtain large power savings over the standard CMOS methods. We also want to

push the operating frequency of our design to frequencies larger than those shown for typical

adiabatic families. We plan to show this through industry standard IC simulator tools, as well as

power measurements from a PCB.

We first simulated inverters of several adiabatic logic families to choose which would be

best help meet our goals. Using these results, our team chose to progress with the Improved Pass

Gate Logic (IPGL) family. From here, we designed six different implementations of a CLA

Adder, with each having several more variations to be tested. Simulations showed that the IPGL

family, although good for a single gate, had poor signal integrity as the number of logic stages

increased. This limited our designs to an operating frequency around 150MHz. Looking into the

downfalls of the IPGL family, we propose a new adiabatic logic family, which pushed power

savings up to 500MHz, and operating frequency to over 1GHz. This slightly held the progress of

our project back, however, we have been able to nearly catch up as we are in the process of

completing the IC layouts and simulations on time. There is an issue with using the ADS

software to design the PCBs, because it does not support multiple layers, which is required for

our circuits. We have decided to move along by using PCAD, however, the completion of the

PCB designs have been delayed. The multiple layer boards add extra cost to our budget, due to

the fact that we need to go outside of Drexel to get the boards manufactured. Nevertheless, the

boards are still within budget. Design, test, and evaluation of the PCB boards are the remaining

work that must be done next term. We also need to look into combining our design with a rotary

clock.

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TABLE OF CONTENTS Ultra Low Power Full Adder IC Design ………………………………………………………….0

1 Abstract …………………………………………………………………………...………….i

List of Figures/ Tables ...................................................................................................................iii

2 Introduction .............................................................................................................................1

2.1 Problem Description .................................................................................................1

2.2 Proposed Work and Deliverables …………………………………………………..2

3 Progress Toward a Solution......................................................................................................3

3.1 Choose Adiabatic Logic Family ...............................................................................3

3.2 Test Different IPGL and CMOS Designs .................................................................4

3.3 Propose New Adiabatic Logic Family ......................................................................5

3.4 Results of Different Full Adder Designs ...................................................................7

3.5 Adiabatic and CMOS Layout Designs ....................................................................10

3.6 CMOS PCB Design ................................................................................................10

4 Budgets .................................................................................................................................10

5 Schedule/ Timeline ...............................................................................................................12

6 Social, Environmental, Ethical Impacts ................................................................................12

7 Summary/ Conclusions .........................................................................................................13

References .....................................................................................................................................13

Appendix .......................................................................................................................................14

Appendix A: 4-Bit CLA Adder Split Into 3 Sections..........................................................14

Appendix B: 2 Base Gate Level Designs.............................................................................15

Appendix C: 2-Input IPGL NAND Gate..............................................................................16

Appendix D: 2-Input IPGL NAND Gate of Proposed Logic Family...................................16

Appendix E: Proper Functionality of Proposed Adiabatic Logic Family at 1GHz...............17

Appendix F: Industrial Budget..............................................................................................18

Appendix G: Updated Remaining Timeline...........................................................................19

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LIST OF FIGURES/ TABLES Figure 1: Power Savings vs. Frequency for Several Adiabatic Logic Families ...……………….3

Figure 2: 4-Bit IPGL CLA Adder Output w/ Power Clock Stage Representation ........................5

Figure 3: 2-Input IPGL NAND Gate w/ Input and Output Signals Specified ................................6

Table 1: Maximum Operating Frequency of the 6 Baseline Designs .............................................7

Figure 4: Adiabatic Power Savings vs. CMOS Equivalent Circuits................................................8

Figure 5: Total Power Consumption of Base Designs for a Single Computation ..........................8

Table 2: Out of Pocket Budget Comparison .................................................................................11

Figure 6: Task Status in Comparison to Proposed Timeline ........................................................12

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2 INTRODUCTION

2.1 PROBLEM DESCRIPTION Moore’s Law states that the number of transistors placed on an integrated circuit (IC) will

double every eighteen to twenty-four months. While this “law” has held for nearly forty-five

years, the utilization of these transistors has begun to taper off within the last decade. Multiple

factors have played a part in this trend, but one of the key issues is the increasing power density

of these tightly packed IC chips. The power in these packages has been increasing so rapidly that

processors were projected to reach the levels of a nuclear reactor (Rabaey). Therefore, even

though it is possible to place nearly a billion transistors on a single chip, these capabilities are not

being utilized to their full advantage due to power limitations. Some consequences of large

power consumption are constant battery recharging in portable devices and the need for liquid

cooling mechanisms. Such side effects are not desirable for consumer products or applications.

Hence, low power techniques have been introduced and researched to help alleviate the problem.

The five levels of abstraction in integrated circuits are: system, module, gate, circuit, and

device. Thus analysis and solution methods for this problem are hierarchical. At the top there is

the system level; here, power density issues are addressed in cooling, insulation, and packaging

systems. Within the module level, power density is addressed through efficient code

programming and parallelism to avoid hot spots in the circuit. At the gate level, the issue is

addressed by the physical spacing between logic gates, routing with minimal length

interconnects, and level converters to shift high signals to lower VDD levels for more power

efficient signal transfer.

Depending on the application, a designer may not address power dissipation at the circuit

and device levels. Since many high-end designs are semi-custom, engineers purchase circuits, or

cell libraries, from vendors and arrange them into IC’s. Hence, in a sense, the engineers accept

whatever power density issues the packaged circuit comes with. However, the initial circuit

designers must account for the three major contributors to power loss during the design process,

which are dynamic (switching) power, short circuit power, and leakage power.

The most popular implementation of transistor level design is the Complementary Metal-

Oxide Semiconductor (CMOS) logic family configuration. When compared to other

implementations, CMOS is regarded as being extremely low power. However, it still incurs

large dynamic power loss during transient operations. Also, there is a brief period of time during

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an output transition, where a direct path from VDD to GND is created, which results in short

circuit power loss. Lastly, leakage power comes as a result of scaling CMOS technology and is

intrinsic to the transistor channel length. Hence, even though CMOS is implemented in nearly

99% of all IC designs, improvements need to be made to reduce the collective power

consumption of all the transistors on a single chip.

2.2 PROPOSED WORK AND DELIVERABLES To decrease power dissipation produced by CMOS technology in typical ICs, we propose

implementation of adiabatic logic. Adiabatic logic is a technique being explored that uses a

periodic clock signal in the circuit to charge and discharge the output capacitance of the logic

blocks. The key principle of adiabatic logic is using reversible logic to recycle the energy back

into the power clock rather than dissipate the energy as heat. In general, CMOS circuits charge a

load capacitance from the dc supply rail and then, when the output transitions to logic 0, that

energy discharges to ground and is dissipated. In most adiabatic designs, a dc power supply is

not used; but rather, a power clock allows the stored energy to flow back into it to be reused

later.

One shortcoming of adiabatic circuits is speed, with typical families operating between

150-500MHz. To lend itself to more applications, we would like our design to work at even

higher frequencies. This would also introduce the possibility of combining our combinational

logic blocks with a rotary clock system designed by Dr. Taskin’s research group. By combining

these two ultra low power techniques, we can hope to achieve up to 50-60% total power savings.

In most modern application specific integrated circuits, or ASICs, mathematical

computation is a key requirement of the hardware, and the most fundamental arithmetic unit is

the full adder. Therefore, the goal of our project is to design an ultra low power full adder unit.

Due to its popularity and common use in many high performance systems, we have decided to

implement the Carry Look-Ahead (CLA) Adder. To test the scalability of our proposed design,

we will implement a 4-bit, 8-bit, and 32-bit CLA arithmetic unit.

To determine the validity of our IC design, we will first create the standard CMOS and

adiabatic adder layouts at the transistor level. This will be done for the 4, 8, and 32-bit circuits.

From these layouts, we will perform industry standard HSPICE simulations to obtain dependable

simulated power results between the two techniques. These designs will be done at the 90nm

scale because this is the smallest technology that we have library models for. To obtain

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measurable results, our second task will be to implement both designs at the PCB level. This

will only be done only for the 4-bit circuit to prove actual power savings. Lastly, we will take

our adiabatic design, and see if it can be used in conjunction with the rotary clock. Hence, we

shall investigate the feasibility of running our adiabatic solution off a rotary clock, designed by

Dr. Taskin’s research group.

3 PROGRESS TOWARD A SOLUTION

3.1 CHOOSE ADIABATIC LOGIC FAMILY There are several different adiabatic logic families that have been presented in the past

ten years or so. We need to determine which family lends itself best to our application. As

mentioned, the primary goal is to obtain large power savings from the design. The other

objective is to push the operating frequency of the circuit as high as possible. Therefore, to

determine which logic family should be used, we measured power savings as a function of

frequency when compared to a standard CMOS gate. For this stage of testing, we chose to

evaluate the output from a simple buffer to gauge the capabilities of each adiabatic family. The

logic families tested were 2N2P, 2N-2N2P, PFAL, IPGL, and BOOST. The results from the

tests are shown below in Figure 1.

Figure 1. Power Savings Achieved Across Several Logic Families as Frequency is Increased

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Looking at Figure 1, we notice that three of the logic families either stop working or do

not achieve any power savings at frequencies higher than 550 MHz. Two families in particular,

BOOST and IPGL, have shown proper functionality into the GHz range. For our design, we

chose to continue progress with the IPGL logic family. This is because the IPGL family shows

proper functionality to the 2GHz range, where power savings can no longer be achieved.

BOOST, on the other hand, was not able to operate at frequencies larger than 1.3GHz. Because

we want our frequency to be as high as possible, we felt that IPGL would lend itself best to help

meet our goals.

3.2 TEST DIFFERENT IPGL AND CMOS FULL ADDER DESIGNS Once we knew that we were going to use IPGL in the full adder circuit, we needed to test

different implementations of the CLA Adder. A CLA Adder can be split up into three blocks,

generate and propagate, carry, and sum subsections. A schematic of a 4-bit CLA adder with

these different sections specified is shown in Appendix A. Our objective is to determine a

transistor level implementation of the adder, which will produce good power savings and high

operating frequencies. To do so, we developed six baseline designs, with each having several

variations that must be tested for optimization. Two of these base designs are shown in

Appendix B. To test the circuits, we needed to implement each of the circuit designs, in their

IPGL configuration, as well as their equivalent CMOS counterpart. From here, we could

determine which design obtains the overall lowest power, the most power savings, and the

highest operating frequency. The tests were performed on the 4-bit adder circuit of each design.

To keep the tests consistent, minimally sized transistors were used for all CMOS gates, and the

input tested was 1111+0000 with a CIN of 1. For the IPGL test, we alternate the input between

the previous and 0000+1111 with a CIN of 0 every cycle.

After completing and simulating the different designs, we noticed that although IPGL

works great for a single buffer, its frequency capabilities are limited as the number of logic

stages increases. Figure 2 shows the output for the best IPGL design at 100MHz. The reason for

why we can’t push frequency any further is because the outputs remain HIGH throughout nearly

60% of the next evaluation stage. Adiabatic logic works accordingly; during the first half of the

cycle, the circuit evaluates the output. Then during the second half, the power is recovered.

Figure 2 also includes a representation of these time periods with relation to the power clock. As

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you will notice from Figure 2, the outputs do not shut off in time for the next evaluation stage.

This could lead to improper functionality of later stages in a bigger system.

Figure 2. 4-Bit CLA Output at 100MHz, w/ Power Clock Stage Distribution

3.3 PROPOSE NEW ADIABATIC LOGIC FAMILY Through evaluation of the results, we realized that IPGL was not sufficient to meet our

goals. At 100MHz, the outputs obtained were no longer valid, and even if we were willing to

accept these waveforms, power savings was only obtained up to 150MHz. Therefore, we needed

to look into these issues to see if we could fix them.

By observing the waveforms inside the adder, we identified the cause of the problem.

Figure 3 shows the input and output signals of an IPGL, 2-input NAND gate. To better

understand the following explanation of the problem, please refer to the IPGL NAND gate

provided in Appendix C. The output of the gate is determined by three signals: Input A, Input B,

and Out_Bar. Inputs A and B provide a path to VDD according to the truth table of a 2-input

NAND gate. The Out_bar signal controls a PMOS transistor that is turned on whenever Out_Bar

is LOW. The problem is that at the beginning of every evaluation stage, the entire system has

just gone through recovery. This means that all signals in the system are following the Power

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Clock and should be Logic LOW, as shown in Figure 3. Hence, at this time, the Output is tied to

VDD because of the PMOS transistor, and the pull down network is shut off because it utilizes all

NMOS transistors. Due to the fact that there is no path to ground, the output is Vthp, as PMOS’

cannot pass a good “0”. Unfortunately, the offset of this voltage level increases with frequency.

Also, the pull down network doesn’t turn back on until the required inputs get above the NMOS

threshold voltage values. The nominal Vthn value for our 90nm technology is .397V. By the time

the inputs get above this value and pull the output to ground, a good portion of the next

evaluation stage has been completed. As more logic stages are added, these waveforms continue

to get worse.

Figure 3. 2-Input IPGL NAND Gate w/ Input and Output Signals Specified

To solve this problem, we introduce two additional NMOS transistors in the design.

During the brief period where the output is floating, we tie the node to ground. The modified

version of the 2-input NAND gate is shown in Appendix D. Appendix E shows the output of the

modified 4-bit CLA adder properly operating at 1GHz.

The disadvantage of our design is that we must introduce a new signal, which can turn

the NMOS transistors on at the desired time. We decided to use the inverse of the power clock

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as the control signal. Even though this is an undesirable effect, we can argue its insignificance,

as ultimately, we want to combine our design with a low power rotary clock. The rotary clock

can easily provide the inverse power clock without requiring the generation of a new signal.

3.4 RESULTS OF DIFFERENT FULL ADDER DESIGNS

After testing the validity of our new adiabatic logic family, we implemented it back into

the six baseline designs previously mentioned in Section 3.2. Our six different designs tested the

capabilities of custom vs. non-custom standard cell implementations. Designs 1 & 4 are

completely non-custom, while Designs 3 & 6 have fully customized blocks for each of the three

subsections shown in Appendix A. And lastly, Designs 2 & 5 use a mix of many basic blocks,

with a handful of fully custom gates. We learned that the more custom designs were better

suited to produce the lowest amount of power at higher frequencies. Table 1 shows the point of

failure for each of the six designs after they were optimized for power efficiency.

Design 1 Design 2 Design 3 Design 4 Design 5 Design 6 fmax, MHz 1006 1153 1108 1017 1161 1120

Table 1. Maximum Operating Frequency of the 6 Baseline Designs

When we say that our designs were optimized for power efficiency, we are referring to

the additional inverse power clock signal being sent throughout the circuit. This signal is a sine

wave, and from a sine wave we can create any other type of waveform. Therefore, we have

observed that we can control the tradeoff between power and signal integrity. With better signal

integrity, we can push the operating frequency of the adder as high as possible. However, this

comes with an increase in power consumption. By reducing the pulse width of the additional

control signal to the appropriate time period, we can eliminate any additional power dissipation

that our topology introduces. The results shown in Table 1 have been made, assuming that any

undesired noise is less than the Vthn value of .397V for the NMOS transistors, and that we are

willing to accept a 25% decrease in full voltage swing of the output. To trigger the next stage,

our output only needs to be approximately .4V. So by assuming that we can tolerate an output

level no lower than .9V is a valid assumption.

Looking at the values in Table 1, we see that all the designs can operate into the GHz

regime. Therefore, they can all be applicable for our final design. To further decide which

topology would be best to use, we looked at the overall power consumption of each design and

the corresponding power savings obtained when compared to the minimally sized equivalent

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CMOS models. Figure 4 shows the power savings obtained when comparing these values to

those from the CMOS configurations, and Figure 5 shows the total power dissipation of the six

designs for a single computation of the 4-bit adder.

Figure 4. Adiabatic Power Savings vs. CMOS Equivalent Circuits

Figure 5. Total Power Consumption of Base Designs for a Single Computation

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In this project, we want to be able to say that we have achieved so much power savings

when compared to CMOS methods. The most accurate way of doing this is to compare our

implementation with its equivalent CMOS circuit. Looking at Figure 4, we notice that Designs 1

and 4, the completely non-custom designs, achieve the most power savings throughout the

largest range of frequencies. However, if we observe the results shown in Figure 5, we notice

that Designs 1 & 4 burn substantially more power than the other four topologies. So even though

they have the best power savings when compared against their own CMOS equivalent, these

designs are not the most efficient for low power applications. Looking once again at Figure 5,

we notice that Design 6 consumes the least amount of power across all the proposed designs. If

we take another look at Figure 4, we notice that even though Design 6 does not obtain savings as

high as 700MHz, it is still a substantially better option other than Designs 1 & 4. Lastly, if we

move back to the frequency values in Table 1, we see that Designs 2 & 5 are best for pushing the

operating frequency, while Designs 1 & 4 are the worst. However, Designs 2 & 5 cannot push

their frequency while also maintaining power savings. Design 6 gives us the overall lowest

power, as well as a means to push the operating frequency as far as possible while obtaining

power savings against the CMOS equivalent. The gate level schematic of this design is shown as

the second picture in Appendix B.

So we have just indicated that we can expect to achieve power savings up to 500MHz

with the chosen Design 6. It is important to note that this comparison was done with minimally

sized transistors. In adiabatic logic this will not change as the size of the transistors do not have

a huge affect on the performance of the system. However, in CMOS technology, and in

particular, on the full adders in the architecture, these transistors are usually sized to make the

computation as fast as possible. As soon as any sizing is performed on the CMOS

implementation, the power numbers will dramatically increase. This leads us to believe that in a

real world application, we could expect to achieve power savings even in the GHz frequency

range, which is one of the reasons why we are concerned with pushing the frequency limits of

adiabatic logic. However, for this project, we want to prove that we designed a circuit that

produces large power savings when compared to its equivalent CMOS design. Therefore, proper

sizing on the final layouts of the CMOS circuits will not be done. This is so that we will have a

direct comparison between our proposed design and the standard CMOS implementations.

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3.5 ADIABATIC AND CMOS LAYOUT DESIGNS Now that we have decided to move along with Design 6, we need to create the IC layouts

to obtain accurate simulation results. The IC layouts are the closest thing to measuring a real

chip, as they are the files used for fabrication. When completed we will have obtained truly

accurate measurements of the data presented above in Section 3.4, and will have completed two

of the total five deliverables.

As of right now we are nearly finished with all the layout designs for 4, 8, and 32-bit

implementations. We ran into a bit of trouble when first starting the layouts because the new

Cadence Virtuoso that is being used for the project is not directly comparable to the older

Cadence version that we have learned in class. Hence, this has delayed our progress. Even

though we do not have results to show within this report, we still expect to get the layouts done

on time and have results to present by the time of the presentation.

3.6 CMOS PCB DESIGN Based on the complexity of the transistor wiring, we realized that we needed at least a

two-layer board for our circuits. Hence, the ADS software could not be used as expected.

Instead, we decided to use the Cadence PCB Editor Tool available on the Drexel ECE

computers. This required some time to learn how the software worked. Once we had a grasp of

how to use the tool, we began the board. Due to the desire to get our IC layouts done on time, all

our resources have gone to completing that task, therefore stalling the PCB design process. Even

so, the CMOS PCB design is nearly halfway complete. A good amount of transistors have been

placed and some of the wires are routed. We still need to design a circuit that will measure the

power being consumed by the adder. Power will only be lost during the binary addition.

Therefore, we need to capture this current draw to quantify power consumption.

4 BUDGETS There have been a few changes made to our out of pocket budget. Due to the fact that

Drexel cannot manufacture our boards, we will have them done by EC-Tronics. We cannot get

quotes on the boards until the layouts are complete, but we expect it to be no more than $200.

The first board will be paid upfront by our design group, which is covered within our allowed

budget. Dr. Taskin’s Research Group will cover the remaining costs. Supplies and equipment

will be covered by Drexel University. The total projected expenses from here on out are

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$14,194, with only $200 being covered by our team. Table 2 shows a comparison of the

proposed out-of-pocket budget compared to our actual expenses as of this point in the project.

The Industrial Budget is shown in Appendix F. The only discrepancy in the Industrial

Budget is that now we plan to use Cadence PCB Editor, rather than the ADS software which was

shown in the budget within our proposal. Therefore, we do not need to include the ADS

Institutional Fee, while the PCB Editor Fee is already covered by our previous costs. Also, we

have not been able to strictly follow our proposed timeline, therefore the hours of work that must

be completed has been updated based on the new schedule. Lastly, this industrial budget will

most likely change again once we are able to get quotes and costs from EC-Tronics on the price

of the boards.

Expense Category Out-Of-Pocket Budget Expenses To Date Electrical Components 2 PCBs $400 * $0 Equipment Waveform Generator $795 ** $0 Multimeter $1,072 ** $0 Oscilloscope $2,900 ** $0 Power Supply $8,982 ** $0 Desktop Computer $700 ** $700 ** Software Cadence Virtuoso for IC Design $15,000 ** $15,000 ** Cadence PCB Editor for PCB Design $12,000 ** $12,000 ** Supplies Phone Charges $50 $25 Printing of reports $40 $20 ** Total Project Cost $41,939 $27,745 Cost Supplied by Drexel University (**) $41,449 $27,720 Cost Supplied by Dr. Taskin’s RG (*) $400 $0 Projected Expenses $90 $14,194

*Costs covered by Dr. Taskin’s Research Group **Costs covered by Drexel University ECE Department

Table 2. Out of Pocket Budget Comparison

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5 SCHEDULE/ PROPOSED TIMELINE Due to a few setbacks in the design, we are slightly behind schedule. We expect to

complete the IC layouts of the full adder within the next week, which would have us caught up in

that regard. As far as the PCBs are concerned we are extremely behind schedule because we

decided to wait until we determined the final design before implementing anything. Within the

next few weeks as we move into the Spring Term we plan on catching up and finishing the two

PCB designs. Figure 6 show a reduced image of the proposed timeline, which indicates the

status of the major tasks within our project. Appendix G shows a completely updated Gantt

Chart Timeline of the remaining work in the project. The only change made to the proposed

timeline is that completion, testing, and evaluation of the PCB boards have been pushed back.

Figure 6. Task Status in Comparison to Proposed Timeline

6 SOCIETAL, ENVIRONMENTAL, ETHICAL IMPACTS In the bigger scheme of things, these results may contribute to changes in pricing

strategies, marketing, and portability. Depending on the results of the project, the optimal

adiabatic circuit may be more or less expensive than its CMOS counterpart. If mass production

of these alternatives is implemented, the pricing of integrated circuits could change dramatically.

The pricing strategies of power companies may also change due to the results of this project.

Since the “switching” action in power electronics introduce harmonics into the power grid, a

reduction in the power requirements of such devices would be welcomed by the power industry

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(although the loss in revenue to this power consumption may not be as welcomed) – however

this reduction in quantity may also lead to the creation of stiff penalties for grid harmonic

injections because it may make it easier to detect these origins.

Marketing for integrated circuits and devices that contain them may also change as a

result of this project. Instead of speed being the main selling point for high performance devices,

the focus could indeed change to power savings. As we see today, the battery life of

rechargeable devices is becoming more and more important. Additionally, the growing concern

about going “green” will ensure that many manufactures will push heavily for power savings in

their product over their competitors.

Portability for devices that implement these circuits could increase substantially. Due to

the ultra low power implications, power electronics can be used in the most remote places in the

world. Medical equipment could reach people in poor rural areas in third world countries, which

would be a great social impact.

7 SUMMARY/ CONCLUSIONS To summarize our progress, based off initial tests, the IPGL adiabatic logic family

seemed to be best to use to help meet our goals. Based on more complex implementations of the

family, we determined that IPGL was not suitable for high frequency applications. These

designs failed at approximately 150MHz. Therefore, we proposed an improvement to the design,

which allowed our CLA Adder to operate into the GHz range, while maintaining power savings

up to 500MHz, based on schematic simulations. The layouts are expected to be done by the time

of our presentation, which will complete two of the final five deliverables. The PCBs are

slightly behind schedule, however we plan to make up for lost time within the next couple of

weeks as we switch into Spring Term. Overall, we seem to be on track to successully complete

this project while meeting all the desired goals.

8 REFERENCES

[1] M. Bystrom and B. Eisenstein, “Are We In Business Yet?” in Practical Engineering Design,

Taylors & Francis Group, Ed. Florida: CRC Press, 2005, pp. 79-95

[2] Rabaey, Jan M. Digital Integrated Circuits: A Design Perspective. Prentice Hall Electronics.

Ed. Charles Sogem. Pp. 354.

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APPENDIX A

4-Bit CLA Adder Split Into Three SubSections

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APPENDIX B 2 Baseline Gate Level Schematics

Design 6

Design 1

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APPENDIX C 2-Input IPGL NAND Gate

APPENDIX D 2-Input NAND Gate of Proposed Logic Family

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APPENDIX E Proper Functionality of Proposed Adiabatic Logic Family at 1GHz

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APPENDIX F Industrial Budget

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APPENDIX G Updated Remaining Timeline

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