ultimate design review g. bertolone, c. colledani, a. dorokhov, w. dulinski, g. dozière, a. himmi,...

Ultimate Design Review

G. Bertolone, C. Colledani, A. Dorokhov, W. Dulinski, G. Dozière, A. Himmi, Ch. Hu-Guo, F. Morel, H. Pham, I. Valin, J. Wang,

G. Claus, M. Gelin, M. Goffe, K. Jaaskelainen, M. Specht, M. WinterJ.Baudot

Design Review [email protected] 26/12/2010

iPHC

OUTLINE Introduction : Initial Physics hypothesis Specifications Hit modeling Architecture Control interface reset sequencer Read out operation : SDS, Mux, Memory

management Running mode: output format Simulation Testability : Ultimate vs Mimosa 26 Layout Conclusion :power consumption, performance


iPHC

Physics: initial hypothesis : considered number of hits 2,4 x 105 hits/s/cm2

CMOS sensor:

Matrix of pixels 928 x 960 ≈ 891k pixels, Short integration time = 185.6 µs Transmission of the useful hits

The useful information is the set of hits (discriminator result = 1)

Suppression of Zeroes

Matrix of

pixels 928 x 960

20.4

8 m

m

20.48 mm

Row0

Row 927

Column 0 Column 959

Ultimate initial hypothesis (STAR)


iPHC

Number of hits by image

Number of hits by row (probability)

Number of hits by group (probability)

540 5 (2,35 x 10-2) 3 (2,35 x 10-4)

540 7 (1.71 x 10-3) 4 (0.7 x 10-5)

540 9 (0.7 x 10-4) 6 (0.1 x 10-6)

Row division (15 groups x 64 columns)


Ultimate : 600 (500 + 100 for noisy pixels)


iPHC

Ultimate specifications

Design based on Mimosa26 architecture Reticle size (~ 3.8 cm²)

M26 1152 x 576 pixels Ultimate 960 x 928 pixels

Reduced power dissipation Vdd: 3V simulate on digital part Shorter integration time

Integration time = 185.6 µs

Higher hit density larger memories 3.5 times larger than Mimosa26 (600 2048 words)

Higher transmission bit rate: 80 160 Mb/s per line Enhanced testability


iPHC

state : 1rstpixel address( 10 bits) + coding (2 bits)

state 1

row M-1

row M+1

row M

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

1

0

0

0

0

0

0

0

0

0

0

row M-1

row M+1

row M

0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0row M

HIT

…...

…...

1 0

1 0

0

1

0

0

1 0

1 1

1

1

1

1

state coding

00

01

10

11

state state

state

0

state 2

0

Ultimate Hit modeling


iPHC

top view implementation digital core

Main Sequencer

SDS

MUX6x15 to9

Core_analog

Sequencer for Analog part

Test Structure

Memory management

RAM 2048 x32

Test Structure

JTAG controller

Disable discriminators

output sequence

Pixel & discriminators

read-out sequence

Matrix of Pixels

Mode selection for Suze input(analog, virtual matrix or test )

Boundaryscan

JTAG bus

Cfg registers

lin

e

Sy

nc

hro

te

st

Co

din

g

sta

tes

Sy

nc

hro

te

st

Co

din

g u

p

to 9

sta

tes

Sy

nc

hro

te

st

Cfg registers

Test Structure

RAM 2048 x32

Serial output transmission

Output mux

Cfg registers

Cfg registers

Cfg registers

Cfg registers

Cfg registers

Cfg registers

clocks

rstb

Others Inputs

Line address

Synchro Line

Synchro frame

others controls

Line Synchro. matrix

Line address

Synchro Line

Synchro frame

others controls

Synchro Line

Synchro Line

others controls

others controls

others controls

Synchro frame

SUZE

Rowl 0

row 927

Pixel 0…….. scanned line …pixel 959

analog discriminatorsSequence Test

Discriminators

OutputsPads


iPHC

SuZe part SuZe condition:

~ 600 hits/sensor/frame Assumptions for LowRes EPI:

Isolate hits 1 hit = 3x4 pixels

Noisy pixels: ~ 100 (10-4)

Read-out row by row

Zero suppression algorithm Find max. 6 strings per group

15 Groups of 64 columns Find max. 9 strings per row

String (or state): up to 4 contiguous pixel signals above threshold

Memories store hits 4 single access memories of 2048x16 bits

(connected by pair) Read/write ping-pong

Serial transmission Output freq. = 160 MHz or 80 MHz

Block diagram of the sensor read-out architecture

S0 S1 S15

N Hits N Hits

Co

lum

n -

0

Co

lum

n -

63

Co

lum

n -

0

Co

lum

n -

63

Co

lum

n -

63

Co

lum

n -

0

A/D A/D… A/D A/D A/D A/D

…

…

…

…

…

…

…

…

S0 S1 S14

Co

lum

n -

0

Co

lum

n -

63

Co

lum

n -

0

Co

lum

n -

63

Co

lum

n -

63

Co

lum

n -

0

A/D A/D… A/D A/D A/D A/D

…

…

…

…

…

…

…

…

(Max. 6 states)

Sparse Data Scan

Retaining at maximum 9 states per row (+addresses) among 15 banks

(Max. 6 states)

Sparse Data Scan

(Max. 6 states)

Sparse Data Scan

core of the zero suppression

SRAM 2048x16 SRAM 2048x16 SRAM 2048x16 SRAM 2048x16

Memory 1 Memory 2

Memory Management (Memory with max. 9 states storage and serial transmission)

Memory ControlFrame counter Serializer


iPHC

Frequency distribution Input:

Clk: 160 MHz (Input LVDS 160 MHz or using the internal PLL 10 MHz)

Inside chip: Pixels and discris: 5 MHz (200 ns 16 x 1/80 MHz) Digital : 80 MHz

Output: 2 LVDS data out: 160 MHz or 80 MHz (low rate) Markers (LVDS): 1 MkD (per frame) and 1 ClkD (160 MHz)

MkD and ClkD LVDS drivers may be disable by JTAG Only 1 MkD and 1 ClkD by ladder


iPHC

Test bench simulation

Design stimuli = S i (xi,yi….)

Design = S i Functionsi (xi,yi….)

Token:identifier Link for constraints file


iPHC

Test bench: Stimuli

Design stimuli = S i (xi,yi….)

Clock

Reset

Cfg. Text file reader

Clock

reset

Design synchronization

eor

Main sequencer fsm

SynchronisationFor stimuli & design

cfg

Design image

cfg

cfg

cfgS'(fi(xi,yi...)

Results from Design

Stimuli for design

eor

sync

status

S(fi(xi,yi...)

status

syncComparaison

Result Design ó design Image

OK?è true false

Stimuli Design

cfgstatus

sync Si(xi,yi...)

S(xa,ya...)

S(xb,yb...)

Pattern generated

by algoritm Fixed

pattern

cfg

cfg

Configuration registers

pattern configuration


iPHC

Testing functionality

10 MHz

8 PADs

Pixel Array

Analog readout

discriminators

SuZe

MUX

LVDS

SDS

Mux 15x6 to 9

Memory storage

160 MHz

Analog part

Digital part

1a

2a

3a

4a

1d

2dMain sequencer

(synchros…)

3d

Analog part1a) Analog pixel scan:

The matrix is divided in stripes of 8 columns swapped with the next block of 8 columns at right and so on until all the columns are analyzed. 8 output pads. Max. Freq. = 20 MHz

2a) Nominal speed: 8 pre-selected columns connected directly to the 8 output pads and read at 80 MHz

3a) An external signal synchronized with the matrix read-out allows activating a line pattern during one or several selected rows (1d)

4a)A test mode injects a test voltage to emulate pixels outputsA test mode reads one selected row register; pixels and discriminators are in working mode, tint = 185 µs, Read-out freq. = 10 MHz via 2 LVDS output pads The row automatic scanning mode of whole matrix is implementedAll voltages of the discriminators are adjustable.

Digital partA test mode receives 2 rows by JTAG to emulate a matrix of (2 JTAG rows) x 464 = 928 rows.

In SuZe, 2 functionalities are tested:

1d )the Sparse Data Scan (SDS) and,

2d) the Multiplexing Logic (Mux) giving up to 9 states.

3d) On pad, we can select 3 modes: working mode ( analog readout + suze)test mode : discriminators, SDS, Mux.Synchronizations signals coming from main sequencer moduleAll the shape and durations of the synchronizations signals are configurable.


iPHC

Data format The data format is the same as Mimosa26 but read-out frequency is doubled

Mode test «pixels+discris»: read 1 row register, data split to 2 outputs at 10 MHz

Main mode: data split to 2 outputs at 160 MHz with LSB first

For each line with hit : one Status/line followed by up to 9 States. The following data stream is generated:

Status/Line word: Address of line, Number of States ( 9 Max., overflow flag if > 9 )

States list – One state = consecutive pixels at 1 in the line:

Column address of the first pixel at 1, Number of pixels at 1

DO0

DO1

Normal Read-out frequency= 160 MHz

:

…………...

…………...

[15:0] in this diagram means 16 consecutive bits

0 < Datalength0

0 < Datalength1

Header 0[15:0]

Header 1[15:0]

Framecpt[15:0]

Framecpt[31:16]

Datalength0

Datalength1

StatusLine[15:0]

State1[15:0]

State2[15:0] Staten[15:0]

StatusLine[15:0]

Datalength0

Datalength1

Trailer 0[15:0]

Trailer 1[15:0]

0 < n < 9

numberof

hit pixels

Bit(0-

not usedThe address of the column

Bit(0-1) Bit (0-9)

0 1 2 …. 12 13 ... 15

State

Data ¢ Max=1850x16 bits/output

Total stream size per output:59200 bits=3700 W16

number of states

Bit(0-3)

The address of the line

Bit (0-9)

OVF

0 ... 3 2 … . 14 15

Status/ Line


iPHC

Power dissipation

Pixel pitch (µm)

Digital (mW)

20.7

(960 col.)140

Conditions:VDDA = 3.3 VVDDD = 3.3 V* LVDS driver: reduced differential signal at +/- 200 mVChip area: 4.6 cm2

Estimated power consumption: 144 mW


iPHC

Layout

1920

9,6

µm

19872 µm

Pixel Array: 928 rows x 960

columns

Pitch: 20.7 µm Active area: ~ 3.8 cm²

X = 19872 µm Y = 19209.6 µm

AMS 0.35 high-res process 400 Ω.cm p- EPI layer


iPHC

Sram2048x16_1 Sram2048x16_2 Sram2048x16_3 Sram2048x16_4Ult_seq

Ser

iali

zerBSR

791 µm

2188 µm

1127 µm

860 µm

226

1 µ

m

19872 µm

Memory management

Topgen_discdata Topgen_topdis_latchreg

306

µm

304

µm

298

µm SDS

MUX

Layout


iPHC

CONCLUSION•The digital core works synchronously at the main frequency 80 MHz except the final part serialiser.• It answers to the classical rules of design. Only one synchronous reset the design, this reset is generated by the appearance of external asynchronous reset or start signal.•The slow control is independent of the readout. The readout can be restart without the activation of slow control.•Each main stage is pipeline at each line improving the reliability and the independence of each stage.

•The memory storage operates at maximum 40 MHz on writing mode and 20 MHz on reading mode with single ram access.

• The tests done with the layout netlist schematic with worst constraints first then typical and best, from units to global simulation test are ok.

•Each simulation complies with the worst case at the nominal core frequency of 80 MHz. •We apply the same procedure and set-up for the simulation described and for the real test bench.

•The experience in the last chip Mimosa26 shows that some particular procedures are directly transposable from test to simulation.


iPHC

Matrix of Pixels1. Pitch : 20.7 µm

2. Number of columns : 960

3. Number of rows : 928

4. Area ( 960 x 928 x 20.7²) : 3.81cm²

5. Line time : 200 ns

6. Integration frame time : 185,6 µs

MHz80

116


Physics1. Nhits : 2.4x105hits/cm²/s

Results1. Hits/ frame/chip : 170 x 2.4(security factor)

2. Hits/row : 0.58

3. Nbr of series (up to 4 pixels) by row for 7: 1.71 °/00 Chip 9 : 0.07 °/00

4. Nbr of series by block for 3: 0.23 °/00 Chip 6 : < 0.0001 °/00

rows_of_numbertime_line


iPHC

Back up slide: Reset

Power reset (rstb)

Vdd

8μs

90% Vdd

internal_rst

1μs min

start

clocks


iPHC

Back up slide:

Lib1

Lib1Lib1

Core Digital

ULTIMATE 1

Hierarchical design structure

topult_manag1 topsuze

suze

Légende

Lib1: Ultimate top

topmux_mem1sds_15_64_buf

ult_manag1

Lib1

toppixrowmuxtopslowcontrol Topdis_latchregsTopgen_discdata topCtrlPixScan

LEVEL

0

1

2

3

Lib1 Lib1 Lib1 Lib1 Lib1

Lib1

Lib1 Lib1


iPHC

Back up slide:

x2

Legend

Lib1: Ultimate Behavioral Functional SynthesisLib8: Ultimate_seq Lib9: jtag_genLib10: Soc_SOCSLOWCONTROLV3

……..

…...…...

Lib10.n Lib9

Lib1

Lib1

Core Digital

ult_manag1

TOP_SLOWCONTROL

Pull_upPull_upPull_up

Pull_downPull_downPull_down

SLOWCONTROL

toppixrowmux TopCtrlPixScan

Lib1

logicpixrowmux

Lib8 Corelib

regsrow

pixrowmuxev pixrowmuxodx464 x464

muxpixlinepwr muxpixline

logic

Corelib

logic

Corelib

muxpixlinepwr muxpixline

logic

Corelib

logic

Corelib

Regrow928

Reg_row

regrowmatev_od

regrow_quartline

selgr1x16

regrow_halfline

Lib8

Lib8 Lib8

Lib8

Lib8Lib8

Lib8 Lib8Lib8Lib8

Lib1

topult_manag1

Lib1

topdis_latchregs

Lib1

topgen_discdata

LEVEL

0

1

2

3

4

5 jtagcore idcode modereg

x 2

Lib1 Lib1

Lib8

6

7 Regrow_sel Selgr_gen

selgr1x16

Selgr_gen_imp

Lib8 Lib8

8

regtreepix

Lib8

regtree en_regtree

logic

Corelib

logic

Corelib

muxrowpix

x15 Lib8Lib8Lib8

Lib8

Lib8

gen_discdata

fsm_data_discri Jtag_data_discri

roregx_ultimateroregx_ultimate GenNewBitsFsm_bank_ultimateFsm_bank_ultimate

Fsm_bank_ultimateBuf_fsm_data_discri

dis_latchregs

Lib8

roregx_ultimate

Lib8

regloadscan

pregld1

Lib8

Buf_2n Buf_15_64_sub

ULTIMATE 1



iPHC

Back up slide:

Lib1

ULTIMATE 1Hierarchical design structure

topsuze

suzeLib1

Lib1

LEVEL

0

1

2

3

4

5

6

7

8

Lib1

Core Digital

Legend

Lib1: Ultimate BehavioralLib2: Ultimatefct_suze FunctionalLib3: Ultimate_seq Synthesis

……..

…...…...

topmux_mem1

mux_mem1

Lib1

topult_manag_seq

ult_manag_seq

10

11

ult_seq

Lib3

ctrl_fsm

Lib3

seqgen_fsm

Lib3

RdoutMode fsm_rd_chip

fsm_rd_genstart_gen

Lib3

regs8

gen_ckdiv16fsm_cmd_ana gen_rd_sync

Lib3

fsm_adrgen

fsm_ctrlsuze

Fsm_regloadgensuze

regloadgen

fsm_ctrlpix

Fsm_regloadgenpixel

regloadgen

regloadgenx2

reg16

pregld1b

muxld

fsm_scan_data

cmd_seqgen cmd_adrgen sh_adrrow

Lib3

Lib3

Lib3

Lib1

Lib1

9

12 gen_mk_test

gen_daqmk

gen_syncclkmarker_gen gen_clkdiv8 gen_seq_load

pregld1b

Compteur_11

Compteur_11b

muxclksyncgen_seq_pix

daq_fsm

RoReg

suze_seq pix_seq

x6

RoRegx14

monitoring1 monitoring2

RoReg_10b RoReg_4b

Lib3

Lib3 Lib3 Lib3Lib3

rdout_fsm

fsm_ctrl_ult

seq_option mux_seq_opt

ro_mode2 ro_mode3 ro_mode4Muxtest_padout

Lib3

Lib3

Lib3


iPHC

Back up slide:

Lib1

ULTIMATE 1Hierarchical design structure

topsuze

suze

Lib1

Lib1

LEVEL

0

1

2

3

4

5

6

7

8

Lib1

Core Digital

sds_15_64_buf

Lib2

Lib2

top_sdstop_sdstop_sds

x15 Lib2

sds

buf_15_64

fsm_sds fsm_nstates

fsm_sel_hitenc_pix sel_ad_code_pix

nstates_ctrl

top_nstates_ctrl

groupemod

Legend

Lib1: Ultimate BehavioralLib2: Ultimatefct_suze Functional Synthesis

……..

…...…...

coder

Fsm_coder

Inter_bank

Process_bit

nandcellpix

norcellpix

or_tree

Selct_adrpix

ffdgen

Sel_hit_reg

Compteur_3

Lib2 Lib2

Lib2 Lib2

Lib2

Lib2

mux_6x8to9

Lib2

Lib1

topmux_mem1

mux_mem1

Lib1

topmux_6x15to9

mux_6x15to9 test_suze

inverting_flipflopmux_token_8stmux_st6x8fsm_mux

regloadscan_mux

pregld1

mux_9x2to9mux_6x8to9 x2

Lib2

Lib2


iPHC

Back up slide:

Lib2

Lib2

Lib2

Lib2

sram2048x16sram2048x16sram2048x16

framecounter AND

testinitfifo muxframe

mxdfifointestbusxor

muxevenodd serializer muxpadserial

addnextline enwriting_oddeven addwriting cswriting nword_to_read

Lib2

Lib1

ULTIMATE 1


topsuze

suze

Lib1

Lib1

LEVEL

0

1

2

3

4

5

6

7

8

Lib1

Core Digital

Legend

Lib1: Ultimate BehavioralLib2: Ultimatefct_suze Functional Synthesis

……..

…...…...topmux_mem1

mux_mem1

Lib1

topult_manag_seq

ult_manag_seq

topmemory_2048

memory_management_buf

memory_writing

mem_4x2048x16b

x4

9 memory_management Buf_fifosram2048x16

10 latchevenoddstatesnb selmemel

x4

11

topbsr_ult

bsr_ult

bsriox11

bsriobsrio


iPHC

Back up slide:


iPHC

Back up slide: SDS architecture

[ 63 : 0 ]64 col. B 0

State 0

Bloc 0

[ 2 : 0 ]First 3 col. B 1

State 5

Status B0

[ 1,1, 1 ]

Overlapping(B0-B1)[ 2 : 0 ]

Control signals

[ 63 : 0 ]Bloc 1

[ 2 : 0 ]

Status B1

[ 2 : 0 ]

[ 2 : 0 ]

Control signals

Bloc 2

Status B2

Control signals

[ 2 : 0 ]

[ 63 : 0 ]

[ 2 : 0 ]

[ 2 : 0 ]

[ 2 : 0 ]

[ 7 : 0 ]

[ 7 : 0 ]

[ 7 : 0 ]

[ 7 : 0 ]

[ 7 : 0 ]

[ 7 : 0 ]

[ 63 : 0 ] Bloc i

[ 2 : 0 ]Status

[ 2 : 0 ]

[ 2 : 0 ]

Bloc 14

Status

Not connected[ 0,0, 0 ]

[ 63 : 0 ]

[ 2 : 0 ]

[ 2 : 0 ]

[ 2 : 0 ]

[ 7 : 0 ]

[ 7 : 0 ]

[ 7 : 0 ]

[ 7 : 0 ]

64 col. B 1

First 3 col. B 2

64 col. B 2

First 3 col. B 3

6 States B 0

State 0

State 5

6 States B 1

State 0

State 5

6 States B 2

State 0

State 5

6 States B i

State 0

State 5

6 States B 14

Control signals

64 col. B i

First 3 col. B i

Control signals

64 col. B i

State 0

State 5

Status B0

6 States B 0

State 0

State 5

6 States B 1

State 0

State 5

6 States B 2

TestSDS

Status B1

Status B2

Test control signals

PLA test output

Overlapping(B1-B2)

Overlapping(B2-B3)

Overlapping(Bi-1-Bi)

Overlapping(Bi-Bi+1)

Overlapping(B16-B17)

SuzeMultiplexer


iPHC

Back up slide: SDS

State1 State2 State3

0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0C0 C63

Rd[63:0]0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0

……

……

……

latch

ckrdpix

rstpix

ckmemlatch

State selection

Coding

Col. address

64 Discriminators at bottom of bank

(Read row by row )

Coding(Data compression)

C0 C1 C63

Bank Results

E0 E1 E63

Rd0 Rd1 Rd63

State: Data 8 bits

Column Address decoder(64 to 6)

Selection of column address of first hit pixel in group (Sparse Data Scan

algorithm)

Storing of N states by bank and generating status register

Discriminators Row

1er Inst

…

2 Inst3 Inst

6 Inst

This is the sequence used to decode column address of first hit pixel in group, it’s corresponding to read enable bit which is set to ‘1’. The number of instruction is limited at 6Each state is composed of 6 bits Column address plus 2 bits code

HIT0

8b

OvfSTATUS[2:0]

HIT5

8b ADR

Sm

4b

….

8b

STATUS[2:0]

8b A5b

….

Ban

k A

dr.

Sta

te 0

Sta

te 5

Maximum 6 States registers of 8 bits Bank address register of 5 bits Status register of 3 bits (number of states by bank)


iPHC

Back up slide: sds block coding

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 260 1 2 0 1 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0 1 0 1 2 3 4 5

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 530 1 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0 1 2

coding Column address Overlappingcoding Column address coding Column address

Status block

State 0 State 1 State 2

coding Column address coding Column address coding Column address

State 3 State 4 State 5 new_bit210j


iPHC

Back up slide: Mux top view

MULTIPLEXER

MU

X 9

x 2

è

9

1 status, 9 states

1 status, 9 states

1 status, 9 states

MU

X 6

x 8

è9

MU

X 6

x 7

è9Mux control

signals

Bloc 0( 1 status, 6 states)


From PLA



From PLA

A

B


iPHC

Back up slide: Mux

ckrdpix

rstline

0

Enable_mux

1rst hit state

2nd hit state

3rd hit state

4th hit state

5th hit state

6th hit state

7th hit state

8th hit state

9th hit state

token 1 current

token 2next 1

token 3next 2

Nb states/line = 8

0 9i Bank istatesNb_


iPHC

Back up slide: Memory mangement

Address +Control

MemoryWriting

MemoryReading

2048 words x 16 bits

RAM2 low


RAM2 high

32 bits

selmempimp

Od

d/e

ve

n s

ele

cti

on

Latch

InitializationSequence

Fra

me

OR

RA

NK

sw

ap

p (

2 / 2

)

Fra

me

OR

RA

NK

sw

ap

p (

1 / 2

)


RAM1 low


RAM1 high

RANK 0

RANK 1

frametoggle

Address + Data In + Controls

Data OUT

ReadingData

Odd

Even

Low

High

Address + Data + Controls

frametoggle

frametoggle

1 status, 9 states

MultiplexerTest

Test control signals

Mux test output

1 status, 9 states

From MUX


iPHC

Back up slide: memory coding

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F0 1 2 3 0 1 2 3 4 5 6 7 8 9 10 15 0 1 0 1 2 3 4 5 6 7 8 9 10

OVF

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F0 1 0 1 2 3 4 5 6 7 8 9 10 0 1 0 1 2 3 4 5 6 7 8 9 10

64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F0 1 0 1 2 3 4 5 6 7 8 9 10 0 1 0 1 2 3 4 5 6 7 8 9 10

96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127

0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F0 1 0 1 2 3 4 5 6 7 8 9 10 0 1 0 1 2 3 4 5 6 7 8 9 10

128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159

0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F0 1 0 1 2 3 4 5 6 7 8 9 10 0 1 0 1 2 3 4 5 6 7 8 9 10

State 8 State 9

Coding Column Coding Column

State 6 State 7


State 4 State 5


State 2 State 3


State 0 State 1

Number Row Coding Column


iPHC

Back up slide: Memory writing

RAM0 (0:15)

Mux output latched

cklatch

rstframe

ckrdpix

state0

state5

state4

state3

state1

state2

state9

state8

state7

state6

RAM1 (16:31)

Initialisation of the memory adr. counter n =0

n = 0 1 2 3 4

state0

state1 state3

state2

state5

state4

state9

state8

state7

state6

state0

state1

state2

n = 5

Not written

6

state0

state1

state2

state0

state1

state2

memory Adr. counter

n = 6 7

state0

state1

state2

state3

Not written

8

state3state2

Reverse writing memory input words

Line 0

Line 1

Line 2

Line 927

9 st

ates

RAM0 (0:15)

RAM1 (16:31)

RAM0 (0:15)

RAM1 (16:31)


iPHC

Back up slide: Serializer

Mu

ltip

lexe

r

Delay16 times clock

dualchannel

clkrate

reading output

Headers, trailers format

frame number Mu

ltip

lexe

r

Test output

en_scan

Do0

Do1

PADS

clkout

syncout

From Mux test Output

From RAM

From Configuration Registers

From frame counter

Words written in frame è è è è è è è è

è è è è è è è è

From memory writing

startframe

Address reading

Clock divider

clk160MHz f÷8

f÷16

f÷16

f÷8

f÷16

cs

ad

clk160MHz


iPHC

Back up slide: output format (1/4)

0 < Data length0 18500 < Data length1 1850

Frequency CLKD = 160 MHz (clkrate = 1)Dualchannel = 1T

MKD

CLKD

0 3 91 2 4 865 7 10 1311 12 14 15

DO0

DO1

Header0

Header1

Framecpt

Framecpt

Data length0

Data length1

StatusLine

State1

State2 Staten

StatusLine

0 < n 9

A word = 16 successive bits

Trailer 1

Trailer 2

…………...

…………...

0

0

1 i

j

datalength0

datalength1

1

[15: 0]

[31:16]


iPHC


T

MKD

CLKD

0 3 91 2 4 865 7 10 1311 12 14 15Frequency CLKD = 160 MHz (clkrate = 1)

0 < n 9

Dualchannel = 0


DO0

DO1 Header2Header1 Framecpt FramecptData

length0Data

length1StatusLine State1 State2[15:0]

0 < n < 9

1 word = 16 successive bits

Trailer1 Trailer2…………...

0 j J = datalength0 + datalength11

[15:0] [31:16]


iPHC


T

MKD

CLKD

0 3 91 2 4 865 7 10 1311 12 14 15

DO0

DO1

Header0

Header1

Framecpt

Framecpt

Data length0

Data length1


Frequency CLKD = 80 MHz (clkrate = 0)

StatusLine

State1

State2 Staten

StatusLine

0 < n 9

A word = 16 successive bits

Trailer 1

Trailer 2

…………...

…………...

0

0

1 i

j

datalength0

datalength1

1

Dualchannel = 1

[15: 0]

[31:16]


iPHC


T

MKD

CLKD

0 3 91 2 4 865 7 10 1311 12 14 15

DO0

DO1 Header2Header1 Framecpt FramecptData

length0Data

length1


Frequency CLKD = 80 MHz (clkrate = 0)

StatusLine State1 State2[15:0]

0 < n 9

1 word = 16 successive bits

Trailer1 Trailer2…………...

0 j J = datalength0 + datalength11

Dualchannel = 0

[15:0] [31:16]


iPHC

Back up slide: pattern 2 rows

Row 0

Row 1

927

( Row 0 + Row 1 ) x times

Row

A/D A/D… A/D A/D A/D A/D… …A/D A/D… A/D A/D A/D A/D…… …(960 Discriminators)

LINEPAT0_REG<0:959>

LINEPAT1_REG<0:959>

LINEPAT0_REG<0:959>

LINEPAT1_REG<0:959>

0 1151


iPHC

Back up slide: discri test Discriminator test structure

Line bit 0

Line bit 511

Loadscan

Shift Register

En_tstdata

Clkscan

dataout1_disc

dataout0_disc

Clkscanout_disc

DFF Scansyncout_disc

Line bit 512

Line bit 959

Shift Register

Clkscan

En_Loadscan

En_Loadscan

ClkscanEn_Loadscan

DO0

DO1

PADS

CLKD

MKD


iPHC

Back up slide: sds testTest structure PLA

STATUS GROUP 2

STATUS GROUP 1

STATUS GROUP 0

BANK 0 STATES 0-5

BANK 1 STATES 0-5

BANK 2 STATES 0-5

000_0000

Loadscan

Shift Register

En_scan

Clkscan

DO0_disc

DO1_disc

Clkscanout

En_scanout

Entstdatadisc

DFFScansync_out

From discriminator

dataout1_test

dataout0_testDO0

DO1

PADS

CLKD

MKD


iPHC

Back up slide: mux testTest structure MUX

State 1 (16 bits)

State 2 (16 bits)

State 3 (16 bits)

State 4 (16 bits)

State 5 (16 bits)

State 6 (16 bits)

State 0 (16 bits)

Loadscan

Shift Register

En_scan

Clkscan

douts0_PLA

douts1_PLA dataout1_test

dataout0_test

Clkscanout

En_scanout

Test_aftermux

DFF Scansync_out

State 7 (16 bits)

State 8 (16 bits)

State 9 (16 bits)

DO0

DO1

PADS

From PLA

CLKD

MKD


iPHC

Back up slide:

Ult_seq

Ser

ializ

er

BSR

Sram2048x16_1 Sram2048x16_2 Sram2048x16_3 Sram2048x16_4

Memory management


iPHC

Back up slide: Cadence environmentStart

cds.lib

Call software environment Cadence Version: 5.7

Read libraries path used

icfb

Library manager

Ams3.70Indus

Compile with ncvlog

Elaboration with ncelab

Analog Design Environment

Simulation with simvision

RTL Compiler CORELIB library .lib

1

hdl.varCompile with ncvhdl

Work library .pak .log etc...

CADENCE environment

Input configuration registers text file

(nedit)

Behavioral schematic

Synthesis schematic

SOC encounter

Layout netlist schematic

2 3

Config file with hierarchy editor

Pattern configuration

Vhdl Source with nedit Verilog Source with nedit Schematic with virtuoso schematic

kit

Layout delay (sdf)

ultimate design review g. bertolone, c. colledani, a. dorokhov, w. dulinski, g. dozière, a. himmi,...

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