u_d counter report
TRANSCRIPT
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TITLE: 9 states up/down counter
NAME: Tong Sing Teik & Law Yew Chung
COURSE: DMJ2
Introduction:
Indigital logicandcomputing, a counter is a device which stores (and sometimes displays) the number of
times a particulareventorprocesshas occurred, often in relationship to aclock signal.
up/down counter is a combination of up counters and down counters that allows you to increase and
decrease values by an increment of 1.
A synchronous 4-bit up/down counter built from D- flip flops. Depending on the logic value on the
Up/Down input (U/D), the counter will increment or decrement its value on the falling edge of the clock
signal. The additional enable input enables (1) or disables (0) counting.
Objective:
1. Implement 9 states up down counter using MSI design concept.
2. Verify the design with waveform file generated from simulator.
Equipment & Program:
1. Paper and pen
2. Altera Quartus II 8.1 Web Edition
Procedure:
Truth table of D-Latch and D-FF was tabulated as below:
Table 1 Truth table of D-latch
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Table 2 Truth table of D-FF
State diagram of counter was drwan which contain 9 states.
Figure 1 State diagram of counter
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State Table was tabulated from state diagram and D-FF input column was mapped using excitation table as below:
Table 2 Excitation table of D-FF
Table 3 State table of counter
PS(Q) NS(Q+) D-FF input
U/D = 0 U/D = 1 U/D = 0 U/D = 1
W X Y Z W X Y Z W X Y Z DW+ DX
+ DY+ DZ
+ DW+ DX
+ DY+ DZ
+
0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0
0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 1
0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0
0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0
0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 1 1
0 1 1 1 0 0 0 1 0 1 1 1 0 0 0 1 1 0 1 1
1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0
Min-term list was obtained by collecting all 1s from column D+
for both U/D = 0 and 1:
DW+
= 0, 10, 12,14,16
DX+
= 1,2,3,4,17
DY+
= 1,2,5,6,13,14,15,16
DZ+
= 1,3,5,7,11,12,15,16
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1-bit decoded was design using primitive gates.
Figure 2 1-bit decoder
Cascading of 1-bit decoder as basic logic unit realized 2-bit decoder
Figure 3 Cascading of 1-bit decoders to 2-bit decoder
Cascading of 2-bit decoders to 4-bit decoder was done, resulting signal diagram is shown in Figure 4.
It was verified to be correctly implement logic of 4-bit decoder.
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Figure 5 Cascading of 2-bit decoders to 4-bit decoder
Figure 6 Signal diagram of 4-bit decoder
Cascading of Cascading of 4-bit decoders and 1-bit decoder to 5-bit decoder was done, resulting signal
diagram is shown in Figure 7.
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It was verified to be correctly implementing logic of 5-bit decoder.
Figure 7 Cascading of 4-bit decoders to 5-bit decoder
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Figure 8 Signal diagram of 5-bit decoder
D-latch and D-FF was build instead of using build in D-FF provided by Quatus II.
Figure 9 D-latch
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Figure 10 D-Flip-flop
Time diagram of D-latch and D-FF was obtained as below:
Finally all logic bloks are combined to realize 9 states up down counter.
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Figure 11 9 states up/down counter
Discussion:
Each D-FF has 2 states that are on and off. This means N number of D-FF has 2^N states. The
required counter needs to support up to 9 states. Since, 9 is fall between 2^4 and 2^3, so at least
4 D-FF is needed for counter to have 9 states.
1st step of realizing the design is prepare states diagram for required 9 states counter.
The corresponding state table was prepared. D-FF input was mapped by using excitation table of
D-FF.
Input of D-FF, D can be implemented using decoder, alternately using logic gates. The choice of
using decoder is due to simplicity. 5 to 32 decoder is need because 9 states counter has 1 input
(U/D) and 4 internal D-FF feedbacks. The decoder provides 32 min-terms, which can provide
sufficient min-term list for the designed counters D-FF input. These required min-term is
collected using or-gate.
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Require logic block such as decoder and D-FF was build using much simpler logic blocks. These
simple logic blocks was build using primitive logic gates which were then cascaded to large
logic block to provide more function. The rationale of using cascading is due to the productivity
and simplicity of design, because much more cost effective and higher performance logic can be
build using transistor level of design.
Conclusion:
Design using cascading of logic blocks is successful and its a way to produce required logic
with higher productivity than complete gate level design which requires much more wiring by
naturally. Decoder is an alternative for generating min-term list instead of logic gates resulted
from k-map. Decoder design simplified wiring and time required to perform k-map
minimization.