ucn 5801a

5800 AND 5801BiMOS IILATCHED DRIVERS

UCN5800A

BiMOS II LATCHED DRIVERS

UCN5800L

Always order by complete part number, e.g., UCN5801EP .

The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOSICs merge high-current, high-voltage outputs with CMOS logic. TheCMOS input section consists of 4 or 8 data (‘D’ type) latches withassociated common CLEAR, STROBE, and OUTPUT ENABLEcircuitry. The power outputs are bipolar npn Darlingtons. This mergedtechnology provides versatile, flexible interface. These BiMOS powerinterface ICs greatly benefit the simplification of computer or micropro-cessor I/O. The UCN5800A and UCN5800L each contain four latcheddrivers; the UCN5801A, UCN5801EP, and UCN5801LW contain eightlatched drivers.

The UCN5800A/L and UCN5801A/EP/LW supersede the originalBiMOS latched-input driver ICs (UCN4400A and UCN4801A). Thesesecond-generation devices are capable of much higher data inputrates and will typically operate at better than 5 MHz with a 5 V logicsupply. Circuit operation at 12 V affords substantial improvement overthe 5 MHz figure.

The CMOS inputs are compatible with standard CMOS and NMOScircuits. TTL circuits may mandate the addition of input pull-up resis-tors. The bipolar Darlington outputs are suitable for directly drivingmany peripheral/power loads: relays, lamps, solenoids, small dcmotors, etc.

All devices have open-collector outputs and integral diodes forinductive load transient suppression. The output transistors arecapable of sinking 500 mA and will withstand at least 50 V in the OFFstate. Because of limitations on package power dissipation, the simul-taneous operation of all drivers at maximum rated current can only beaccomplished by a reduction in duty cycle. Outputs may be paralleledfor higher load current capability.

The UCN5800A is furnished in a standard 14-pin DIP; theUCN5800L and UCN5801LW in surface-mountable SOICs; theUCN5801A in a 22-pin DIP with 0.400" (10.16 mm) row centers; theUCN5801EP in a 28-lead PLCC.

FEATURES

To 4.4 MHz Data Input Rate High-Voltage,

High-Current Outputs CMOS, NMOS,

TTL Compatible Inputs

Output Transient Protection Internal Pull-Down Resistors Low-Power CMOS Latches Automotive Capable

2

3

4

5

6

7 8

9

10

11

12

13

14

SUPPLY

GROUND

CLEAR

OUT 1

OUT2

OUT3

Dwg. PP-014A

OUT4

1

141

COMMON

OUTPUTENABLE

IN 1

STROBE

IN 2

IN 3

IN 4

VDD

LAT

CH

ES

Data S

heet26180.10B

ABSOLUTE MAXIMUM RATINGSat +25°C Free-Air Temperature

Output Voltage, VCE . . . . . . . . . . . . . . 50 VSupply Voltage, VDD . . . . . . . . . . . . . . 15 VInput Voltage Range,

VIN . . . . . . . . . . . -0.3 V to V DD + 0.3 VContinuous Collector Current,

lC . . . . . . . . . . . . . . . . . . . . . . 500 mAPackage Power Dissipation,

PD . . . . . . . . . . . . . . . . . . . . See GraphOperating Temperature Range,

TA . . . . . . . . . . . . . . . . -20°C to +85 °CStorage Temperature Range,

TS . . . . . . . . . . . . . . . -55°C to +150°C

Caution: CMOS devices have input staticprotection but are susceptible to damage whenexposed to extremely high static electricalcharges.

Note the UCN5800A (DIP) and the UCN5800L(SOIC) are electrically identical and share acommon terminal number assignment.

5800 AND5801


115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000

FUNCTIONAL BLOCK DIAGRAM

Copyright © 1985, 1997, Allegro MicroSystems, Inc.

50 75 100 125 150

2.5

0.5

0

AL

LO

WA

BL

E P

AC

KA

GE

PO

WE

R D

ISS

IPA

TIO

N IN

WA

TT

S

AMBIENT TEMPERATURE IN °C

2.0

1.5

1.0

25

Dwg. GP-023-1

22-PIN DIP, R = 50°C/WθJA

28-LEAD PLCC, R = 55°C/WθJA

14-PIN DIP, R = 60°C/WθJA

14-LEAD SOIC, R = 95°C/WθJA

24-LEAD SOIC, R = 68°C/WθJA

COMMON

GROUND

STROBE

OUTPUT ENABLE

IN N

COMMON MOS CONTROL TYPICAL MOS LATCH TYPICAL BIPOLAR DRIVE

OUTN

Dwg. FP-016-1

CLEAR

SUPPLY

VDD

TYPICAL INPUT CIRCUIT

Dwg. EP-010-4A

IN

VDD


ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).

LimitsCharacteristic Symbol Test Conditions Min. Typ. Max. Units

Output Leakage Current ICEX VCE = 50 V, TA = +25°C — — 50 µA

VCE = 50 V, TA = +70°C — — 100 µA

Collector-Emitter VCE(SAT) IC = 100 mA — 0.9 1.1 V

IC = 200 mA — 1.1 1.3 V

IC = 350 mA, VDD = 7.0 V — 1.3 1.6 V

Input Voltage VIN(0) — — 1.0 V

VIN(1) VDD = 12 V 10.5 — — V

VDD = 10 V 8.5 — — V

VDD = 5.0 V (See Note) 3.5 — — V

Input Resistance rIN VDD = 12 V 50 200 — kΩ

VDD = 10 V 50 300 — kΩ

VDD = 5.0 V 50 600 — kΩ

Supply Current IDD(ON) VDD = 12 V, Outputs Open — 1.0 2.0 mA

VDD = 10 V, Outputs Open — 0.9 1.7 mA

VDD = 5.0 V, Outputs Open — 0.7 1.0 mA

IDD(OFF) VDD = 12 V, Outputs Open, Inputs = 0 V — — 200 µA

VDD = 5.0 V, Outputs Open, Inputs = 0 V — 50 100 µA

Clamp Diode IR VR = 50 V, TA = +25°C — — 50 µA

VR = 50 V, TA = +70°C — — 100 µA

Clamp Diode Forward Voltage VF IF = 350 mA — 1.7 2.0 V

NOTE: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic “1”.

Saturation Voltage

Leakage Current

(Each Stage)

(Total)

1234

5

6

7

8

9

10

11

12 13 14 15 16 17 18

19

20

21

22

23

24

25

262728

GR

OU

ND

OU

TP

UT

EN

AB

LE

ST

RO

BE

K

ST

VD

D

OE

Dwg. PP-037

LAT

CH

ES

NCNC

NC

NC

NC

NC

SU

PP

LY

CLA

MP

DIO

DE

CO

MM

ON

CC

LEA

R

OUT1

IN8

OU

T8

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

IN1

IN2

IN3

IN4

IN5

IN6

IN7

UCN5801EP(additional pinout diagrams

are on next page)



TRUTH TABLE

OUTN

INN STROBE CLEAR ENABLE t-1 t

0 1 0 0 X OFF1 1 0 0 X ONX X 1 X X OFFX X X 1 X OFFX 0 0 0 ON ONX 0 0 0 OFF OFF

X = irrelevant.t-1 = previous output state.t = present output state.

OUTPUT

CLEAR

STROBE

OUTPUTENABLE

INN

OUTN

A C B C B

G

D E

F

A C B

G

E

TIMING CONDITIONS(Logic Levels are VDD and Ground)

A. Minimum Data Active Time Before Strobe Enabled(Data Set-Up Time) ..........................................................50 ns

B. Minimum Data Active Time After Strobe Disabled(Data Hold Time) .............................................................. 50 ns

C. Minimum Strobe Pulse Width ..................................................125 ns

D. Typical Time Between Strobe Activation andOutput On to Off Transition ............................................500 ns

E. Minimum Time Between Strobe Activation andOutput Off to On Transition ............................................500 ns

F. Minimum Clear Pulse Width ....................................................300 ns

G. Minimum Data Pulse Width .....................................................225 ns

Information present at an input is transferred to its latch when theSTROBE is high. A high CLEAR input will set all latches to the outputOFF condition regardless of the data or STROBE input levels. A highOUTPUT ENABLE will set all outputs to the OFF condition, regardlessof any other input conditions. When the OUTPUT ENABLE is low, theoutputs depend on the state of their respective latches.

Dwg. No. A-10,895A

UCN5801A

2 21

22

SUPPLY

CLEAR 1 OUTPUTENABLE

STROBE VDD

3

4

5

6

7 16

17

18

19

20 OUT 1

OUT2

OUT3

OUT4

IN 1

IN 2

IN 3

IN 4

7

8

9

10

11 12

13

14

15

GROUND

OUT 5

OUT6

OUT7

Dwg. PP-015

OUT8

COMMON

IN 5

IN 6

IN 7

IN 8

LAT

CH

ES

2 23

24

SUPPLY

CLEAR 1 OUTPUTENABLE

STROBE VDD

3

4

5

6

7

21

22 OUT1

OUT2

OUT 3

OUT 4

IN1

IN 2

IN 3

IN 4

7

8

9

10

11GROUND

OUT5

OUT6

OUT 7

Dwg. PP-015-1

OUT 8

COMMON

IN5

IN 6

IN 7

IN 8

LAT

CH

ES

NOCONNECTION

NOCONNECTIONNCNC12 13

18

19

20

14

15

16

17

UCN5801LW


TYPICAL APPLICATIONUNIPOLAR STEPPER-MOTOR DRIVE

Dwg. No. B-1537

1

2

3

4

5

6

7 8

9

10

11

12

13

14

OUT 2

OUT 3

OUT 4

OUT 1

+30 V

IN 1

IN 2

IN 3

IN 4

STROBE

CLEAR

OUTPUT ENABLE (ACTIVE LOW)

LAT

CH

ES

UCN-5800A

VDD VDD

+30 V

µρ

STROBE

IN 1

IN 2

IN 3

IN 4

OUT 1

OUT 2

OUT 3

OUT 4

Dwg. GP-060

STROBE

IN 1

IN 2

IN 3

IN 4

OUT 1

OUT 2

OUT 3

OUT 4

Dwg. GP-060-1

UNIPOLAR WAVE DRIVE UNIPOLAR 2-PHASE DRIVE



UCN5800ADimensions in Inches

(controlling dimensions)

Dimensions in Millimeters(for reference only)

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.2. Lead spacing tolerance is non-cumulative.3. Lead thickness is measured at seating plane or below.

0.0140.008

0.300BSC

Dwg. MA-001-14A in

0.430MAX

0.100BSC

14

1 7

0.2800.240

0.210MAX

0.0700.045

0.015MIN

0.0220.014

0.005MIN

0.1500.115

8

0.7750.735

0.3550.204

7.62BSC

Dwg. MA-001-14A mm

10.92MAX

14

1 7

7.116.10

5.33MAX

1.771.15

0.39MIN

0.5580.356

2.54BSC

0.13MIN

3.812.93

8

19.6818.67


NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.2. Lead spacing tolerance is non-cumulative.

0° TO 8°0.34440.3367

0.24400.2284

0.0500.016

Dwg. MA-007-14 in

0.050BSC

0.00980.0075

1 2 3

0.15740.1497

0.0200.013

0.06880.0532

0.0040 MIN.

14 8

8.758.55

6.205.80

1.270.40

0° TO 8°

Dwg. MA-007-14A mm

1.27BSC

0.250.19

1 2 3

4.003.80

0.510.33

1.751.35

0.10 MIN.

14 8

UCN5800LDimensions in Inches(for reference only)

Dimensions in Millimeters(controlling dimensions)



UCN5801ADimensions in Inches



NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.2. Lead spacing tolerance is non-cumulative.3. Lead thickness is measured at seating plane or below.

22

1 2 3 11

9.658.39

5.33MAX

0.0700.030 28.44

26.67

0.39MIN

0.5580.356

2.54BSC

0.13MIN

4.062.93

0.3810.204

10.16BSC

Dwg. MA-002-22 mm

12.70MAX

12

22

1 2 3 11

0.3800.330

0.210MAX

0.0700.030

0.015MIN

0.0220.014

0.100BSC

0.005MIN

0.1600.115

0.0150.008

0.400BSC

Dwg. MA-002-22 in

0.500MAX

12

1.1201.050


UCN5801EPDimensions in Inches




18 12

0.020MIN

0.050BSC

128

INDEX AREA

Dwg. MA-005-28A in

0.0260.032

0.0130.021

26

25

19 11

4

5

0.1650.180

0.4950.485

0.4560.450

0.4950.485

0.4560.450

0.2190.191

0.2190.191

0.51MIN

4.574.20

1.27BSC

12.5712.32

11.58211.430

128

INDEX AREA

Dwg. MA-005-28A mm

0.8120.661

0.3310.533

12.5712.32

26

25

19

18 12

11

4

5

11.5811.43

5.564.85

5.564.85



UCN5801LWDimensions in Inches(for reference only)

Dimensions in Millimeters(controlling dimensions)


0° TO 8°1 2 30.020

0.013

0.0040 MIN.

0.01250.0091

0.0500.016

Dwg. MA-008-24A in

0.050BSC

24 13

0.29920.2914

0.4190.394

0.61410.5985

0.09260.1043

0° TO 8°1

24

2 30.510.33

0.10 MIN.

0.320.23

1.270.40

Dwg. MA-008-24A mm

1.27BSC

13

7.607.40

10.6510.00

15.6015.20

2.652.35


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BiMOS II (Series 5800) & DABiC IV (Series 6800)INTELLIGENT POWER INTERFACE DRIVERS

SELECTION GUIDE

Function Output Ratings * Part Number †

SERIAL-INPUT LATCHED DRIVERS

8-Bit (saturated drivers) -120 mA 50 V‡ 5895

8-Bit 350 mA 50 V 5821

8-Bit 350 mA 80 V 5822

8-Bit 350 mA 50 V‡ 5841

8-Bit 350 mA 80 V‡ 5842

9-Bit 1.6 A 50 V 5829

10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10

12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811

20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812

32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818

32-Bit 100 mA 30 V 5833

32-Bit (saturated drivers) 100 mA 40 V 5832

PARALLEL-INPUT LATCHED DRIVERS

4-Bit 350 mA 50 V‡ 5800

8-Bit -25 mA 60 V 5815

8-Bit 350 mA 50 V‡ 5801

SPECIAL-PURPOSE FUNCTIONS

Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804

Addressable 28-Line Decoder/Driver 450 mA 30 V 6817

* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.Negative current is defined as coming out of (sourcing) the output.

† Complete part number includes additional characters to indicate operating temperature range and package style.

‡ Internal transient-suppression diodes included for inductive-load protection.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures fromthe detail specifications as may be required to permit improvements in the design of its products.

The information included herein is believed to be accurate and reliable. However, AllegroMicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents orother rights of third parties which may result from its use.

ucn 5801a

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