type item atmel lit. no. - microchip...

SMART

Atmel-11260A-ATARM-How-to-Simulate-I2S-Interface-With-USART-Port-On-SAM9G15-eMPU-ApplicationNote_17-Mar-15

Scope

This application note introduces an example on how to use the USART and TimerCounter in the Atmel® | SMART ARM®-based SAM9G15 embeddedmicroprocessor unit (eMPU) to simulate an interface with an Integrated Inter-ICSound (I2S) formatted audio codec.

This simulation can be used to provide an audio interface in addition to the I2Speripheral included in the SAM9G15 device.

References

Type Item Atmel Lit. No.

DatasheetSAM9G15 Datasheet 11052

Wolfson® WM8731 Datasheet –

Software Library SAM9G15 Software Package –

APPLICATION NOTE

How to Simulate I2S Interface With USART Port OnSAM9G15 eMPU

Atmel | SMART SAM9G15 Series

http://www.atmel.com/tools/SAM9G15SOFTWAREPACKAGE.aspx

1. I2S Introduction

I2S (also known as Inter-IC Sound, Integrated Inter-chip Sound, or IIS) is an electrical serial bus interface standardintroduced in 1986 and used for connecting digital audio devices together. It is used to communicate PCM audiodata between integrated circuits in an electronic device. The I2S bus separates clock and serial data signals,resulting in a lower jitter than the typical communication systems that recover the clock from the data stream.

The I2S transmitter and receiver have the same clock signal for data transmission. The transmitter can be amaster to generate the clock signal or be a slave to use the clock signal from the receiver which acts as a master,or either of the transmitter and the receiver can be salve and the other controller will act as a master to generatethe clock signal for both.

Figure 1-1 shows the different use-cases.

Figure 1-1. I2S System Configurations

The I2S bus consists of at least three lines:

Bit clock (also called continuous serial clock): SCK

Word select: WS (also called left right clock LRCLK)

Serial data (SD)

Figure 1-2 shows the typical I2S waveform.

Figure 1-2. I2S Interface Timing

In this application, SAM9G15 will act as a master to provide the two clocks: SCK and WS. During playback,SAM9G15 acts as a transmitter and when recording, SAM9G15 acts as a receiver. The codec works as a slave tobe clocked by SAM9G15.

How to Simulate I2S Interface With USART Port On SAM9G15 eMPU [APPLICATION NOTE]Atmel-11260A-ATARM-How-to-Simulate-I2S-Interface-With-USART-Port-On-SAM9G15-eMPU-ApplicationNote_17-Mar-15

1

2. Device Overview

2.1 SAM9G15 Overview

SAM9G15 is a high performance eMPU with an ARM926 core, running up to 400 MHz.

The SAM9G15 features a graphics LCD controller with 4-layer overlay and 2D acceleration (picture-in-picture,alpha-blending, scaling, rotation, color conversion), and a 10-bit ADC that supports 4/5-wire resistive touchscreenpanels. Multiple communication interfaces include a soft modem supporting exclusively the Conexant SmartDAAline driver, HS USB Host and Device and FS USB Host with dedicated onchip transceivers, two HSSDCard/SDIO/MMC interfaces, USARTs, SPIs, I2S and TWIs.

The 10-layer bus matrix coupled with multiple DMA channels ensures uninterrupted data transfers with minimalprocessor overhead.

The External Bus Interface incorporates controllers offering support for 4-bank and 8-bank DDR2/LPDDR,SDRAM/LPSDRAM, static memories, as well as specific circuitry for MLC/SLC NAND Flash with integrated ECCup to 24 bits.

2.2 Wolfson WM8731 Codec Overview

The Wolfson WM8731 is a low-power stereo codec with an integrated headphone driver. It supports samplefrequency from 8 kHz to 96 kHz (8/32/44.1/48/88.2/96 kHz) and various word length (16/20/24/32-bit). It also canbe programmed to support different types of Audio Data Interface such as I2S, Left-justified, Right-justified andDSP mode and it can work in Master or Slave clocking mode. The clock can be generated by the oscillatorconnected with the codec if it works in Master mode.

For detailed information of this codec, refer to the Wolfson WM8731 datasheet available on www.cirrus.com.

2How to Simulate I2S Interface With USART Port On SAM9G15 eMPU [APPLICATION NOTE]Atmel-11260A-ATARM-How-to-Simulate-I2S-Interface-With-USART-Port-On-SAM9G15-eMPU-ApplicationNote_17-Mar-15

http://www.cirrus.com

3. Implementation

3.1 Overall Introduction of Solution

In the application, we use two channels of Timer Counter 0 (TC0) to generate BCLK and LRC clock for the codec,and use USART2 to transmit or receive the PCM data to or from the codec. Figure 3-1 gives the overall diagram ofthe signal connection between SAM9G15 and WM8731.

Figure 3-1. TC USART Signal

3.2 Clock Generation

In this application, we select Left-justified mode for the data transfer and receiving. Figure 3-2 illustrates thewaveform of this mode.

Figure 3-2. Left-justified Waveform

As can be seen from the diagram, the DACDAT or ADCDAT (SD) is available as long as LRC (WS) level changes,and is sampled from the first rising edge of BCLK (SCK). The data is MSB first ordered.

The Timer Counter (TC) in SAM9G15 includes six identical 32-bit TC channels. Each channel can be configured toperform a wide range of functions including frequency measurement, event counting, interval measurement, pulsegeneration, delay timing and pulse width modulation. In this application, we select two TC channels (TIOA0 andTIOA1) to generate the waveform for BCLK and DACLRC/ADCLRC.

TIOA0 is selected to generate BCLK and TIOA1 is selected to generate LRC. Both channels are configured asWaveform mode to provide wave generation.

The TC’s clock source is optional. We select TIMER_CLOCK1 (MCK/2) as the clock source for TIOA0, and usethe TIOA0 output waveform as the clock source for TIOA1.

SAM9G15 WM8731

TCLK0

SCK2

TCLK1

BCLK

DACLRC/ADCLRC

DACDAT

TIOA0

MCK/2

TIOA1

TXD2

RXD2

CTS2 GNDADCDAT

USART2

TC0

TWD0TWCK0

SDIN

SCLKTWI0


3

Both TIOA0 and TIOA1 use the RA and RC register to set the compare value and every time when the TC counterreaches the RA or RC value, the TIOA output level will invert. When the TC counter reaches RC value, its valuewill be reset to zero, and then continue to increase and so on. With this mode, we can generate the desuredfrequency by setting the register value of RA and RC.

To ensure the accuracy of the data transfer, the code is programmed to set the initial status of TIOA0 and TIOA1output to high level.

Note: The first time the TC begins to output the waveform, the initial output level of TIOA is low level. Consequently, in the initialization part, the TC output will be enabled once to make sure that when restarted the TC output in the following time, its initial status is high level.

How to calculate the RA and RC register value of TIOA0 to generate BCLK with the required frequency:

Freq (tcsrc) = Frequency of clock source of the TC channel

Freq (bclk) = Frequency of the generated waveform

DutyCycle = The duty cycle percent of the positive level of the generated waveform

RC = Freq(tcsrc)/Freq(bclk)

In this application: Freq(tcsrc) = Board_MCK/2

RA = RC * DutyCycle/100

In this application, DutyCycle = 50, so RA = RC/2

How to calculate the RA and RC register value of TIOA1 to generate LRC with the required frequency:

From the waveform diagram, we can see the relationship between BCLK and LRC. Normally in one LRC cycle, the number of BCLK cycles is not less than two times of the number of sample length (bits per sample). For example, for the stereo PCM data with 16-bit sample length, every LRC cycle includes at least 32 (2*16) BCLK cycles. So if we take the TIOA0 as the clock source of TIOA1, then the RA register value is set to bit number per each sample, and RC register value is set to double of bit number per each sample.

RA = Sample length

RC = 2 * Sample length

3.3 Data Transfer

The Universal Synchronous Asynchronous Receiver Transceiver (USART) in SAM9G15 supports specificoperating modes, providing interfaces on SPI, RS485, LIN, ISO7816 and infrared transceivers. In this application,we select SPI mode of USART to transmit the PCM data to the codec and receive the PCM data from the codec.

To ensure the clock synchronization, the clock of the SPI transfer is connected to the output of TIOA0 (BCLK), sowe need to set the SPI in slave mode.

The maximum data length that can be transferred in SPI mode is 9 bits. Since the normal PCM data length is timesof 8 bits (16, 24, or 32 bits per each sample), we set the data length for SPI transfer to 8 bits.

The data transfer order of MSB first is compliant with the data order requirement of the codec.

We also need to set the SPI transfer mode to read the data in each rising edge of the clock.

Figure 3-3 illustrates the waveform generated for the USART SPI Slave mode.


Figure 3-3. USART SPI Slave Mode Waveform

3.4 DMA Configuration

The data transfer of the USART SPI mode can use DMA mode, which will save processor bandwidth andsignificantly improve the system efficiency. SAM9G15 DMA can use Single-buffer transfer and Multi-buffertransfer. In this application, we use the Multi-buffer DMA transfer method: Linked Lists (buffer chaining). Thebuffers are linked by the pointer like a chain. The previous buffer contains the descriptor pointer which points to thenext buffer’s location in the system memory. The LLI (Linked List Item) registers should be initialized before DMAtransfer.

Figure 3-4 gives the diagram overview of how to use DMA to transfer data.

Figure 3-4. DMA Audio Transfer

For detailed description of how LLI DMA works, please refer to section “DMA Controller (DMAC)” in the SAM9G15datasheet.

LLI 0

Transmit Register

Receive Register

DMAC

USART2

TX

RX

DACDAT

ADCDAT

LLI 1

LLI 2

LLI n

…...

Buffer in Memory

Sample n-1 MSB

… ...

Sample n-1 LSB

… ...

Sample 1 MSB

Sample 1 LSB

Sample 0 MSB

Sample 0 LSB

Low Address

High Address

Buffer in RAM

Sample n MSB

Sample n LSB


5

3.5 Communication with the Audio Codec

Before operating the codec (WM8731), we need to configure it to the right working mode. This device can beprogrammed with 3-wire or 2-wire interface to access all feature settings such as volume control, mutes, de-emphasis, data transfer mode, data format, sample rate, etc.

In this application, we use 2-wire (I2C) mode to communicate with WM8731 to control the audio interface, volumeadjustment, data format, sample frequency and other relative features for the audio playback and recording.

For a detailed description of the codec feature setting, refer to the Wolfson WM8731 datasheet.

3.6 Hardware Connection

This application is realized on the SAM9G15-EK. Hardware modifications need to be made by installing flyingleads before running this demo on the board.

The instructions to modify SAM9G15-EK are the following.

1. Disconnect the original connection of the following signals:

Remove R147 connected with PA7 (refer to Figure 3-7)



Remove RR17 connected with PB1 and PB2 (refer to Figure 3-8)

Remove R86, R87, R88, R89 connected with pin3, pin6 and pin7 of WM8731 (refer to Figure 3-6)

Disconnect PA26 with pin4 of WM8731 (refer to Figure 3-6)

Disconnect PA25 with pin5 of WM8731 (refer to Figure 3-6)

2. Connect the corresponding signals according to the following direction:

TC0 → TIOA0 (PA21) connects to USART2 → SCK (PB2) and BCLK (pin3) of WM8731

TC0 → TIOA1 (PA22) connects to DACLRC (pin5) and ADCLRC (pin7) of WM8731

USART2 → SCK (PB2) connects to TC0 → TIOA0 (PA21)

USART2 → TXD (PA7) connects to DACDAT (pin4) of WM8731

USART2 → RXD (PA8) connects to ADCDAT (pin6)

USART2 → CTS (PB1) connects to GND

Figure 3-5, Figure 3-6, Figure 3-7 and Figure 3-8 are the schematics with the signals that need to be modified.


Figure 3-5. SODIMM Schematics

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4 4

3 3

2 2

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LCDDAT19

LCDDAT21

LCDDAT22

LCDDISP

LCDPWM

LCDDAT1

LCDDAT3

LCDDAT5

LCDDAT6

LCDDAT8

LCDDAT10

LCDDAT13

LCDDAT15

LCDDAT16

LCDDAT18

LCDDAT20

LCDDAT23

LCDVSYNC

LCDHSYNC

LCDPCK

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10-J

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-10

J2 HD

2X20

-HH

J2 HD

2X20

-HH

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

R83

4.7k

R83

4.7k

JP2

JP2

1

2

3

KEY

CO

N1

1612

618-

4

KEY

CO

N1

1612

618-

4

GN

D10

52

RF

U3

33R

FU

131

RF

U25

59R

FU

2357

GN

D7

41

RF

U20

54

RF

U18

50R

FU

1749

RF

U15

47R

FU

1345

GN

D9

51

RF

U10

40R

FU

838

GN

D1

5V

CC

33

VC

C1

1V

CC

22

VC

C4

4

VB

AT

6

RF

U9

39

RF

U11

43R

FU

1244

RF

U14

46

RF

U16

48

GN

D8

42

RF

U19

53

RF

U21

55R

FU

2256

RF

U24

58

RF

U26

60

RF

U2

32

GN

D3

11

US

BC

_DP

7

US

BC

_DM

9

GN

D6

29

US

BB

_DP

15U

SB

B_D

M13

GN

D4

17

DIB

P19

DIB

N21

GN

D5

23

US

BA

_DM

25

US

BA

_DP

27

GN

D12

94

PD

0/N

AN

DO

E63

PD

2/A

21/N

AN

DA

LE65

PD

4/N

CS

367

PD

6/D

1669

PD

8/D

1871

GN

D11

74

PD

10/D

2075

PD

12/D

2277

PD

14/D

2479

PD

16/D

26/A

2381

PD

18/D

28/A

2583

PD

20/D

30/N

CS

485

PA

0/T

XD

0/S

PI1

_NP

CS

189

PA

2/R

TS

0/M

CI1

_DA

1/E

0_E

TX

091

PA

4/S

CK

0/M

CI1

_DA

3/E

0_E

TX

ER

93

PA

11/S

PI0

_MIS

O/M

CI1

_DA

095

PA

13/S

PI0

_SP

CK

/MC

I1_C

K97

PA

21/R

XD

2/S

PI1

_NP

CS

010

2

PA

23/T

IOA

2/S

PI1

_SP

CK

104

PA

31/T

WC

K0/

SP

I1_N

PC

S2/

E0_

ET

XE

N10

5

PA

16/M

CI0

_CD

A10

9

PA

18/M

CI0

_DA

111

1

PA

20/M

CI0

_DA

311

3

PA

5/T

XD

1/C

AN

TX

111

5

PA

10/D

TX

D/C

AN

TX

011

7

PA

25/T

CLK

1/T

F12

1

PA

27/T

IOB

0/R

D12

3

PA

29/T

IOB

2/R

F12

5

PC

0/LC

DD

AT

0/IS

I_D

0/T

WD

112

9

PC

2/LC

DD

AT

2/IS

I_D

2/T

IOA

313

1

PC

4/LC

DD

AT

4/IS

I_D

4/T

CLK

313

3

PC

7/LC

DD

AT

7/IS

I_D

7/T

CLK

413

7

PC

9/LC

DD

AT

9/IS

I_D

9/U

RX

D0

139

PC

11/L

CD

DA

T11

/ISI_

D11

/PW

M1

141

PC

12/L

CD

DA

T12

/ISI_

PC

K/T

IOA

514

3

PC

14/L

CD

DA

T14

/ISI_

HS

YN

C/T

CLK

514

5

PC

17/L

CD

DA

T17

/UR

XD

114

9

PC

19/L

CD

DA

T19

/E1_

TX

1/P

WM

115

1

PC

21/L

CD

DA

T21

/E1_

RX

1/P

WM

315

3

PC

22/L

CD

DA

T22

/TX

D3

155

PC

24/L

CD

DIS

P/R

TS

315

7

PC

26/L

CD

PW

M/S

CK

315

9

PC

29/L

CD

DE

N/E

1_T

XC

K/S

CK

116

3

PC

31/F

IQ/E

1_M

DIO

/PC

K1

165

PB

0/E

0_R

X0/

RT

S2

169

PB

2/E

0_R

XE

R/S

CK

217

1

PB

4/E

0_T

XC

K/T

WD

217

3

PB

6/E

0_M

DC

/AD

717

5

PB

8/E

0_T

XE

R/A

D9

177

PB

9/E

0_T

X0/

PC

K1/

AD

1017

9

PB

11/E

0_T

X2/

PW

M0/

AD

018

1

PB

13/E

0_R

X2/

PW

M2/

AD

218

3

PB

15/E

0_R

XC

K/A

D4

185

PB

17/E

0_C

OL/

AD

618

7

PB

18/IR

Q/A

DT

RG

189

PW

R_E

N30

JTA

GS

EL

8

WK

UP

10

SH

DN

12

BM

S14

nRS

T16

nTR

ST

18

TD

I20

TC

K22

TM

S24

TD

O26

RT

CK

28

RF

U4

34

PD

1/N

AN

DW

E64

PD

3/A

22/N

AN

DC

LE66

PD

5/N

WA

IT68

PD

7/D

1770

PD

9/D

1972

PD

11/D

2176

PD

13/D

2378

PD

15/D

25/A

2080

PD

17/D

27/A

2482

PD

19/D

29/N

CS

284

PD

21/D

31/N

CS

586

PA

1/R

XD

090

PA

3/C

TS

0/M

CI1

_DA

2/E

0_E

TX

192

PA

12/S

PI0

_MO

SI/M

CI1

_CD

A96

PA

14/S

PI0

_NP

CS

098

PA

7/T

XD

210

0

PA

8/T

IOA

0/S

PI1

_MIS

O10

1

PA

22/T

IOA

1/S

PI1

_MO

SI

103

PA

30/T

WD

0/S

PI1

_NP

CS

3/E

0_E

MD

C10

6

PA

15/M

CI0

_DA

010

8

PA

17/M

CI0

_CK

110

PA

19/M

CI0

_DA

211

2

PA

6/R

XD

1/C

AN

RX

111

6

PA

9/D

RX

D/C

AN

RX

011

8

PA

24/T

CLK

0/T

K12

0

PA

26/T

CLK

2/T

D12

2

PA

28/T

IOB

1/R

K12

4

PC

1/LC

DD

AT

1/IS

I_D

1/T

WC

K1

130

PC

3/LC

DD

AT

3/IS

I_D

3/T

IOB

313

2

PC

5/LC

DD

AT

5/IS

I_D

5/T

IOA

413

4

PC

6/LC

DD

AT

6/IS

I_D

6/T

IOB

413

6

PC

8/LC

DD

AT

8/IS

I_D

8/U

TX

D0

138

PC

10/L

CD

DA

T10

/ISI_

D10

/PW

M0

140

PC

13/L

CD

DA

T13

/ISI_

VS

YN

C/T

IOB

514

4

PC

15/L

CD

DA

T15

/ISI_

MC

K14

6

PC

16/L

CD

DA

T16

/E1_

RX

ER

/UT

XD

114

8

PC

18/L

CD

DA

T18

/E1_

TX

0/P

WM

015

0

PC

20/L

CD

DA

T20

/E1_

RX

0/P

WM

215

2

PC

23/L

CD

DA

T23

/RX

D3

156

PC

25/C

TS

315

8

PC

27/L

CD

VS

YN

C/E

1_T

XE

N/R

ST

116

0

PC

28/L

CD

HS

YN

C/E

1_C

RS

DV

/CT

S1

162

PC

30/L

CD

PC

K/E

1_M

DC

164

PB

1/E

0_R

X1/

CT

S2

170

PB

3/E

0_R

XD

V/S

PI0

_NP

CS

317

2

PB

5/E

0_M

DIO

/TW

CK

217

4

PB

7/E

0_T

XE

N/A

D8

176

GN

DA

NA

117

8

PB

10/E

0_T

X1/

PC

K0/

AD

1118

0

PB

12/E

0_T

X3/

PW

M1/

AD

118

2

PB

14/E

0_R

X3/

PW

M3/

AD

318

4

PB

16/E

0_C

RS

/AD

518

6

GN

DA

NA

218

8

RF

U5

35R

FU

636

RF

U7

37

VD

DN

F1

61V

DD

NF

262

NC

73

VD

DIO

P0_

087

VD

DIO

P0_

188

GN

D13

99

GN

D14

107

GN

D15

119

GN

D16

114

GN

D17

126

GN

D18

135

GN

D19

142

GN

D20

147

GN

D21

154

GN

D22

161

GN

D23

191

VD

DIO

P1_

012

7V

DD

IOP

1_1

128

VD

DA

NA

_016

7V

DD

AN

A_1

168

SE

LCO

NF

IG16

6

AD

VR

EF

190

ET

H0_

TX

+19

3

ET

H0_

TX

-19

5

ET

H0_

RX

+19

7

ET

H0_

RX

-19

9

LED

019

2

LED

119

4

LED

219

6

AV

DD

T19

8

GN

D_E

TH

200

JP3

JP3

1

2

3

J3 HD

2X20

-HH

J3 HD

2X20

-HH

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

JP9

SIP

2

JP9

SIP

2

12

JP1

JP1

1

2

3

J1 HD

2X20

-HH

J1 HD

2X20

-HH

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940


7

Figure 3-6. AUDIO Schematic

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TF

TD

TK

IIS of Audio Interface

in Slave Mode

TW

D0

TW

I_ad

dr

TW

CK

0

MODE = 0: 2-wire

MPU mode for 9x5

TWI interface

CSB = 1:

addr=0011011

RF

RD

RK

PCK0

R164 near SODIMM

LIN

E_I

N

HE

AD

PH

ON

E

R162 near CODEC

BD

erek

11-O

ct-1

0X

.XX

X-X

XX

-XX

AU

DIO

_GN

D

AU

DIO

_GN

DA

UD

IO_G

ND

AU

DIO

_GN

D

AU

DIO

_GN

D

AU

DIO

_GN

DA

UD

IO_G

ND

AU

DIO

_GN

D

VC

C_D

AC

AU

DIO

_GN

D

AU

DIO

_GN

D

VD

DIO

P0

VD

DIO

P0

VD

DIO

P0

VC

C_D

AC

AU

DIO

_GN

D

AU

DIO

_GN

D

PB

10{3

,10}

PA

24{3

}P

A26

{3}

PA

25{3

}

PA

29{3

}P

A27

{3}

PA

30{3

,14}

PA

31{3

,14}

PA

28{3

} RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

AL

E1/

1R

EV

.S

HE

ET

This

agr

eem

ent i

s ou

r pr

oper

ty. R

epro

duct

ion

and

publ

icat

ion

with

out o

ur w

ritte

n au

thor

izat

ion

shal

l exp

ose

offe

nder

to le

gal p

roce

edin

gs.

A

AT

91S

AM

9x5-

EK

8 14B

XX

-XX

X-X

XD

erek

X.X

AU

DIO

10-J

UN

-10

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

AL

E1/

1R

EV

.S

HE

ET

This

agr

eem

ent i

s ou

r pr

oper

ty. R

epro

duct

ion

and

publ

icat

ion

with

out o

ur w

ritte

n au

thor

izat

ion

shal

l exp

ose

offe

nder

to le

gal p

roce

edin

gs.

A

AT

91S

AM

9x5-

EK

8 14B

XX

-XX

X-X

XD

erek

X.X

AU

DIO

10-J

UN

-10

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

AL

E1/

1R

EV

.S

HE

ET

This

agr

eem

ent i

s ou

r pr

oper

ty. R

epro

duct

ion

and

publ

icat

ion

with

out o

ur w

ritte

n au

thor

izat

ion

shal

l exp

ose

offe

nder

to le

gal p

roce

edin

gs.

A

AT

91S

AM

9x5-

EK

8 14B

XX

-XX

X-X

XD

erek

X.X

AU

DIO

10-J

UN

-10

C43

470p

C43

470p

C52

1uC

521u

R90

47k

R90

47k

J15

ST

ER

EO

_3.5

mm

J15

ST

ER

EO

_3.5

mm

1

34

25

C42

470p

C42

470p

C48

10u

C48

10u

L3 220o

hm a

t 100

MH

zL3 22

0ohm

at 1

00M

Hz

12

L18

220o

hm a

t 100

MH

zL1

822

0ohm

at 1

00M

Hz

12

R81

5.6K

R81

5.6K

R80

5.6K

R80

5.6K

C11

610

0nC

116

100n

R76

10k

R76

10k C

4710

0nC

4710

0nR77

4.7k

R77

4.7k

C46

10u

C46

10u

+

C60

220u

F/1

0V

+

C60

220u

F/1

0V

C44

470p

C44

470p

J13

ST

ER

EO

_3.5

mm

J13

ST

ER

EO

_3.5

mm

1

34

25

C54

10u

C54

10u

C45

100n

C45

100n

R75

10k

R75

10k

LL

INE

IN

RL

INE

IN

LO

UT

RO

UT

VM

IDM

ICIN

MIC

BIA

S

RH

PO

UT

LH

PO

UT

MO

DE

SD

INS

CL

K

CS

B

AD

CL

RC

DB

VD

D

DC

VD

D

AV

DD

AG

ND

HP

GN

D

CL

KO

UT

XT

I/M

CL

K

XT

O

OSC

AD

CD

AT

DA

CD

AT

DA

CL

RC

DG

ND

BC

LK

HP

VD

D

MN

10W

M87

31S

ED

S

LL

INE

IN

RL

INE

IN

LO

UT

RO

UT

VM

IDM

ICIN

MIC

BIA

S

RH

PO

UT

LH

PO

UT

MO

DE

SD

INS

CL

K

CS

B

AD

CL

RC

DB

VD

D

DC

VD

D

AV

DD

AG

ND

HP

GN

D

CL

KO

UT

XT

I/M

CL

K

XT

O

OSC

AD

CD

AT

DA

CD

AT

DA

CL

RC

DG

ND

BC

LK

HP

VD

D

MN

10W

M87

31S

ED

S 14

910

27

1920

15

16 43 5 721

28

123 2422

1312 18 17

11

2 25 26

68

C12

122

pC

121

22p

C12

222

pC

122

22p

R88

0RR

880R

R79

4.7k

R79

4.7k

L7 220o

hm a

t 100

MH

zL7 22

0ohm

at 1

00M

Hz

12

C11

710

0nC

117

100n

C41

470p

C41

470p

L6 220o

hm a

t 100

MH

zL6 22

0ohm

at 1

00M

Hz

12

Y3

12.2

88M

Hz

Y3

12.2

88M

Hz

13

2 4

R78

5.6K

R78

5.6K

C50

100n

C50

100n

C62

470p

C62

470p

R16

4

22R

DN

P

R16

4

22R

DN

P R74

5.6K

R74

5.6K

C61

470p

C61

470p

C40

10u

C40

10u

+

C59

220u

F/1

0V

+

C59

220u

F/1

0V

C53

100n

C53

100n

R86

0RR

860R

C56

100n

C56

100n

C11

510

uC

115

10u

R87

33R

R87

33R

R16

20R

DN

P

R16

20R

DN

P

R16

50R

R16

50R

L4 220o

hm a

t 100

MH

zL4 22

0ohm

at 1

00M

Hz

12

C49

1uC

491u

R91

47k

R91

47k

R89

0RR

890R

C55

100n

C55

100n

C51

10u

C51

10u


Figure 3-7. LCD&ISI Schematic

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

ISI o

nly

Fo

r G

25L

CD

Fo

r G

15/G

35/X

35L

CD

&IS

I

LC

D/T

SC

LCDDAT0

LCDDAT17

LCDDAT2

LCDDEN

LCDDAT4

LCDDAT7

LCDDAT19

LCDDAT9

LCDDAT21

LCDDAT11

LCDDAT12

LCDDAT22

LCDDAT14

LCDDISP

LCDPWM

LCDDAT3

LCDDAT1

LCDPCK6

TA

DD

CL

5T

AD

DC

LLCDDAT8

LCDDAT10

LCDDAT13

LCDDAT15

LCDDAT16

LCDDAT18

LCDDAT20

LCDDAT23

LCDVSYNC

AD0_XP

AD2_YP

AD4_LR

AD1_XM

AD3_YM

SPI1_MISO

SPI1_MOSI

SPI1_SPCK

ZB_IRQ0

SPI1_NPCS1

ZB_IRQ1

0D

WT

0K

CW

T

ISI_D1

ISI_D3

ISI_D5

ISI_D7

ISI_D9

ISI_D11

ISI_MCK

ISI_VSYNC

ISI_HSYNC

ISI_PCK

ISI_D0

ISI_D2

ISI_D4

ISI_D6

ISI_D8

ISI_D10

EN_PWRLCD

ONE_WIRE

BD

erek

11-O

ct-1

0X

.XX

X-X

XX

-XX

LCD

HS

YN

C

PB

18LC

DH

SY

NC

5V_I

NT

ER

3V3

PA

13{3

,5,6

}P

A7

{3,6

}P

A31

{3,8

}

PC

1{3

}P

C3

{3}

PC

5{3

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3.7 Software Implementation

The software demo provided for this application includes the contents listed in Table 3-1.

3.8 Code Overview

Users can use commands through the debug interface to start and stop playing or recording the audio, downloadthe PCM data into the memory of SAM9G15 by Xmodem of HyperTerminal. Figure 3-9 is the overview for thefunctions of this demo.

Figure 3-9. Function Flow Chart

Table 3-1. Contents of Provided Software Demo

Directory Description

librariesIncludes the library files to support the SAM9G15 chip, EK and other peripherals such as USB, storage. Users can simply call the functions in the libraries.

usart_i2s_dma_audio Includes the application IAR project

Readme.txt A brief introduction document to tell users how to make the code run on SAM9G15-EK

System Initialization

Timer Counter Initializtion

Wait for Command

Command Check

USART Initialization

DMA Configuration

Send the Audio to Memory from X-

modermStop RecordingStop playback

Codec Initialization

Timer Counter Initialization

DMA Configuration

USART Initialization

Timer Counter Initialization

Play the PCM data in Memory

Record the PCM from Line-in


11

3.8.1 System Initialization

In this part, it is necessary to disable the system watchdog, configure the system clock, and configure the GPIO forthe corresponding peripherals such as pins of USART2, TIOA0, TIOA1, etc.

Here is the code for reference:/* Disable watchdog */ WDT_Disable( WDT ) ;

/* System tick configuration */ _ConfigureTick(BOARD_MCK);

/* Configure all pins used for this application */PIO_Configure(pins, PIO_LISTSIZE(pins));

As for the pins structure, it includes all the PIOs used in this demo:/** List of pins to configure. */static const Pin pins[] = {

PIN_GPIO_PA26, //used as GPIO

PIN_GPIO_PB7, //used as GPIO

PINS_TWI0,PIN_TC0_TIOA0,

PIN_TC0_TIOA1,PIN_USART2_RXD,PIN_USART2_TXD,PIN_USART2_SCK,PIN_USART2_CTS,PIN_PCK0

};


3.8.2 Timer Counter Initialization

In this part, mainly set the clock source and working mode for the two TC channels according to the defaultfrequency firstly. And also need to define the start level status for the two waveform outputs.

/* Initialize TC, to make sure TC0 Ch0 TIOA output initial status is high level, so pls make sure this initialization done before any other action */ _TcWaveformInitialize(wavFrequency,wavBitsPerSample); /* Start the TC once, to make sure the initial output level of TIOA0&TIOA1 are high when next time TC starts */ _TcClkEnable(); _TcClkDisable();

In function _TcWaveformInitialize(), there are two functions to set each TC channel in detailed.static void TcCh0WaveformConfigure(uint32_t frequency){ const uint32_t divisors[5] = {2, 8, 32, 128, BOARD_MCK / 32768}; uint32_t ra, rc;

/* Set channel 0 as waveform mode */REG_TC0_CMR0 =

waveformConfigurations[configuration].clockSelection/* Waveform Clock Selection */

| TC_CMR_WAVE /* Waveform mode is enabled */ | TC_CMR_ACPA_CLEAR /* RA Compare Effect: Clear */ | TC_CMR_ACPC_SET /* RC Compare Effect: Set */ | TC_CMR_WAVSEL_UP_RC /* UP mode with automatic trigger on RC Compare */

| TC_CMR_ASWTRG_SET; /* Soft trigger effect on TIOA: Set */

/* Configure the BCLK frequency based on the wav file's sample frequency */

if (frequency == 8000)configuration = 0;

else if (frequency == 32000)configuration = 1;



else {

printf("This frequency: %d is not supported \r\n", frequency);

return; }

/* Set the RA and RC compare register value */rc = (BOARD_MCK /

divisors[waveformConfigurations[configuration].clockSelection]) / waveformConfigurations[configuration].frequency; REG_TC0_RC0 = rc; ra = (100 - waveformConfigurations[configuration].dutyCycle) * rc / 100; REG_TC0_RA0 = ra;


13

}

/** * \brief Configure clock, frequency and duty cycle for TC0 channel 1 in waveform mode. */static void TcCh1WaveformConfigure(uint8_t DatLen){

uint32_t ra, rc;/* Set channel 1's clock source as TIOA0 */REG_TC0_BMR = TC_BMR_TC1XC1S_TIOA0;/* Set channel 1 as waveform mode */REG_TC0_CMR1 = TC_CMR_TCCLKS_XC1 /* Waveform Clock Selection */

| TC_CMR_CLKI /*counter is increamented on falling edge of the clock */ | TC_CMR_WAVE /* Waveform mode is enabled */ | TC_CMR_ACPA_CLEAR /* RA Compare Effect: clear */ | TC_CMR_ACPC_SET /* RC Compare Effect: set */ | TC_CMR_WAVSEL_UP_RC /* UP mode with automatic trigger on RC Compare */

| TC_CMR_ASWTRG_SET; /* Soft trigger effect on TIOA: Set */ ra = DatLen; REG_TC0_RA1 = ra; rc = DatLen*2; REG_TC0_RC1 = rc;}


3.8.3 Codec Initialization

In this part, SAM9G15 will configure the WM8731 with the I2C interface to set the headphone output volume, PCMdata format, and configure the sampling frequency, etc.

/** * Initialize PCK & WM8731 for Audio * 12MHz PCK */static void _ConfigureAudio(uint32_t sampleRate, uint8_t sampleBit){ /* -- WM8731 Initialize -- */

/* Enable TWI peripheral clock */ PMC_EnablePeripheral(ID_TWI0); /* Configure and enable the TWI (required for accessing the DAC) */ TWI_ConfigureMaster(TWI0, TWI_CLOCK, BOARD_MCK); TWID_Initialize(&twid, TWI0);

/* WM8731 as slave */

printf("Initialize WM8731 in Slave mode\r\n");

/* If not use OSC on Codec, use 12M PCK, we select this mode in this demo */ /* USB mode, can support 8k/32k/44.1k/48k */

WM8731_Init_1(&twid, WM8731_SLAVE_ADDRESS, 1, 0, 0,sampleRate,sampleBit);

/* Enable the DAC master clock (Uses 12M, USB mode) */REG_PMC_PCK = PMC_MCKR_CSS_MAIN_CLK | PMC_MCKR_PRES_CLOCK;/* Programmable Clock 0 Output Enable */REG_PMC_SCER = PMC_SCER_PCK0;/* Wait for the PCKRDYx bit to be set in the PMC_SR register */while ((REG_PMC_SR & PMC_SR_PCKRDY0) == 0);

/* -- Load WAV file information if wav file is available -- */CheckWavFile();

}


15

3.8.4 USART Initialization

In this part, it is necessary to configure the USART to work in SPI slave mode, set the transferred data length to 8-bit per each transfer with MSB firstly, and sample the data in the rising edge of the clock, etc.

Please refer to the following code for detailed settings./** * \brief Configure USART2 in SPI slave mode. */static void _ConfigureUsart( void ){ uint32_t mode = US_MR_USART_MODE_SPI_SLAVE /* USART works as SPI Slave mode */

| US_MR_CHRL_8_BIT /*Transmit data length is 8-bit*/ | US_MR_CHMODE_NORMAL

| US_SPI_BPMODE_3;

/* Enable the peripheral clock for USART2 in the PMC */ PMC_EnablePeripheral( ID_USART2 );

/* Configure the USART in the desired mode @USART_SPI_CLK bauds */ USART_Configure( USART2, mode, USART_SPI_CLK, BOARD_MCK );

}


3.8.5 DMA Configuration

In this part, it is necessary to create the DMA channels and set callback function for both USART transmitting andreceiving.

/** * \brief DMA driver configuration. */ static void _ConfigureDma(void) { uint32_t dwCfg; uint8_t iController; /* Driver initialize */ DMAD_Initialize( &dmad, 0); /* IRQ configure */ IRQ_ConfigureIT(ID_DMAC0, 0, DMA_IrqHandler); IRQ_ConfigureIT(ID_DMAC1, 0, DMA_IrqHandler); IRQ_EnableIT(ID_DMAC0); IRQ_EnableIT(ID_DMAC1);

/* Allocate DMA channels for USART2 */ usart2DmaTxChannel = DMAD_AllocateChannel( &dmad, DMAD_TRANSFER_MEMORY, ID_USART2); usart2DmaRxChannel = DMAD_AllocateChannel( &dmad, ID_USART2, DMAD_TRANSFER_MEMORY); if ( usart2DmaTxChannel == DMAD_ALLOC_FAILED || usart2DmaRxChannel == DMAD_ALLOC_FAILED ) { printf("DMA channel allocate error\n\r"); while(1); }

/* Set RX callback */ DMAD_SetCallback(&dmad, usart2DmaRxChannel, (DmadTransferCallback)_DmaRxCallback, 0); /* Set TX callback */ DMAD_SetCallback(&dmad, usart2DmaTxChannel, (DmadTransferCallback)_DmaTxCallback, 0);

/* Configure DMA RX channel */ iController = (usart2DmaRxChannel >> 8); dwCfg = 0 | DMAC_CFG_SRC_PER(

DMAIF_Get_ChannelNumber( iController, ID_USART2, DMAD_TRANSFER_RX )) | DMAC_CFG_SRC_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG; DMAD_PrepareChannel( &dmad, usart2DmaRxChannel, dwCfg );

printf("USART2 DMA RX channel number: %d\r\n",DMAIF_Get_ChannelNumber( iController, ID_USART2, DMAD_TRANSFER_RX ));

/* Configure DMA TX channel */ iController = (usart2DmaTxChannel >> 8); dwCfg = 0 | DMAC_CFG_DST_PER(


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DMAIF_Get_ChannelNumber( iController, ID_USART2, DMAD_TRANSFER_TX )) | DMAC_CFG_DST_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG; DMAD_PrepareChannel( &dmad, usart2DmaTxChannel, dwCfg );

printf("USART2 DMA TX channel number: %d\r\n",DMAIF_Get_ChannelNumber( iController, ID_USART2, DMAD_TRANSFER_TX )); }

3.8.6 Audio PCM Data Playback

In this part, SAM9G15 will send the PCM data in its memory to the codec with the USART port. Before sending thedata to codec, the system must perform two actions:

ensure that each PCM sample stored in the memory can be sent to the codec with the MSB first order

configure the LLI DMA pointer for each DMA transfer buffer:

The 16-bit PCM data from WAV file is stored in the memory as described below.

The following is the storage order in PCM files:

When the PCM files are sent to SAM9G15’s memory, they will be stored in the order shown in Figure 3-10.

Figure 3-10. DMA Data Storage

For the USART DMA transfer, each time it will send one byte because the maximum data length for transfer is 8-bit. So every time when transferring one sample (e.g., 16-bit), DMA will transfer the bytes stored in the loweraddress firstly, and then the bytes stored in the higher address. To make sure the 16-bit sample can be transferred

Sample 0 Sample 1 ... Sample nHigh Byte 0, Low Byte 0 High Byte 1, Low Byte 1 ... High Byte n, Low Byte n

Buffer in Memory

Sample n-1 MSB

… ...

Sample n-1 LSB

… ...

Sample 1 MSB

Sample 1 LSB

Sample 0 MSB

Sample 0 LSB

Low Address

High Address

Buffer in RAM

Sample n MSB

Sample n LSB


with MSB firstly, we need to convert the Low bytes and High bytes of each sample before starting the DMAtransfer. For the 24-bit or 32-bit sample, the data also need to be converted with the same rule.

Note: For the PCM data recorded in the memory, there is no need to do the inversion because the recorded data received from USART is directly from codec and it can be sent back to the codec without data processing.

After having ensured that each PCM sample stored in the memory can be sent to the codec with the MSB firstorder and after having configured the LLI DMA pointer for each DMA transfer buffer, the system can start the DMAtransfer by enabling the TC clock generation and the recorded data becomes audible from the headphone.

The following is the detailed code for reference:/** * \brief Play a WAV file pre-loaded in DDRAM. */static void PlayWav(uint32_t wavDataAddress, uint32_t wavSize){ uint32_t size; uint32_t src; int i;

remainingBytes = wavSize; transmittedBytes = 0; /* For the wav file, the sample storage is like: */

/*Sample 0 - Sample 1 - Sample n */

/*High Byte0, Low Byte0 - High Byte1, Low Byte1 - High Byten, Low Byten */

/ *For SAM9G15 DMA transmission, it sends the bytes with lower address firstly. But for I2S, MSB should be transmitted firstly. */

/* So before starting the DMA transmission, need to reverse the high and low bytes of the samples in the source file to adapt the DMA transmission order. */

/* For the recorded PCM data in the flash, there is no need to do the data reversion. */

/* Here only provide the data conversion sample for 16-bit data, users can add their own data processing code here. */

if (userWav->bitsPerSample == 16){

//change the wav file contents valueuint16_t *pWords = (uint16_t*)(wavDataAddress);uint16_t tmp1, tmp2;

/* Audio Data Processing: only for 16-bit sample now */

/* Convert the high and low bytes of one sample, because DMA transfers the lower bytes firstly and WM7831 requires MSB first. */

if (DatConverted ==0){

for (i =0; i<(wavSize/2);i++ ){

tmp1 = pWords[i]&0x00ff;tmp2 = pWords[i]&0xff00;pWords[i] = (tmp1<<8)|(tmp2>>8);

//printf("2. pWords[%d] = %x\r\n", i, pWords[i]);


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}DatConverted = 1;}

}

/* Set the DMA LLI to transmit the audio data */

src = wavDataAddress+ transmittedBytes;TX_LLI_NO = 0;for ( i = 0; (i<MAX_LLI_SIZE&& remainingBytes>0); i++){

size = min(remainingBytes, 65535);

txLLI[i].dwSrcAddr = (uint32_t)src;txLLI[i].dwDstAddr = (uint32_t)(&USART2->US_THR);txLLI[i].dwCtrlA = DMAC_CTRLA_BTSIZE(size)

|DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;

txLLI[i].dwCtrlB = DMAC_CTRLB_FC_MEM2PER_DMA_FC | DMAC_CTRLB_SRC_INCR_INCREMENTING | DMAC_CTRLB_DST_INCR_FIXED;

txLLI[i].dwDscAddr =((uint32_t)&txLLI[ i + 1 ].dwSrcAddr);src += size;remainingBytes -=size;transmittedBytes +=size;TX_LLI_NO++;//printf("i = %d\r\n",i);

}txLLI[i-1].dwDscAddr = 0;

/*Start DMA transmit*/isWavPlaying = 1;DMAD_PrepareMultiTransfer(&dmad, usart2DmaTxChannel, &txLLI[0]);DMAD_StartTransfer(&dmad, usart2DmaTxChannel);USART_SetTransmitterEnabled(USART2, 1 ) ;Wait (100);_TcClkEnable();

}


3.8.7 Record PCM Data from Line-in

In this function, we need to set the LLI DMA pointers for the receive buffer and then we can start the recording byenabling the DMA transfer and TC clock generation.

/* Record the audio from Line-in input */static void RecordWav(uint32_t recordDataAddr){

uint32_t src;uint32_t size;uint8_t i;ReceivedBytes = 0;

/* Use LLI to transmit data with DMA */src = recordDataAddr+ ReceivedBytes;RX_LLI_NO = 0;for ( i = 0; (i<MAX_LLI_SIZE&& ReceivedBytes<MAX_RECORD_SIZE); i++){

size = 65535;

rxLLI[i].dwSrcAddr = (uint32_t)(&USART2->US_RHR);rxLLI[i].dwDstAddr = (uint32_t)src;rxLLI[i].dwCtrlA = DMAC_CTRLA_BTSIZE(size)

| DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;

rxLLI[i].dwCtrlB = DMAC_CTRLB_FC_PER2MEM_DMA_FC | DMAC_CTRLB_SRC_INCR_FIXED | DMAC_CTRLB_DST_INCR_INCREMENTING;

rxLLI[i].dwDscAddr =((uint32_t)&rxLLI[ i + 1 ].dwSrcAddr);src += size;ReceivedBytes +=size;RX_LLI_NO++;

}rxLLI[i-1].dwDscAddr = 0;

/* Start DMA Receive */isRecording = 1; DMAD_PrepareMultiTransfer(&dmad, usart2DmaRxChannel, &rxLLI[0]);DMAD_StartTransfer(&dmad, usart2DmaRxChannel);USART_SetReceiverEnabled(USART2, 1 );Wait (100);_TcClkEnable();

}


21

3.8.8 Callback Function for DMA

The callback function is used to handle condition checking when the DMA interrupt happens. Normally we willcheck if the LLI buffer reaches the end or if the PCM data in the memory is finished.

/** * \brief DMA TX callback. */static void _DmaTxCallback(uint8_t status, void* pArg){ pArg = pArg; //printf("Call back \r\n"); if (status >= DMAD_ERROR) { isWavPlaying = 0; isWavPlaying = 0; return; } INT_NO++;

/* Check if read the last LLI, if yes, stop the playing */ if (INT_NO == TX_LLI_NO) { isWavPlaying = 0;

INT_NO = 0;/* Disable USART2 SPI transmitting */USART_SetTransmitterEnabled( USART2, 0 ) ;/*Stop DMA*/

DMAD_StopTransfer(&dmad, usart2DmaTxChannel);/* Stop BCLK and LRCLK */_TcClkDisable();DisplayMenu();

}

}

/** * \brief DMA RX callback. */static void _DmaRxCallback(uint8_t status, void* pArg){

pArg = pArg;if (status >= DMAD_ERROR){

isRecording= 0; return;

}INT_NO++;

/* Check if read the last LLI, if yes, stop the recording */ if (INT_NO == RX_LLI_NO) { isRecording = 0;

INT_NO = 0;


/* Disable USART2 SPI receiving */USART_SetReceiverEnabled( USART2, 0 );/*Stop DMA*/

DMAD_StopTransfer(&dmad, usart2DmaRxChannel);/*Stop BCLK and LRCLK*/_TcClkDisable();DisplayMenu();

}}

3.8.9 Stop Playback or Recording

Users can stop audio playing or recording by inputting commands from the Debug window.


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4. Conclusion

With this application demo, users can add one more audio interface in their application if more than one I2Sinterface is required. Although in this application we only provide the Left-justified mode demo code, users canvery easily modify the code to generate the waveform they want to keep compliant with I2S or Right-justified mode.


5. Revision History

Table 5-1. Revision History

Document Rev.11260A Changes

17-Mar-15 First issue.


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