Two-Dimensional MOSFET Dopant Profile by Inverse Modeling

via Source/Drain-to-Substrate Capacitance Measurement

C.Y.T. Chiang*, Y.T. Yeow* and R Ghodsi**

*Department of Computer Science and Electrical EngineeringThe University of Queensland, Brisbane, Qld, Australia 4072

Phone: +61-7-33654442 Fax: +61-7-33654999email: ytchiang@netscape.net

**Cypress Semiconductor, San Jose, CA 95134

ABSTRACT

This paper proposes and demonstrates a new approachto 2-dimensional dopant profile extraction for MOSFETÕsby treating the source/drain-to-substrate junction as a gateddiode. The small-signal capacitance of the diode measuredas a function of gate and source/drain bias is used as thetarget to be matched in an inverse modeling process. It isshown that this capacitance allows both the substratedopant profile in the channel region and the source/drain-to-substrate profile parallel to the surface to be evaluatedwith a single set of measurement data. Experimental resultsfor n-MOSFETs with drawn channel length = 1 µm ispresented. Comparison of other electrical measurementwith simulation data based on the extracted profile is alsogiven.

Keywords: MOSFETÕs, semiconductor device doping,semiconductor device measurements, semiconductor devicemodeling.

1 INTRODUCTION

The design and realization of an appropriate dopantconcentration profile is critical in achieving the desiredelectrical characteristics of a modern MOSFET. Anaccurately determined dopant profile is also important forthe calibration of process simulators. While many physico-chemical analysis techniques are now available for dopantprofile extraction [1], they require extra chemicalprocessing and data calibration. With advances innumerical device simulation, the inverse modelingtechnique using a particular set of experimental data hasbecome popular for the extraction of MOSFET 2-D dopantprofile: Khalil et al. applied this method to a combination ofgate-to-source/drain capacitance (Cgsd) and drain/source-to-substrate junction (Csdb) [2] and Lee et al. used I-V data inthe subthreshold region [3]. In this method one or moremeasured electrical quantities of a device are chosen as thetarget data; numerical simulation is then carried out with aninitial dopant profile for the device to calculate thecorresponding electrical quantities. The assumed profile is

then adjusted iteratively to obtain an optimal match ofsimulation data to their experimental target.

An inverse modeling process using only the capacitanceof the drain/source-to-substrate junction (Csdb) forextracting the complete 2-dimensional profile ofMOSFET's is presented. We treat the junction as a gateddiode under the control of gate bias and junction reversebias. With channel in accumulation, the measuredcapacitance includes the depletion capacitance of the innersidewall junction and is therefore a function thesource/drain-to-substrate junction profile in a directionparallel to the surface. By sweeping the junction reversebias and the channel to different levels of accumulation, wecause the depletion region of this sidewall junction tosweep to varying extent on both sides of the junction. Bybiasing the channel into inversion, the measuredcapacitance includes the inversion layer-to-substratecapacitance which is dependent on the substrate dopantprofile in channel region [4]. Thus by measuring thiscapacitance over a suitable range of gate and source/drainbias, we would have captured the contributions to themeasured capacitance from the dopant concentration ofwhole active region of the transistor ie where the field-effect action of the gate is active. In comparison, the gate-to-source/drain capacitance referred to in previousparagraph is more a function of the channel potentialdistribution along the surface arising from a givensource/drain reverse bias. Its dependence on the surfacedopant profile is through the fact that the dopant profileinfluences the channel potential distribution.

The nature of the gated diode is such that thecontributions to the measured capacitance from the bottomand the outer sidewall junctions can be determined andsubtracted from the measured data. Only the capacitancecontributions from the inner sidewall junction and inversionlayer-to-substrate junction are used as the target data in theinverse modeling process. This implies that the simulationwork does not have to model the length of the experimentalsource and drain junctions or the outer sidewall junctions.

2 BASIS OF INVERSE MODELING

Csdb has four components: Csdb=Cinvb+Csdb1+Csdb2+Csdb3,inversion layer-to-substrate capacitance, inner sidewallcapacitance, bottom capacitance and outer sidewallcapacitance respectively, this is shown in Fig. 1.

As we vary the gate bias, the carrier type andconcentration in the channel region changes, and hence alsothe capacitances of the first two components which areassociated with the channel region.

Fig. 2 shows the measured Csdb as a function of gate-to-substrate bias Vgb and source/drain-to substrate reverse biasVsdb for an n-channel LDD MOSFET (W/L = 50 µm/1µm,gate oxide = 15 nm). For a given gate bias, the measuredcapacitance decreases with increasing junction reverse biasdue to the increase of the depletion widths of the individualcomponents. It can also be seen that at Vg b = 0 V,corresponding to a depleted surface in the transistorchannel, the capacitance shows a minimum for all Vsdb's. Asthe channel goes into accumulation (Vgb < 0 V) the innersidewall capacitance Csdb1 comes into existence and themeasured capacitance increases due to reduction of thedepletion width of this sidewall junction with increasingdegree of accumulation. In inversion (Vg b > 0 V) theincrease in the measured capacitance is due to theintroduction of the inversion layer-to-substrate capacitanceCinvb which very rapidly saturates to a level corresponding afixed substrate depletion width (at the given source/drainreverse bias). Cinvb and Csdb1 are functions of the channelregion substrate and source/drain junction dopant profiles tobe extracted as well as functions of the gate-to-substratebias Vgb and the source/drain-to-substrate bias Vsdb. Theirsum, (Cinvb + Csdb1) is chosen as the target experimental datain our inverse modeling.

When the gate bias is such that the channel region isdepleted, both the above components disappear: Cinvb

because the inversion layer is absent, Csdb1 because thesubstrate next to the sidewall is completely depleted.Detailed examination of this raw measured Csdb as afunction of Vgb in Fig. 2 reveals that this capacitance has avery ÒflatÓ minimum. This supports the argument that at theminimum capacitance point there are no contributions fromthe Vgb-dependent components Cinvb and Csdb1. This applies

for the complete range of Vsdb, giving rise to the minimumcapacitance line seen in Fig. 2. This minimum capacitanceline therefore represents the remaining capacitancecomponents, i.e. (Csdb2 + Csdb3) which is a function ofsource/drain bias but not the gate bias. They are not ofinterest in our extraction process and are removed from themeasured capacitance before applying inverse modeling.This is achieved by subtracting the minimum capacitanceline from all other measured data to leave behind (Cinvb +Csdb1) as a function of Vsdb and Vgb. The results are shownin Fig. 3.

The dopant profile extraction process starts by buildingup a suitable dopant profile model for the MOSFET with anumber of analytical profiles reflecting the variousfabrication processes involved. Each analytical profile hasits own set of adjustable parameters. A numerical devicesimulation program is then used to evaluate the gated diodecapacitance for the assumed profile and then the parametersare adjusted to produce the best fit of the simulatedcapacitance to the measured data. For matching purposes,the experimental capacitance is reduced to per unit widthquantity for compatibility with results of 2-D simulator.Similar subtraction process described in the treatment ofexperimental capacitance is used to remove thecontributions of (Csdb2 + Csdb3) in the simulation data.

CinvbCsbd3

Csdb2

Csdb1

p-substrate

n+ Source n+ Drain

VgbVsdb

Fig. 1. Device bias for Csdb measurement and componentsof Csdb.

Fig. 2. 3-D plot of the measured Csdb as a function of Vgb

and Vsdb.

-6 -3 0 3 6 96

42

00.6

0.620.640.660.680.7

0.720.74

Csdb (

pF)

Vgb (V)

Vsdb (V)

Fig. 3. (Cinv+Csdb1) as a function of Vgb and Vsdb obtainedfrom data in Fig. 2.

-6 -3 0 3 6 96

42

00

0.1

0.2

0.3

0.4

0.5

0.6

Cinv

+ Cs

db1

(fF

m-1)

Vgb (V)

Vsdb (V)

Based on the knowledge of the fabrication processes ofthe devices under test, we have modeled our device thus:source/drain junction by two 2-D Gaussian profiles toaccount for LDD structure, the channel as two 1-DGaussian profiles to account for threshold adjust andpunch-through implants, and the substrate as a constantdopant concentration. The device simulator MEDICI [5] isthen used to compute the simulation Csdb as a function ofVsdb and Vgb and an optimization process is based on theLevenberg-Marquardt algorithm. Subtraction processdescribed in the treatment of experimental capacitance isused to extract the simulation Cinvb+ C sdb1. The bestrepresentation of the actual profile is obtained by adjustingthe Gaussian profile parameters to produce the best fitbetween measured and simulated Cinvb+Csdb1.

3 MEASUREMENT

Fig. 4 shows the instrumentation used to obtain theresults in Fig. 2. The HP4284A LCR meter was used tomeasure the capacitance and to apply the reverse biasbetween the source/drain and the substrate (Vsdb).Measurement signal was 50 mV at 100kHz injected into thesubstrate and detected at the grounded source and drainjunctions. HP 4145A parameter analyzer was used toprovide the necessary gate-to-source/drain bias.

4 RESULTS AND DISCUSSION

Fig. 2 shows the measured Csdb as a function of Vgb andVsdb for a LDD nMOSFET with estimated Leff=0.75 µm(drawn W/L=50 µm/1µm, gate oxide=15 nm). Fig. 3 showsCinvb+Csdb1 obtained from data in Fig. 2 by subtracting theminimum measured Csdb at Vgb=0V. Our analytical profilemodels and associated adjust parameters are described inTable 1. The initial guess of each parameter was set to themiddle of range set and the simulation capacitance Csdb wascalculated for the same bias range used in measurement.Device gate length was set to the same drawn length. Otherdevice parameters such as gate material and work function

difference, which would affect the threshold voltage, wereselected to reflect the experimental device. To optimize theparameters of the analytical models obtained, the simulatorwas programmed to run until the RMS error for the used 20data is less than 5 %. Where necessary the range limits forthe parameters were reset to ensure that the optimizationprocess does not push a parameter to its range limit. Fig. 5is the comparison of the experimental and simulationCinvb+Csdb1 obtained after optimization. The agreement iswithin 5% set in the optimization process. Fig. 6 is the 3-Dplot of the optimized profile.

Region andDopant Modeltype

Parameters Range ofParameters

Distance of Gaussian peakfrom gate edge

0.1 to 0.5 µm

Gaussian Peak at surface 151020 to 551020

cm-3

y direction sigma 0.1 to 0.3 µm

n+ drain implant2-D Gaussian

Ratio of x direction sigmato y direction sigma

0.3 to 0.9

Distance of Gaussian peakfrom gate edge

−0.1 to 0.1 µm

Gaussian peak at surface 151018 to 751018

cm-3

y direction sigma 0.1 to 0.3 µm

n-type LDDimplant2-D Gaussian

Ratio of x direction sigmato y direction sigma

0.3 to 0.9

Gaussian peak at surface 551016 to 151017

cm-3p-type thresholdimplant profile1-D Gaussian y-direction sigma 0.1 to 0.3 µm

Gaussian peak 151016 to 551016

cm-3

Distance of peak fromsurface

0.1 to 0.6 µm

p-type punch-through implant1-D Gaussian

y-direction sigma 0.1 to 0.3 µm

Uniform p-typesubstrate

Dopant concentration 151015 to 251016

cm-3

Table 1. Description of Analytical Profiles Used inInverse Modeling.

Vgsd

p-substrate

HP4284A LCR METER

n+ Source n+ Drain

LCRHIGH LCRLOW

Fig. 4. Instrumentation for measurement of Csdb.

Fig. 5. Comparison of measured and simulation (Cinvb +

Csdb1) per unit width as a function of Vsdb with Vgb as aparameter for the 1 µm device. Lines are experimentaldata, " o" and " " are simulation data. "• " areexperimental points chosen as target data for inversemodeling.

0

0.2

0.4

0.6

0 1 2 3 4 5 6Vsdb (V)

Cinvb

+ C

sdb1

(f

Fm-1

)

9 V ( , )

Vgb = - 6 V- 5 V- 4 V

- 1 V- 2 V- 3 V

We also briefly investigated the effects of changes insome assumed device parameters on extracted profiles: 5%change in gate oxide thickness or gate length leads to amaximum of 10% change in the dopant concentration at thecritical locations.

For validation, we compared the measured Ids-Vds (Fig.7), the subthreshold current (Fig. 8) and the gate-to-draincapacitance (Fig. 9) with the simulation results obtainedusing the extracted profile. Two different mobility models

were tested. They account for dopant concentrationdependence and longitudinal field dependence in the sameway but have different surface-field dependence: MOBA inwhich only the inversion layer is affected by the transversefield and MOBB in which carriers at every position isaffected the transverse field [5]. The comparison indicatesthat simulation results at low transverse fields and currentagree well with measurement. At high drain currents theobserved differences arise more from the difference in themobility models than from accuracy of the extracted dopantprofile.

5 CONCLUSIONS

We have demonstrated a new and simple method ofMOSFET 2-D dopant profile extraction based onsource/drain-to-substrate capacitance. Although thecapacitances involved are small (0-20 fF), our subtractionprocess removes stray capacitances as well as the bottomand outer sidewall junction capacitances. As measurementthere is no drain current flowing in the device, thesimulation results and hence also the extracted dopantprofile are independent of carrier transport model assumedin the simulation.

REFERENCES

[1] A.C. Diebold, M.R. Kump, J.J. Kopanski and D.G.Seiler, J. Vac. Sci. Technol. B, 14, pp. 196-201, 1996.

[2] N. Khalil, J. Faricelli and C.-L. Huang, J. Vac. Sci.Technol. B, 14, pp. 224-230, 1996.

[3] Z. K. Lee, M.B. McIlrath and D.A. Antoniadis, IEEEIEDM. Tech. Dig., p. 683-686, 1997.

[4] C.Y.T. Chiang, C.T.C. Hsu, Y.T. Yeow and R. Ghodsi,IEEE Trans Electron Dev. vol. ED-45, No. 8, pp. 1732-1736. 1998.

[5] MEDICI: Two-Dimensional Device SimulationProgram, TMA Associates, Palo Alto, CA, 1994.

1020

1018

1016N(x

, y)

(cm

- 3)

0.0

0.2

0.4

0.6

0.8

1.0

y (µm) x (µm)

0.0

0.5

1.0

1.5

2.0

S Channel

D

Fig. 6. 3-D plot of the extracted dopant profile. Devicebased on measured data in Fig. 3.

Fig. 8. Comparison of measured and simulation per unitwidth subthreshold Id-Vgs characteristics. Simulation usesthe extracted profile of Fig. 6.

1.00E-13

1.00E-11

1.00E-09

1.00E-07

1.00E-05

-1 0 1 2 3

Vgs (V)

Ids (

Am-1

)

Vds = 0.05 V10-7

10-9

10-11

10-13

10-5

Fig. 7. Comparison of measured and simulation per unitwidth Id-Vds characteristics. Simulation uses the extractedprofile of Fig. 6. Lines are experimental, "o" and "• " aresimulation based on the mobility models including thesurface field effect according to MOBA and MOBBrespectively.

0

0.05

0.1

0.15

0.2

0.25

0 1 2 3 4 5Vds (V)

Ids (

mA

/m

)

Vgs = 3 V

Vgs = 2 V

Vgs = 1 V

Fig. 9. Comparison of measured and simulation per unitwidth Cgd-V gs characteristics. Simulation uses theextracted profile of Fig. 6.

0

0.2

0.4

0.6

0.8

1

1.2

-4 -2 0 2 4 6

Vgs (V)C g

d (fF

m-1) Vds = 0 V

Vds = 1 V

Vds = 2 V