two dimensional highly associative level-two cache design
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Two Dimensional Highly Associative Level-Two Cache Design. Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Mar-26. Outline. Information of literature Background Introduction of CAM - PowerPoint PPT PresentationTRANSCRIPT
Two Dimensional Highly Associative Level-Two Cache Design
Han LiuSupervisor: Seok-Bum Ko
Electrical & Computer Engineering Department 2010-Mar-26
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OutlineInformation of literatureBackgroundIntroduction of CAMPrevious Research2D-Cache Organization2D-Cache OperationComparison
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Information of literatureTwo Dimensional Highly Associative Level-
Two Cache Design
Chuanjun Zhang and Bing Xue
IEEE International Conference on Computer Design, 2008. (ICCD 2008)
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BackgroundHighly associativity is important for L2 CacheHighly associative caches increase HW cost
More comparator More routing wires
Tag stored in CAM cells facilitate tag comparison
CAM cells are power costly and consume large area
LRU replacement is only implemented in low associative caches.
Random replacement needs simple HW, but has higher miss rate than LRU
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Introduction of CAMCAM: Content Addressable Memory
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Previous ResearchCAM based method for low associative
caches are conducted in such aspects,Low HW complexityLow miss rateLow miss penalty
SW controlled fully associative has better flexibility
This work focuses on inexpensive highly associative L2 cache
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2D-Cache Organization
For Column
For Row
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2D-Cache Operation (1/2)Search for the hit block for a cache hit
All the column are searched concurrentlySearch for the victim block for a cache miss
No CAM tag matches the desired addressEach column has one CAM tag matches the desired
addressSome columns have CAM tag hits while remaining
columns do not have CAM tag hits
2D-Cache layout
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2D-Cache Operation (2/2)
LRU in column
Random in Row
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Benchmark Results (1/3)26 SPEC2K
CAM-bit v.s. Miss rate
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Benchmark Results (2/3)
Ways in row v.s. Miss rate(ways in column is constant to 8)
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Benchmark Results (3/3)
Replacement Policy v.s. Miss rate(Row-Column)
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Comparison (1/3)
Energy and Latency of diff. caches
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Comparison (2/3)
IPC reduction over the 8-way caches
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Comparison (3/3)
Energy reduction over the 8-way caches
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Question
Thanks!