Application ReportSCEA042–July 2009

TWL1200 PCB Design GuidelinesJason Battle ................................................................................................. Standard Linear and Logic

ABSTRACTThe Texas Instruments TWL1200 is a 19-bit voltage translator specifically designed tobridge the 1.8-V/2.6-V digital-switching compatibility gap between a 2.6-V basebandand the Wi-Link-6 (WL1271/3), and is optimized for SDIO, UART, and audio functions.When laying out a printed circuit board (PCB) for the TWL1200, careful consideration ofdesign rules and guidelines must be employed to help preserve signal integrity andensure optimal device performance.

This document presents several guidelines for designing the TWL1200 PCB andincludes recommendations for device placement and proper layout.

Contents1 Overview ............................................................................................. 22 Layout and Design Guidelines .................................................................... 23 TWL1200 Reference Design Schematic ....................................................... 104 References......................................................................................... 11

List of Figures

1 Continuous and Split Ground Planes ............................................................ 32 90°, 45°, and Rounded Trace Bends ............................................................ 43 Transmission Line Effects ......................................................................... 44 Power and Ground Rail Bounce .................................................................. 55 Leadaway Trace Routing for BGA or WCSP Packages....................................... 56 Trace Length Sizing for SDIO_DATA0 .......................................................... 67 Proper High-Speed Trace Routing for Crosstalk Reduction .................................. 78 Cross-Sectional View of Blind, Buried, and Traditional Vias.................................. 89 250-µm and 150-µm Via Sizing for TWL1200 and WL1271/3 Pads ......................... 810 Proper TWL1200 Power Supply Decoupling.................................................... 911 TWL1200 Reference Design .................................................................... 10

List of Tables

1 Four-Layer Stackup for TWL1200 PCB Design ................................................ 22 TWL1200 I/O Drive Strengths..................................................................... 6

SCEA042–July 2009 TWL1200 PCB Design Guidelines 1Submit Documentation Feedback

1 Overview

2 Layout and Design Guidelines

2.1 Layer Stackup

Overview www.ti.com

This document provides helpful guidelines that should be followed during TWL1200 layout creation. It is acomplementary document and is not intended to replace the device data sheet. As a result, systemdesigners should still reference all relevant device data sheets and application materials duringsystem-level design to facilitate development of the highest quality end product.

The guidelines presented in this document are based on Texas Instruments' reference platforms andgeneral design recommendations. Follow these rules to avoid unnecessary mistakes that can result inmultiple PCB spins and delay time-to-market of the end product.

For questions or issues that arise during the layout process, contact your local Texas Instrumentsrepresentative or field applications support.

The recommendations in this document refer to a four-layer PCB stackup with the TWL1200 andWL1271/3 devices implemented. Designing with a minimum of four layers is a great general-purpose ruleof thumb for constructing a board with low electromagnetic interference (EMI). Additional layers may beincorporated into the PCB if needed, but they are not required to achieve an efficient design because allnecessary routing for the TWL1200 and WL1271/3 can be accomplished in four layers. If complex designswarrant the need for more layers, the designer must always strive to preserve symmetry by using evennumbered layer counts, as this helps prevent board warping during the fabrication process. For thisTWL1200 PCB design, the chosen dielectric material is FR-4. Ideal board stackup from top to bottom isshown in Table 1.

Table 1. Four-Layer Stackup for TWL1200 PCB DesignThickness Dielectric Loss Width ImpedanceSubclass Name Type Shield(mils) Constant Tangent (mils) (Ω)

1 Surface 1 02 TOP (high speed) Conductor 2.4 1 0 4 42.7273 Dielectric 2 4.5 0.0354 GND Plane 1.2 1 0 YES5 Dielectric 52 4.5 0.0356 VCC Plane 1.2 1 0 YES7 Dielectric 2 4.5 0.0358 BOTTOM (low speed) Conductor 2.4 1 0 4 42.7279 Surface 1 0

High-frequency signals exhibit sensitivity to impedance changes and discontinuities introduced by the useof vias. Placing this layer on the top helps reduce the need for vias and provides easy access for makingdirect interconnections. In addition, it is critical to keep all high-frequency traces at a characteristicimpedance of 50 Ω or less to minimize transmission line effects. Due to clearance constraints that arise indealing with ball grid array (BGA) and wafer chip scale packages (WCSP), a worst case trace width of 4mils was assumed for this design. An impedance calculator or field solver may be used to help ensure thatthe desired trace impedance is achieved. Placing the ground layer directly underneath the high-frequencylayer creates an ideal low-inductance path for return current flow, reducing potential for noise and signalreflection. The power layer is placed immediately underneath the ground layer to increase high-frequencybypass capacitance, which helps strengthen PCB immunity to power supply ripple. Adding thelow-frequency signal routes on the bottom layer is the next logical step, as these signals can typicallyhandle use of vias and other discontinues without suffering adverse effects on performance due to slowercharacteristic rise and fall times. If variations in this board stackup are necessary based on individualapplication requirements, system designers need to recalculate the characteristic trace impedance of allhigh-speed signal layers to ensure that they do not exceed 50 Ω in the new stackup.

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2.2 Reference Planeswww.ti.com Layout and Design Guidelines

For medium- to high-frequency signals, best performance can be achieved by using a ground plane that iscontinuous across the entire PCB. Introducing discontinuities into the ground plane can increase EMIradiation due to larger inductance from potentially longer return current paths. Other unwanted effects canarise when splitting the ground layer into multiple planes. Traces on other layers that cross multiple splitgrounds can result in increased crosstalk due to coupling between these traces and incorrect referenceplanes. For example, routing audio signals, which are analog in nature, across a digital ground plane canstrengthen the parasitic coupling between them, allowing noise to be injected into the digital ground plane.Another consequence is that controlled impedance traces become undefined when the ground plane issplit under them. Signals routed on a continuous ground layer beneath controlled impedance traces havethe same problematic effect as well. An example of continuous and split ground planes is shown inFigure 1.

Figure 1. Continuous and Split Ground Planes

For four-layer boards, the best solution is to create a continuous dedicated plane for ground and to splitthe power supply layer as needed for different supply voltages. Larger PCB designs with spare layers mayremove the need to split the power supply plane, because the extra layers allow for creation of dedicatedpower supply layers. If the ground plane needs to be split for some reason, such as to provide separatedigital and analog ground references for a given system, the following rules should be taken intoconsideration to prevent potential design mistakes:• Minimize loop areas by avoiding signal routes across plane splits.• Connect local grounds to the common ground though a single point. Return current should not be

forced to travel through multiple local grounds before reaching the common ground.• Ensure that individual signal or power planes reference only their correct ground plane.• Bypass capacitors should not be placed between any given signal or power plane and an unrelated

ground plane.

With regard to the TWL1200, these reference plane guidelines are most critical for the SDIO, UART, andPCM audio lines. These traces carry medium- to high-frequency periodic signals that may exhibitincreased sensitivity when routed across plane splits. Low-frequency, non-periodic signals, such as theenable and interrupt control signals routed on the bottom layer, exhibit higher tolerance to suchdiscontinuities. Because the TWL1200 PCB design requires both 2.6-V and 1.8-V rails, it is best to keepthe ground layer continuous and split the power plane into separate areas for the required voltages. Thisallows signal integrity to be maintained without having to add two additional layers to accommodate theextra voltage level.

SCEA042–July 2009 TWL1200 PCB Design Guidelines 3Submit Documentation Feedback

2.3 Routing

2.3.1 Trace Width

2.3.2 Trace Length

Layout and Design Guidelines www.ti.com

Moving on to board routing, careful attention must be paid to trace characteristics such as width, length,and angle. Effective trace resistance is largely determined by its width and this, in turn, has a direct impacton its current carrying capability. Deviations in width across the length of a trace should be avoidedbecause they cause impedance changes which contribute to the reflection of alternating current (ac)signals, causing problematic oscillations and ringing at the electrical source. This is also the reason whythe angle of traces routed around corners becomes so important. 90° bends are seen as a largeimpedance change due to the increase in effective trace width. Better design practice is to use 45° anglesfor all trace bends in general-purpose designs. Higher speed signaling may even warrant the need forrounded trace bends to limit impedance changes as stringently as possible. Examples of each bend styleare shown in Figure 2.

Figure 2. 90°, 45°, and Rounded Trace Bends

Trace length represents an equally important characteristic. As trace length increases, so does theeffective capacitance and inductance. Instead of being seen as a lumped load, the trace starts to behaveas a transmission line with distributed parallel capacitance and series inductance. An equivalent circuit fora trace with excessive length is shown in Figure 3.

Figure 3. Transmission Line Effects

This increases an electrical signal's net RC time constant, resulting in slower output slew rates and longerpropagation delay times. In addition, heavy inductance in the propagated signal's path can contribute toexcessive ringing during rising and falling output transitions as a result of undesired current interactions.

4 TWL1200 PCB Design Guidelines SCEA042–July 2009Submit Documentation Feedback

ActiveOutputs

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2.3.3 Solder Thieving

www.ti.com Layout and Design Guidelines

The critical nature of these characteristics is purely application dependant, and appropriate measuresshould be taken to optimize them based on specific design needs. It is also worth noting that series andparallel termination techniques offer system designers a reliable method of impedance matching for traceswith excessive length. An example of power and ground rail bounce caused by large series inductances isshown in Figure 4.

Figure 4. Power and Ground Rail Bounce

Another caveat for trace design depends on the chosen device package. Ball grid array and wafer chipscale style packages do not have leads and instead use solder balls that are reflowed during the solderprocess. The width of all traces routed to these balls determines how much solder is thieved away fromthem during reflow. Migration of solder away from the ball joints reduces package reliability and increasesrisk of shorted leads as well as other problems. Although solder resist can lessen this effect, it is still bestto use symmetrical leadaway traces as a reliable method to mitigate issues involving solder thieving. As aresult, traces routed from inner balls to just outside of the package outline should have a smaller widththan that of their respective solder pads to prevent solder migration. Trace widths from 4 mils to 6 milsusually suffice as reliable general-purpose leadaway for WCSP and BGA applications. From there,leadaway traces can be routed elsewhere on the board using standard 8-mil to 10-mil traces or larger,depending on impedance matching or ampacity requirements. Correct leadaway trace routing for WCSPand BGA packages is shown in Figure 5.

Figure 5. Leadaway Trace Routing for BGA or WCSP Packages

SCEA042–July 2009 TWL1200 PCB Design Guidelines 5Submit Documentation Feedback

2.3.4 High-Speed Signals

Layout and Design Guidelines www.ti.com

When applying routing guidelines to any trace design, it often proves quite helpful to refer to the devicedata sheet for details on circuit architecture, principles of operation, and application information. Looking atthe TWL1200 data sheet, it is evident that the design consists of both fully-buffered and semi-bufferedinput/output (I/O) sections with varying output drive characteristics (see Table 2).

Table 2. TWL1200 I/O Drive Strengths2 mA 4 mA 8 mA

WLAN_EN(B) AUDIO_OUT(A) SDIO_CLK(B)SLOW_CLK(B) WLAN_IRQ(A) BT_UART_TX(A)

BT_EN(B) CLK_REQ(A) BT_UART_RX(B)AUDIO_IN(B)

AUDIO_CLK(A)BT_UART CTS(B)BT_UART RTS(A)

AUDIO_F-SYNC(A)

The drive strength of a corresponding output gives an indication of the amount of capacitive and/orresistive loading it can handle without severe degradation in its output high (VOH) and output low (VOL)voltages. A closer comparative look at Table 2 also reveals that all TWL1200 SDIO paths except forSDIO_CLK are semi-buffered and offer very little, if any, direct current (dc) drive. The issue is furthercompounded by the fact that these signals switch at frequencies up to 25 MHz, making them relativelyhigh-speed and quite sensitive to local sources of electrical noise that may exist as a result of improperPCB layout design. From this, it becomes simple to conclude that the SDIO paths should receive thehighest priority in proactively minimizing trace length to mitigate transmission line effects. A reasonableapproach is to keep the total trace length for each semi-buffered SDIO line to a maximum of four inches.This includes the entire electrical length from baseband chipset to destination SDIO peripheral, throughthe TWL1200. The routing example in Figure 6 shows proper trace length sizing for the SDIO_DATA0path to and from the A and B sides of the TWL1200.

Figure 6. Trace Length Sizing for SDIO_DATA0

An additional concern arises when routing adjacent traces too close together. Crosstalk is essentially acapacitive coupling event that occurs when a signal "bleeds" onto nearby traces through a parasiticlow-impedance path. To prevent this phenomenon, best design practice is to keep the distance betweenadjacent traces at least 2 to 3 times their width apart. For example, 10-mil traces should be kept at least20 mils away from unrelated traces, pads, vias, or other electrical paths. Figure 7 shows proper distancingbetween a high-speed SDIO trace and a low-speed control signal routed on the same layer.

6 TWL1200 PCB Design Guidelines SCEA042–July 2009Submit Documentation Feedback

www.ti.com Layout and Design Guidelines

Figure 7. Proper High-Speed Trace Routing for Crosstalk Reduction

Another factor relevant to SDIO routing is in regards to discrete resistive and capacitive loading placed onthese I/Os for line termination or filtering purposes. Resistive loading such as external pullup or pulldownresistors create additional problems for these I/Os and should be avoided entirely. If absolutely necessaryfor a given system design, they should be of relatively high-impedance values to prevent the possibility ofoverdriving the internal pullup resistors on the TWL1200 SDIO lines. Values of 50 kΩ or larger are wellsuited for this purpose if the end application finds them absolutely necessary. Failing to use proper valuescan compromise the current-sourcing capability of the internal pullups, creating an effective voltagedivider, which can result in bus contention due to indeterminate input and output logic levels. Excessivecapacitance on these traces is problematic as well and can lead to degradation of rising and falling SDIOedges. This eventually leads to duty-cycle distortion and can make it quite difficult to achieve higher datarates.

Another issue with heavy capacitive loading has to do with the design architecture of the TWL1200'ssemi-buffered, switch-type translation paths. For these I/Os, the dc drive is provided by internal pullupresistors in combination with the open-drain or push-pull drivers that are interfaced with the TWL1200. Theac drive, however, is provided by edge-acceleration circuitry that temporarily decreases the outputimpedance of the TWL1200 SDIO lines to achieve faster output rise and fall times. When excessivecapacitance is present on these lines, the edge-acceleration circuitry times out and switches off before theSDIO output transition is fully completed. As the SDIO output signals are reflected back to the TWL1200,they see a higher impedance than before, causing signal reflections which can lead to glitches, ringing, orother troublesome oscillations. Overall, layout designers should avoid use of discrete loads or connectorson the SDIO lines where possible to keep capacitance low and manageable.

If onboard connectors are necessary, as is the case with Secure Digital (SD) cards, trace lengths to andfrom these connectors can be decreased to help compensate for the additional capacitance.Board-to-board connectors, however, may not be used, as the net capacitance from each board'sparasitics will quickly overwhelm the semi-buffered TWL1200 SDIO lines, causing SDIO communication toand from the TWL1200 to break down. For best results, system designers must keep the capacitance foreach SDIO line to less than 20 pF, as is stated in the Secure Digital specification. This helps to optimizedata rates and provide increased noise margins for high-speed signal lines on the TWL1200 PCB design.

Once all of the TWL1200 SDIO lines are complete, the layout design should continue using the aboveguidelines for the slow clock, Bluetooth (BT) Universal Asynchronous Receiver/Transmitter (UART), andPulse Code Modulation (PCM) audio traces. Finally, routing can proceed with the low-speed controlsignals traces, ideally on the bottom layer.

SCEA042–July 2009 TWL1200 PCB Design Guidelines 7Submit Documentation Feedback

2.3.5 Vias

Layout and Design Guidelines www.ti.com

In routing out the inner balls of the TWL1200 package, it may prove quite difficult to keep sufficientclearance between multiple traces. Having multiple layers grants the designer the flexibility to route signalsout from under the package using vias. As mentioned earlier, good results can be achieved by routing allof the high-speed signals on the top layer and keeping via usage reserved for power, ground, andlow-speed signal connections only. If high-speed signal vias are unavoidable, blind or buried vias can beused instead, but they will contribute to increased cost for the PCB design. Blind vias connect an outerlayer to an internal layer without routing through the entire board, while buried vias provide connectionsbetween internal layers only. This preventative helps eliminate signal reflection caused by through-holevias, which create multilayer stubs. Examples of blind, buried, and traditional vias are shown in Figure 8.

Figure 8. Cross-Sectional View of Blind, Buried, and Traditional Vias

Via sizing is another critical aspect to consider in all PCB designs. A good TWL1200 board design uses apad size of 250 µm and a hole size of 75 µm when routing from layer 1 to layer 2. Similarly, vias routedfrom layer 2 to layer 3 or layer 3 to layer 4 should use a pad size of 150 µm and a hole size of 75 µm.Proper via sizing for different layer routes underneath the TWL1200 ball grid array package outline isshown in Figure 9.

Figure 9. 250-µm and 150-µm Via Sizing for TWL1200 and WL1271/3 Pads

This rule also applies for vias outside of the TWL1200 package outline, except that the via pad size shouldbe increased to 275 µm.

TWL1200 PCB Design Guidelines8 SCEA042–July 2009Submit Documentation Feedback

2.4 Power Supply Bypassingwww.ti.com Layout and Design Guidelines

Proper power supply bypassing must always be practiced to decouple unwanted noise from localintegrated circuits (ICs). This is typically accomplished by placing low equivalent series resistance (ESR)capacitors as close to the power supply pins of a given IC as PCB real estate allows. Low ESR capacitorsguarantee that an ideal low-impedance bypass to ground is available for efficient decoupling ofhigh-frequency power-supply noise. Although many types of capacitors are available, low ESR ceramiccapacitors appear to be the dominant choice nowadays. Other materials, such as tantalum, offeralternatives to ceramics and may be viable depending on application needs. It is always best to considersize, cost, ESR, and maximum voltage tolerance before proceeding with design implementation.

For decoupling needs, it is equally important to look at desired capacitance. The critical point to rememberis that higher capacitance effectively decouples lower frequencies and lower capacitance achieves thesame for higher frequencies. Thus, best practice dictates that small banks of different capacitor values beused across the PCB. Generally, 1-µF to 10-µF capacitors should be placed at the outputs of voltageregulators and at any connectors where external power is supplied to the PCB. Similarly, 0.1-µF to0.01-µF capacitors should be connected to all IC power pins to facilitate effective bypassing. Viaconnections made to any of these capacitor terminals should always be placed in pairs of two or more toreduce equivalent series inductance (ESL). In addition, connections should be routed so that current isforced to flow across the capacitor terminals before reaching its intended destination. Componentplacement is just as crucial to stable power design. Capacitors should always be placed as close aspossible to the respective power supply pin of the device it is decoupling. Because these capacitors areseen as a local source of additional supply current for switching ICs, it is best to keep the distancebetween them as small as possible. An example of proper decoupling design for the TWL1200 is shown inFigure 10.

Figure 10. Proper TWL1200 Power Supply Decoupling

SCEA042–July 2009 TWL1200 PCB Design Guidelines 9Submit Documentation Feedback

3 TWL1200 Reference Design Schematic

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.

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G7

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E11

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H2

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J3

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K4

L3

M3

C9

C8

A8

B8

C5

C3

B2

C11

C4

D2

M2

K3

G2

F9

M6

F11

M4

L6

J1

G1

G9

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VDD_PPA_IFBT

VDD_CLASS1P5

VCC_TXBW

VCC_TXAW

VCC_RXW

VDD_DCOBT

VCC_ANAW

VCC_DCOW

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VDD_LDO_IN_CLASS1P5

VDDS

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VDD_LDO_INBT

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TP

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SP

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SD

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SD

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S232_T

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WL_R

S232_R

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LM

XTA

LP

SLO

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EQ

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CLK

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EQ

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UT

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BT

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C1

BT

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C2

BT

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UN

C6

BT

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UN

C5

BT

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UN

C4

BT

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UN

C7

TE

ST

MB

T

TE

ST

PB

T

FM

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S_F

SY

NC

FM

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FM

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FM

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O

FM

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CL

FM

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Q

FM

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DA

N.C.

VSS_DIG

VSS_DIG

VSS_DIG

VSS_DIG

VSS_DIG

VSS_DCOBT

VSSARFFM

VSSAADCPLLFM

VSS_XTAL

VSSAPASYNTHFM

1271 S

OC

WS

P P

G 2

.0

H3VSS_DIG

B6VSS_ANAW

M1PMS_TEST_1P8V A7

K11

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PW

PD

ET

DR

PW

PA

BC

DC

_R

EQ

L1

F3

H4

G5

J2

E4

D4

F2

D5

F1

C1

B1

A2

A3

A4

A5

K7

M8

M7

J7

F8

H11

F7

F6

G4

F4

H9

H7

H10

B7

C6

C7

D6

M11

D3

A9

K1VDD_MEM_LDO

VDD

VDD

VDD

VDD

VDD

VDD

VIN_DIG_LDO

VDD_DIG_LDO

VDD

PMS_VBAT

U2

1271F

E-T

QM

679002-E

2

RX

BP

RX

BN

TX

B

PA

BC

PDET

BT

GND

GND

GND

SW

0

SW

1

SW

2

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VBAT

VBAT

VBAT

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15

16

17

8

3

2

17

14

12

11

10

13

9

6

5

4

C121uF

C111uF

C161uF

C81uF

C71uF

C151uF

C21

1uF

C171uF

C261uF

C300.1

uF

C310.1

uF

VC

CA

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VC

CB

_1V

8

BT

_U

AR

T_R

TS

(A)

C4

TW

L1200

D4

E1

E7

CLK

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EQ

(B)

CLK

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EQ

(A)

VC

CA

VC

CA

VC

CB

VC

CB

D5

C5

F3

F5

AU

DIO

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(B)

AU

DIO

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(A)

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DIO

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LK

(A)

AU

DIO

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LK

(B)

A5

A3

B3

B5

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N(A

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AU

D_D

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4

AU

DIO

_O

UT

(A)

AU

DIO

_O

UT

(B)

G5

G3

E2

E6

BT

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N(B

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BT

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N(A

)

BT

_U

AR

T_C

TS

(A)

BT

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AR

T_C

TS

(B)

F7

F1

F2

F6

BT

_U

AR

T_R

TS

(B)

BT

_U

AR

T_R

TS

(A)

BT

_U

AR

T_R

X(A

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BT

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AR

T_R

X(B

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7

G1

G2

G6

BT

_U

AR

T_T

X(B

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BT

_U

AR

T_T

X(A

)

OE

B4

SD

IO_C

LK

(A)

SD

IO_C

LK

(B)

A7

A1

A2

A6

SD

IO_C

MD

(B)

SD

IO_C

MD

(A)

SD

IO_D

ATA

0(A

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2

C2

SD

IO_D

ATA

1(A

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ATA

2(A

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DIO

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ATA

3(A

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SD

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7S

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ATA

2(B

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7S

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ATA

1(B

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6

B6

SD

IO_D

ATA

0(B

)

SLO

W_C

LK

(A)

SLO

W_C

LK

(B)

F4

G4

D1

D6

WLA

N_E

N(B

)

WLA

N_E

N(A

)

WLA

N_IR

Q(A

)D

7

D2

E3

D3

GN

D

GN

D

WLA

N_IR

Q(B

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GN

D

GN

D

E4

E5

RX

BP

- RX

BN

:100ohm

diffe

rentia

l sig

nals

Pre

limin

ary

- su

bje

ct to

ch

an

ge.

outp

ut

input

0v -

1.9

2v

GN

D

0.2

v -

1.1

95v

VIO

Xta

l

Dig

ital C

LK

AC

couple

d

XTA

LP

(D7)

XTA

LM

(D8)

Fast C

lock

Mode

Gro

un

d c

on

ne

ctio

n o

n s

olid

gro

un

d la

ye

r on

ly

1- S

DIO

lines s

hould

be h

eld

hig

h b

y th

e h

ost.

2- If w

SP

I is u

sed, S

DIO

_D

1 a

nd S

DIO

_D

2 s

hould

be g

rou

nded

3- C

LK

_R

EQ

_O

UT

should

be h

eld

low

by th

e h

ost (W

ired-O

R ,a

ctive

hig

h).

if not u

sed a

nd p

ush-p

ull c

onfig

ura

tion n

ot u

se

d, tie

toV

IO

4- C

LK

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EQ

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UT

_n is

Wire

d A

ND

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low

, not u

sed

in th

e re

f des h

ence tie

to G

ND

.

if a p

ush p

ull c

onfig

ura

tion is

used th

e s

ignal

should

be p

ulle

d b

y th

e h

ost

5-

VD

D_LD

O_IN

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LA

SS

1P

5 c

an b

e c

onnecte

d to

1V

8 fo

r reduced p

ow

er c

onsum

ptio

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gT

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that m

axim

um

outp

ut p

ow

er w

ill be lo

we

r than w

ithV

bat

PG

2.0

PG

1.1

1uF

0.1

uF

0.2

2uF

1uF

1nF

N.C

.

C21 C3

C4

FE

RF

MD

RF

3482

ES

1.5

TriQ

TQ

M679002

PG

2.0

** Filte

r sele

ctio

n a

s w

ell a

s A

nte

nna is

a c

usto

me

r decis

ion.

The p

arts

sele

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d h

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d a

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xam

ple

only.

TWL1200 Reference Design Schematic www.ti.com

A reference schematic for the TWL1200 design is shown in Figure 11.

Figure 11. TWL1200 Reference Design

10 TWL1200 PCB Design Guidelines SCEA042–July 2009Submit Documentation Feedback

4 References

www.ti.com References

1. WiLink 6.0 PCB Design Guidelines (SWAA043)

2. Simultaneous Switching Performance of TI Logic Devices (SZZA038)

3. The Bypass Capacitor in High-Speed Environments (SCBA007)

4. TWL1200 (SDIO, UART, and Audio Voltage Translation Transceiver) data sheet (SCES786)

5. WL1271/3 (WiLink 6.0 Single-Chip WLAN/BT/FM Device) data sheet (SWAS017)

6. High-Speed Digital Design: A Handbook of Black Magic (Johnson, Howard W., 1993)

SCEA042–July 2009 TWL1200 PCB Design Guidelines 11Submit Documentation Feedback

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