tutorial 2 x-treme efficiency power electronics · load efficiency > 2000 mostly voluntary...

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X-treme Efficiency Power Electronics J. W. Kolar Swiss Federal Institute of Technology (ETH) Zurich Power Electronic Systems Laboratory www.pes.ee.ethz.ch

Tutorial 2

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Deep Green Power Electronics J. W. Kolar Swiss Federal Institute of Technology (ETH) Zurich Power Electronic Systems Laboratory www.pes.ee.ethz.ch

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Outline

► Trends of Efficiency Improvement ► Converter Loss Components ► Efficiency Improvement by * Design * Control * Topology & Control ► Highly Accurate Efficiency Measurement ► η > 99% Converter Demonstrators ► Conclusions

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Power Electronics Performance Trends

─ Power Density [kW/dm3] ─ Power per Unit Weight [kW/kg] ─ Relative Costs [kW/$] ─ Relative Losses [%] ─ Failure Rate [h-1]

■ Performance Indices ►

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Drivers for High Efficiency

< 2000 Increase of Power Density / Thermal Limitation / Max. Full Load Efficiency > 2000 Mostly Voluntary Efficiency Requirements for Entire Power Range (100%, 50%, 20%)

► ►

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Efficiency / Power Factor Limits (5%)…20%...100% Load

►

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Inefficiency (Losses)…

─ PV Inverters: Typ. Loss Reduction of Factor 2 over 5 Years

General Efficiency Trends

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Efficiency Basics

Converter Loss Components Efficiency Maximum

Efficiency vs. Power Factor

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Non-Idealities of Converter Circuits

2 2 21, 2 2 ( ) 22( ) ( ) (1 ) ( (1 ) )

V aux E eq P F P P L DS onP P C U f U k f I D R DR D D ESR I ►

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Non-Idealities of Converter Circuits

► 2,0 , , 0 2 2V V V I V II I II

P P P P k k P k P

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2

1 2

2

1 11

V

V

PP

PP P

P

Influence of Loss Components on Efficiency Characteristic

2,0 , , 0 2 2V V V I V II I II

P P P P k k P k P

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2

1 2

2

1 11

V

V

PP

PP P

P


2,0 , , 0 2 2V V V I V II I II

P P P P k k P k P

00

,0 0 2

22

1 1 111 V

k

P k P

PP

► Only Constant Losses

►

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2

1 2

2

1 11

V

V

PP

PP P

P


2,0 , , 0 2 2V V V I V II I II

P P P P k k P k P

► Only Power Proportional Losses

,

2

1 1 1 .11

I IV I I

k constP k

P

►

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2

1 2

2

1 11

V

V

PP

PP P

P


2,0 , , 0 2 2V V V I V II I II

P P P P k k P k P

► Quadratically Power Dependent Losses

2, 2

2

1 1 111

II IIV II II

k PP k P

P

►

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2

1 2

2

1 11

V

V

PP

PP P

P

Efficiency Maximum

@ Maximum: Equal Constant and Quadratic Losses , , max ,0V II VP P

►

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Efficiency vs. Power Factor

2, 1

1 1 1,(1)

1 1cos

V Ri i

i

P I R

P U I

► Sensible Compromise e.g. for Three-Phase Systems

21(1 )

cosi

i

THDr

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Measures for Efficiency Improvement

Design - Power Semiconductors - Inductive Components / EMI-Filter - Auxiliaries

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Power Semiconductors

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► On-State Losses ► Capacitive Switching Losses

GS iss rss

GD rss

DS oss rss

C C C

C C

C C C

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► On-State Losses ► Capacitive Switching Losses

2 2, , ( ) , 2 2

1 ( )2V T DS rms DS on E eq P

P I R C U U f

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*( )

( )

*, ,

DS on

DS on

Si

E eq E eq Si

RR

A

C C A

,1

V T C P Si P

Si

P A fA

► Silicon Area Related Resistance / Capacitance ►

►

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*( )

( )

*, ,

DS on

DS on

Si

E eq E eq Si

RR

A

C C A

► Optimum Silicon Area - Minimum Losses ►

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Power Semiconductors - Efficiency Barrier

*( )

( )

*, ,

DS on

DS on

Si

E eq E eq Si

RR

A

C C A

* *, ,min 2 ( ) ,

12 2V T C P P rms P DS on E eq

P f I U f R CFOM

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► Selection of ASi > ASi,opt Leads to Lower Efficiency in Whole Operating Range

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Inductive Components / EMI Filter

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Inductive Components – Efficiency vs. Volume

2

1 1d

E P E E

UL iB

NA f A A l

3, 2

1 1( )V E P E

P f B V ll l

2, 2

1V W rms W

W

l lP I R

A l l

► Iron and Copper Losses are Decreasing with Increasing Linear Dimensions

- Iron Losses

- Copper Losses

4

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Selection of the Switching Frequency

► Example of Single-Phase PFC Rectifier Systems

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ˆN

d

UM

U

2 2,( ) ,( )

ˆ ˆT n T n

U U U U 2 21 1

,(2 ) ,(2 )2 4ˆ ˆ

T n T nU U U U

- Consider Boost Inductor as Part of EMI Filter - Calculate Equivalent Noise Voltage @ Switching Frequency

Limited Influence of Higher Order Harmonics

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ˆN

d

UM

U

2 2 2, , , ,Pf eq rms T rms N rms

U U U , ,2( )

2Pf eq rms d

MU M U


- Consider Boost Inductor as Part of EMI Filter - Calculate Equivalent Noise Voltage @ Switching Frequency

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► Equivalent Noise Voltage @ Switching Frequency

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Required EMI Filter Attenuation

► Higher Switching Frequency Increases Required Attenuation

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Required EMI Filter Attenuation

► Higher Switching Frequency Increases Required Attenuation

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Minimize Required EMI Filter Attenuation

► Distribute Harmonic Power Equal over Frequency Range

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EMI Filter Optimization

4 2 2

1(1 )F

Gk k L C

0.5opt

k

► Equal Partitioning of Total Inductance Provides Max. Attenuation

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212

212

C C C

L L L

V CU k C

V LI k L

(1 )C

L

V rV

V r V

2(1 )

L C

r rLC V Max

k k

0.5optr

► Equal Partitioning of Total Volume between L & C Provides Max. Attenuation

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► Impact of Switching Frequency and Ripple Ratio on Volume

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► Impact of Switching Frequency and Ripple Ratio on Volume (PN=1.5kW)

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► Optimization for Minimum Losses at Given Maximum Filter Volume

► Optimum Values ki and fP are Close to Volume Optimal Design

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Control - Intermittent Operation - Interleaving

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Intermittent Operation

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Intermittent Operation

► Operate Converter ONLY at Maximum Efficiency Power Level

► Adjust Delivered Power by Proper Selection of the Duty Cycle

max

2,

2, max

avgon

rep

PT

T P

► Energy Storage Requirement !

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Parallel Interleaving

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Mechanical Version of “Parallel Interleaving”

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Parallel Operation of Multiple Sub-Systems

► Features Phase-Shedding (Equivalent to Adjustable Silicon Area!) ► Features Cancellation of Harmonics

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Parallel Operation of Multiple Sub-Systems

► Equal Sharing of Total Power for Minimal Losses

2, 2

2, 2(1 )a

b

P aP

P a P

0.5opt

a

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Efficiency Optimum Phase-Shedding

► Maximization of Part-Load Efficiency

1 12, 2,1sw swN N

P P

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Efficiency Optimum Phase-Shedding

► Deactivation of “Cylinders”

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► Operation of n =2 Systems 180° Out of Phase

Ripple Cancellation

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Ripple Cancellation

max, 2ˆ

32d

n

P

Ui

f L

max, 1

ˆ8

d

n

P

Ui

f L

► Possible Red. of Input Capacitance C → C/8 –or– Inductance 2L → L/4

►

Doubling of Effective Switching Frequ. @ Same

Switching Losses

►

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Scaling Laws of Parallel Interleaving

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► Parallel Interleaving (Homogeneous Power)

■ Characteristics

■ Fully Benefits from Digital IC Technology (Improving in Future) ■ Redundancy Allows Large Number of Units without Impairing Reliability

─ Breaks the Frequency Barrier ─ Breaks the Impedance Barrier ─ Breaks Cost Barrier - Standardization ─ High Part Load Efficiency

H. Ertl, 2003

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─ Multiplies Frequ. / Red. Ripple @ Same (!) Switching Losses & Incr. Control Dynamics

■ Fully Benefits from Digital IC Technology (Improving in Future) ■ Redundancy Allows Large Number of Units without Impairing Reliability

H. Ertl, 2003

! !

N = 3

► Parallel Interleaving (Homogeneous Power)

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Minimum Volume for 100% Current Ripple (DCM)

► Remark #1 Volume of Cell-Inductors

■ Harmonics Cancellation Allows Large ripple of Cell Currents

►

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■ Allowed Ls Directly Related to Switching Time ts i i

s sL L

Zs

U UL t

I I

t

Parallel Interl. Allows to Split-Up Large Currents Increase of Z / Allows Faster Swtchg

► Remark #2 Impedance Matching

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► Remark #3 Efficiency/Power Density (Pareto) Limit

■ Parallel Interleaving - Shift of the Pareto Limit Higher Power Densities

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EMI Reduction due to Parallel Interleaving

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Reduction of EMI Filter Volume

► Symm. Interleaving – 180° ► Asymm. Interleaving – 90°

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Topology & Control - Single-Stage vs. Two-Stage Conversion - Synchronous Rectification - Resonant Transition Mode Switching - Interleaving

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Single-Stage vs. Two-Stage Conversion

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► Single-Stage Integration of Functions ─ Examples: * Matrix Converters * Multi-Functional Utilization (Machine as Inductor of DC/DC Conv.) * etc.

■ Integration Restricts Controllability / Overall Functionality (!) ■ Typ. Lower Efficiency / Higher Control Compl. of Integr. Solution ■ Basic Physical Properties remain Unchanged (e.g. Filtering Effort)

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■ Highly Optimized Specific Functionality High Performance for Specific Task ■ Restriction of Functionality Lower Costs

■ Example of Wide Input Voltage Range Isolated DC/DC Converter

► Two-Stage Optimal Splitting of Functionality

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■ Resonant Frequ. ≈ Switching Frequ. Input/Output Voltage Ratio = N1/N2

─ Example: DC-Transformer Isolation @ Constant (Load Ind.) Voltage Transfer Ratio

E.g. adopted by VICOR – “Sine Amplitude Converter” for Fact. Power Architecture Very High Efficiency

► Two-Stage Optimal Splitting of Functionality

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Resonant Transition Mode

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Technological Limits of Hard-Switched CCM Converters

► On-State Voltage of Freewheeling Diodes (UF) ► Capacitive Switching Losses of MOSFETs (ASi,opt)

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■ Synchronous Rectification ■ Negative Current Ensures ZVS

Zero Voltage Switching – Triangular Current Mode (TCM) Operation

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Zero Voltage Switching – Triangular Current Mode (TCM) Operation

■ Synchronous Rectification ■ Negative Current Ensures ZVS

►

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12kW TCM Buck+Boost DC/DC Converter

► Overlapping Input and Output Voltage Ranges U1=150…450V U2=150…450V

► Max. Eff. = 99.3% @ 30kW/l

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■ Instead of Adding Aux. Circuits Change Operation of BASIC (!) Structure – “Natural” Performance Limit

99.3% Efficiency 30 kW/dm3

”Snubbers” vs. TCM

─ Non-Isolated Buck+Boost DC-DC Converter for Automotive Applications

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Further Concepts - Partial Power Conversion - Ride-Through Boost Converter - Series/Parallel Rearrangement

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Partial Power

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Partial Power Converter

► Reduces Rated Power of PPC

► Limited Influence of PPC Efficiency on Total Efficiency

2 1 cU U U

2

2

,1

1 1

c

c

U

Uc

c U

U

Pp

P

2

2

2

1

(1 )(1 )

c

c

U

U c

U

U

P

P

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Voltage / Topology Preconditioning

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► Voltage / Topology Preconditioning

► Ride-Through Boost Converter

► Series-Parallel Reconfiguration (Voltage:2 AND Current x2 Advantage Comp. to Multi-Level Conv.)

■ S/P Reconfiguration also Applicable for 3-Phase System (Star Delta Rearrangement)

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* Conventional

* ISOP = Input Series / Output Parallel Topology

● Low Inp. Voltage / Output Curr. Harmonics ● Low Input / Output Filter Requirement ● Impedance Matching

■ Numerous Combinations (ISOP, ISIS, IPOS, IPOP, etc.)

* Input Series

► Mixed Interleaving

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Highly Accurate Efficiency Measurement

Concepts - Power Analyzer - Calorimeter

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Power Analyzer

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Maximum Admissible Power Measurement Error

2P

2

1

P

P

1

(1 )VP

P

(1 )V

2(1 )V P

► Admissible Error of Loss Determination NOT Efficiency Determination

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Calorimeter

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Two-Chamber Calorimeter

► Relative Error of Loss Measurements < 3.5%@10W < 1.0%@100W < 0.5%@200W

► Measurements up to 85°C Ambient Temp.

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Ultra-High Efficiency Converters

Concepts - 2x Interleaved CCM Bridgeless PFC Rectifier @ 3.3kW - 6x Interleaved TCM PFC Rectifier - Telecom Rectifier Module

Research Projects of ETH Zurich Partly Supported

by the European Center for Power Electronics

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3.3kW CCM PFC Rectifier System

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99.36% @ 1.2kW/dm3

■ Bidirectional – Supports V2G Concepts ■ Employs NO SiC Power Semiconductors -- Si SJ MOSFETs only

3.3kW TCM PFC Rectifier System

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► Measurement Results

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99.36% @ 1.2kW/dm3

► Employs NO SiC Power Semiconductors -- Si SJ MOSFETs only

230 Vrms


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97.0

97.2

97.4

97.6

97.8

98.0

98.2

98.4

98.6

98.8

99.0

1000 1500 2000 2500 3000 3500

P O /W

/%

264V230V184VLimit

98.6% @ 4.5kW/dm3

Ultra-Compact/Efficient TCM PFC Rectifier System • Input Voltage 184…264VAC • Output Voltage 420VDC • Rated Power 3.3kW

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Converter Performance Evaluation Based on η-ρ-Pareto Front

►

Triple-Interleaved TCM Rectifier (56kHz)

Double-Interleaved Double-Boost CCM Rectifier (450kHz)



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KEYS for Achieving the Performance Improvement

… despite Using “Old” Si Technology

■ Only Basic Topology Employed – Low Complexity ■ ZVS Achieved by Only Modifying Operation Mode – No Aux. Circuits ■ Active ZVS – No (Low) Switching Losses – No Direct Limit of # of Parallel Trans. ■ Triangular Current Mode (TCM) – Simple Symm. of Loading of Modules – No Current Sensor (only i=0 Detection) ■ Variable Switching Frequency – Spread & Lower Ampl. EMI Noise ■ No Diode On-State Voltage Drop – Synchr. Rectification ■ Continuously Guided u, i Waveforms – No Free Ringing Low EMI Filter Vol. ■ Interleaving – Low EMI Filter Vol. & Cap. Curr. Stress ■ Utilization of Low Superjunct. RDS,(on) – Low Cond. Losses despite TCM ■ Utilization of Digital Signal Processing – Low Control Effort despite 6x Interl.

… the Basic Concept is Known since 1989 (!)

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Alternative Converter Concepts (?)

■ Minimum Performance Difference for Best Matching of Topology/Semicond./Modulation ■ Only Use BASIC Topologies - Costs are THE Deciding Criteria (!)

Source:

Dr. Gerald Deboy Plenary Presentation @

IECON 2013, Vienna

─ Indication for a “Natural” Performance Limit

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► Is Another Step of Massive Improvement Possible ?

►




Triple-Interleaved TCM Rectifier (33kHz) 99% @ 6kW/dm3

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Multi-Cell Approach Series Interleaving

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Telecom Rectifier Employing Series Multi-Cell Approach

■ Input Series Output Parallel (ISOP) Connection

■ Specifications Input Voltage 230 Vrms (180 Vrms – 270 Vrms) Nominal Output Voltage 48 VDC Output Voltage Range 40-60 VDC Rated Power 3.3 kW Target Efficiency 98.5% Target Power Density 3 kW/dm3

Hold-Up Time 10ms at Rated Power Switching Frequency ≥20 kHz (per Module) EMI Standard CISPR Class A and Class B

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► First Optimization Results

■ Calculation of Opt. Maximum Admissible DC-Link Voltage Drop during Hold-Up Time (10ms) ■ Pareto-Optimal for N = 6 Cells (PFC Rectifier + Phase-Shift Full-Bridge)

■ Optimal Performance for 20% Hold-up DC-Link Voltage Drop

10%

20%

30%

40%

98% @ 3kW/dm3

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“Conventional” 3.3kW Telecom Rectifier Module

► 3x Interleaved TCM PFC Rectifier Stages ► Full-Bridge Phase-Shift DC/DC Converter / Full Bridge Synchr. Rectifier

96.8% @ 2.5kW/dm3

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Next Gen. “Conventional” 3.3kW Telecom Rectifier Module

► 3x Interleaved TCM PFC Rectifier Stages ► 2x Interleaved Full-Bridge Phase-Shift DC/DC Conv. / Full-Bridge Synchr. Rectifier

97% @ 3.3kW/dm3

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Scaling Laws of Series Interleaving

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■ Characteristics ─ Breaks the Frequency Barrier ─ Breaks the Silicon Limit 1+1=2 NOT 4 (!) ─ Breaks Cost Barrier - Standardization ─ Extends LV Technology to HV

H. Ertl, 2003

Series Interleaving of Converter Cells

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■ Excellent Opportunity for Extreme Efficiency Ultra-Compact Converters

■ Series Interleaving of LV MOSFETs (LV Cells) Effectively SHIFTS the Si-Limit (!)

DS,on eff DS,on1 5

1( ) ( ).

R A R AN

► ►

– Scaling of Specific On-State Resistance

Assumption: Chip Area of each LV Chip Equal to the Chip Area of the HV Chip

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■ Interleaved Series Connection Dramatically Reduces Switching Losses (or Harmonics)

■ Converter Cells Could Operate at VERY Low Switching Frequency (e.g. 5kHz) ■ Minimization of Passives (Filter Components)

S,N S,N= 1 2 3

1 1 ( )2

P P ...N N

– Scaling of Switching Losses for Equal Δi/I and dv/dt

Sp

t t t

ttt

►

1N

t

t


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Remarks on Performance Indices

Couplings & Limits

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► Power Electronics Converters Performance Indices

─ Power Density [kW/dm3] ─ Power per Unit Weight [kW/kg] ─ Relative Costs [kW/$] ─ Relative Losses [%] ─ Failure Rate [h-1]

■ Performance Indices

[kgFe /kW] [kgCu /kW] [kgAl /kW] [cm2

Si /kW]

►

►

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► Design Challenge

■ Mutual Couplings of Performance Indices Trade-Offs

─ For Optimized System Several Performance Indices Cannot be Improved Simultaneously

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► Mapping of Design Space into System Performance Space

Abstraction of Power Converter Design

Performance Space

Design Space

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Mathematical Modeling and Optimization of Converter Design

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■ Identifies Performance Limits Pareto Front

─ Sensitivities to Technology Advancements (Example: η-ρ-Pareto Front) ─ Trade-off Analysis

Multi-Objective Optimization

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► Analysis of Performance Limits Pareto Front

■ Clarifies Influence of Main Components and Operating Parameters

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► η-ρ-σ-Pareto Surface

■ σ: kW/$

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Efficiency vs. Power Density

► FOM = Ratio of Relative Losses and Power Density

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Observation

► Very Limited Room for Further Performance Improvement !

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Efficiency Power Density

Observation

► Very Limited Room for Further Performance Improvement !

■ General Challenge in Power Electronics ■ Cost Models are Becoming Mandatory – Even for University Research(!)

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Conclusions

► No Magic New Topology ► Technological Limits (Magnetics!) ► Light-Load Efficiency → Ohmic Characteristics / ZVS / Interleaving ! ► Modern Semiconductor Technology ► Modern Digital Control Technology ► System Oriented Analysis → Architecture & Energy Management ► Adv. Packaging & Thermal Manag. for High Eff. AND Power Density

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Questions

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References

F. Krismer Y. Lobsiger J. Mühlethaler Th. Nussbaumer J. Miniböck M. Kasper

J. W. Kolar, F. Krismer, Y. Lobsiger, J. Mühlethaler, T. Nussbaumer, J. Miniböck, Extreme Efficiency Power Electronics, Proc. of International Conf. of Integrated Power Electronics Systems (CIPS), Nuremberg, Germany, March 6-8, 2012. U. Badstuebner, J. Miniböck, J. W. Kolar, Experimental Verification of the Efficiency/Power-Density (n-p) Pareto Front of Single-Phase Double-Boost and TCM PFC Rectifier Systems, Proc. of 28th IEEE Applied Power Electronics Conf. (APEC), Long Beach, California, USA, March 17-21, 2013.

Acknowledgement

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About the Instructor Johann W. Kolar (F´10) received his M.Sc. and Ph.D. degree (summa cum laude / promotio sub auspiciis praesidentis rei publicae) from the University of Technology Vienna, Austria. Since 1984 he has been working as an independent international consultant in close collaboration with the University of Technology Vienna, in the fields of power electronics, industrial electronics and high performance drives. He has proposed numerous novel converter topologies and modulation/control concepts, e.g., the VIENNA Rectifier, the SWISS Rectifier, the Delta-Switch Rectifier, the isolated Y-Matrix AC/DC Converter and the three-phase AC-AC Sparse Matrix Converter. Dr. Kolar has published over 450 scientific papers at main international conferences, over 180 papers in international journals, and 2 book chapters. Furthermore, he has filed more than 110 patents. He was appointed Assoc. Professor and Head of the Power Electronic Systems Laboratory at the Swiss Federal Institute of Technology (ETH) Zurich on Feb. 1, 2001, and was promoted to the rank of Full Prof. in 2004. Since 2001 he has supervised over 60 Ph.D. students and PostDocs. The focus of his current research is on AC-AC and AC-DC converter topologies with low effects on the mains, e.g. for data centers, More-Electric-Aircraft and distributed renewable energy systems, and on Solid-State Transformers for Smart Microgrid Systems. Further main research areas are the realization of ultra-compact and ultra-efficient converter modules employing latest power semiconductor technology (SiC and GaN), micro power electronics and/or Power Supplies on Chip, multi-domain/scale modeling/simulation and multi-objective optimization, physical model-based lifetime prediction, pulsed power, and ultra-high speed and bearingless motors. He has been appointed an IEEE Distinguished Lecturer by the IEEE Power Electronics Society in 2011. He received 9 IEEE Transactions Prize Paper Awards, 8 IEEE Conference Prize Paper Awards, the PCIM Europe Conference Prize Paper Award 2013 and the SEMIKRON Innovation Award 2014. Furthermore, he received the ETH Zurich Golden Owl Award 2011 for Excellence in Teaching and an Erskine Fellowship from the University of Canterbury, New Zealand, in 2003. He initiated and/or is the founder/co-founder of 4 spin-off companies targeting ultra-high speed drives, multi-domain/level simulation, ultra-compact/efficient converter systems and pulsed power/electronic energy processing. In 2006, the European Power Supplies Manufacturers Association (EPSMA) awarded the Power Electronics Systems Laboratory of ETH Zurich as the leading academic research institution in Power Electronics in Europe. Dr. Kolar is a Fellow of the IEEE and a Member of the IEEJ and of International Steering Committees and Technical Program Committees of numerous international conferences in the field (e.g. Director of the Power Quality Branch of the International Conference on Power Conversion and Intelligent Motion). He is the founding Chairman of the IEEE PELS Austria and Switzerland Chapter and Chairman of the Education Chapter of the EPE Association. From 1997 through 2000 he has been serving as an Associate Editor of the IEEE Transactions on Industrial Electronics and from 2001 through 2013 as an Associate Editor of the IEEE Transactions on Power Electronics. Since 2002 he also is an Associate Editor of the Journal of Power Electronics of the Korean Institute of Power Electronics and a member of the Editorial Advisory Board of the IEEJ Transactions on Electrical and Electronic Engineering.

tutorial 2 x-treme efficiency power electronics · load efficiency > 2000 mostly voluntary...

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