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Post-CMOS Grand ChallengesPost-CMOS Grand Challenges

Juri Matisoo

Vice-President, Technology

Semiconductor Industry Association

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AcknowledgementsAcknowledgements

SIA TSC Working Group Bob Doering, TI, Chair; George Bourianoff, Intel Philip Wong, IBM Luan Tran, Micron Papu Maniar, Motorola Jim Hutchby, SRC

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Agenda/OverviewAgenda/Overview

Value and Need for Investment in Nanoelectronics* Research

Long-Term Manufacturing Research

Long-Term Device Research

Recommendations Summary

* In this presentation: “nanoelectronics” ≡ “future IC technology”

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Benefits to the U.S.Benefits to the U.S.from the Semiconductor Industryfrom the Semiconductor Industry

Powers other Industries

Spurs Economic Growth

~3% of GDP growth due to “computer quality” increase

Creates High-Wage Jobs

~300K jobs in the U.S. currently

Fosters International Competitive Advantage

Bolsters National Defense/Homeland Security

Intelligence gathering/processing

Guidance/Control systems (e.g., for E2C2)

Logistics management/efficiency

Communications Technology

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The Need for New EnablersThe Need for New Enablersof Progress in Future ICsof Progress in Future ICs

The industry productivity gains of 25%/year reduction in cost/function and improved performance and reduced power consumption over the last 40 years have been driven by miniaturization of semiconductor devices.

The International Technology Roadmap for Semiconductors (ITRS) predicts that over the next 10-15 years, this trend will end.

New devices and manufacturing techniques are needed.

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Long-Range Grand ChallengesLong-Range Grand Challenges

In the long term, the SIA TSC feels that we face two grand challenges worthy of very large federal funding:

(1) Scaling limits of “evolutionary lithography/thin-film manufacturing”

(2) Scaling limits of “charge-transport devices/interconnect”

We suggest that these might be overcome through new and synergistic research in the under-funded broad areas of:

(1) “Directed self-assembly” of complex structures with “nanoelectronics-functionality” (computation, comm., etc.)

(2) “Beyond (classical) charge transport” signal-processing/ computational technology (e.g., based on quantum-states)

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Rationale for Directed Self-AssemblyRationale for Directed Self-Assembly

Break the manufacturing “scaling tyranny” of:

(1) Maintaining adequate process-control margin

(2) Contamination-density-limited yield

(3) Escalating wafer-fab capital cost

(4) Lengthening production cycle time

(5) Rapidly increasing photomask cost

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Desired ConsequencesDesired Consequencesof Directed Self-Assemblyof Directed Self-Assembly

(1) Approaching “atomic-level” perfection/control in manufacturing of nano-systems (“future SOCs”)

(2) Providing radically enhanced and affordable functionality in nano-systems

(3) Revolutionizing fab economics and logistics

(4) Application to a broad range of devices (e.g., from “ultimate CMOS” to “quantum-state”)

Note: the principal barrier to implementation of advanced device concepts is often “manufacturing feasibility”

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Current Examples of Self-Assembly TechniquesCurrent Examples of Self-Assembly Techniques

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The Self-Assembly “Place and Route” ProblemThe Self-Assembly “Place and Route” Problem

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IC Metrics that Should Guide ResearchIC Metrics that Should Guide Researchon NanoManufacturingon NanoManufacturingIC Metrics that Should Guide ResearchIC Metrics that Should Guide Researchon NanoManufacturingon NanoManufacturing

Cost/Integrated-Function (e.g., $/gate or $/bit integrated into system)

Operations/Second (computation speed, e.g. MIPS)

Power Dissipation (both operating and standby power)

Integration Density (e.g., integrated functions/cm2 or /cm3)

Integration Diversity (SOC functions - e.g., analog, RF, e-RAM)

Capital Cost/Capacity (e.g., capital investment $/chips/month)

Mfg. Cycle Time (impacts time-to-market and ASIC delivery)

R&D Cost (e.g., cost per new product or tech node)

NanoManufacturing Goals: 100x beyond limits of the evolutionary approach

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Rationale for Beyond-Charge-TransportRationale for Beyond-Charge-TransportSignal-Processing/ComputationSignal-Processing/Computation

Break the “CMOS electrical scaling tyranny,” e.g.:

(1) Voltage (limiting speed/power/error-rate tradeoff)

(2) Resistance (limiting speed and low power)

(3) Capacitance (limiting speed and low active power)

(4) Charge-Leakage Mechanisms (limiting standby power)

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Desired ConsequencesDesired Consequencesof Beyond-Charge-Transportof Beyond-Charge-TransportComputation/Signal-ProcessingComputation/Signal-Processing

(1) Providing significant performance improvements via mechanisms beyond merely scaling physical dimensions (e.g., multiple logic states, far-from-equilibrium operation)

(2) Providing qualitatively new types of nano-system functionality (e.g., direct sensing/actuating)

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Some Potential Some Potential State VariablesState VariablesAlternative to Classical Electric ChargeAlternative to Classical Electric Charge

Atomic/molecular quantum states (including “artificial atoms”)

Magnetic-dipole magnitude/orientation (e.g., electron/nuclear spin)

Electric-dipole magnitude/orientation

Magnetic flux quanta

Photon number

Photon polarization

Mechanical state

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Example: Spin-Resonance Transistor (SRT)Example: Spin-Resonance Transistor (SRT)

Transistors that control spins rather than charge

More energy efficient than conventional transistors

Combines magnetic and electrostatic fields

May enable quantum computing

Courtesy Eli Yablanovitch, UCLACourtesy Eli Yablanovitch, UCLA

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Challenges to MetrologyChallenges to Metrology

Instrumentation and techniques for Identification and visualization of atomic species

and structure Observation of short-range and long-range order,

defects Device characterization

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SummarySummary

We have identified two major challenges for nanoelectronics, worthy of significant Government funding via NNI

We presented these findings to PCAST as part of their NNI review, and strategy development