Seventh International Dielectrics and Conductors for ULSI Multilevel Interconnection Conference (DCMIC), SantaClara, CA, March 5-9, 2001, pp. 38-50.

Trends for ULSI Interconnections and Their Implications for Thermal,Reliability and Performance Issues

(Invited Paper)

Kaustav BanerjeeCenter for Integrated Systems

Stanford University, Stanford, CA 94305kaustav@stanford.edu

Abstract

This paper provides an overview of ULSIinterconnect scaling trends and their implicationsfor thermal, reliability and performance issuessimultaneously. It shows how interconnect scalingrequirements for deep sub-micron (DSM)technologies cause increasing thermal effects. Thepaper then examines the impact of thermal effectson both interconnect design and electromigration(EM) reliability. Specifically, it discusses theimpact of thermal effects on the allowable currentdensity limits. Furthermore, it also discusses howthermal and reliability constrained current densitylimits may conflict with those obtained throughpurely performance based criterion. Additionally,high-current interconnect design rules for ESD andI/O circuits are also examined.

1 Introduction

As VLSI technology scales, interconnects arebecoming the dominant factor determining systemperformance and power dissipation [1], [2], [3].The ever-increasing demand for speed andfunctionality of Si-based advanced highperformance chips has caused aggressive scaling ofICs beyond 0.25-µm minimum feature size. Thesetechnology nodes, commonly referred to as deepsub-micron, (DSM) allow VLSI circuits to meetthe required device density and various circuitperformance specifications. This trend hasresulted in a dramatic reduction of the interconnectmetal pitch and increased the number ofmetallization levels to accommodate the increasingnumber of wired circuits per chip. A schematiccross-section of a multilevel interconnect schemeis shown in Figure 1. This aggressive interconnectscaling has resulted in increasing current densitiesand associated thermal effects.

DielectricMaterial

Silicon

Metal 1

Metal 2

Metal 3

Metal 4

Metal 5

Via

Contact

W

SH

Figure 1. A schematic cross section of a multi-levelinterconnect scheme employed in present VLSI circuits.The metal pitch is defined as (W + S) and the aspectratio is defined as (H/W).

Thermal effects are an inseparable aspect ofelectrical power distribution and signaltransmission through the interconnects in VLSIcircuits due to self-heating (or Joule heating)caused by the flow of current [4]. Thermal effectsimpact interconnect design and reliability in thefollowing ways. Firstly, they limit the maximumallowable RMS current density, jRMS-max (since theRMS value of the current density is responsible forheat generation) in the interconnects, in order tolimit the temperature increase. Secondly,interconnect lifetime (reliability) which is limitedby electromigration (EM), has an exponentialdependence on the inverse metal temperature [5].Hence, temperature rise of metal interconnects dueto self-heating phenomenon can also limit themaximum allowed average current density, javg-max,since EM capability is dependent on the averagecurrent density [6]. Thirdly, thermally inducedopen circuit metal failure under short-duration highpeak currents including electrostatic discharge

(ESD) is also a reliability concern, [7] and canintroduce latent EM damage [8] that has importantreliability implications.

Additionally, low dielectric constant (low-k)materials are being introduced as an alternativeintra- and inter- level insulator to reduceinterconnect capacitance (therefore delay) andcross-talk noise to enhance circuit performance [9],[10], [11]. These materials can further exacerbatethermal effects owing to their lower thermalconductivity than silicon dioxide [12].

Furthermore, it is important to understand howthermal and reliability constraints may conflictwith the performance optimization steps employedat the circuit level. Hence, thorough analysis ofthermal effects in DSM interconnects is necessaryto comprehend their full impact on circuit design,accurately model their reliability, and providethermally safe design guidelines for varioustechnologies.

In the next sub section interconnect scalingrequirements as per [13] are examined and theirimplications for thermal effects are discussedbriefly.

1.1 Trends in Interconnect Scaling andImplications for Thermal Effects

As VLSI circuits continue to be scaledaggressively, a rapid increase in functional densityand chip size is observed as shown in Figure 2.This has resulted in increasing number ofinterconnect levels and reduction in interconnectpitch in order to realize all the inter-device andinter-block communications. Figure 3 shows thistrend with interconnect levels increasing further inthe near future, from 6 levels at the 250 nm node to9 levels at the 50 nm node. This increase in thenumber of interconnect levels causes the uppermost interconnect layers to move further awayfrom the Si substrate making heat dissipation moredifficult. Additionally, decreasing interconnectpitch will cause increased thermal coupling.Furthermore, the critical dimensions of contactsand vias are also decreasing with scaling as shownin Figure 4 resulting in higher current densities inthese structures. Compounded with theintroduction of low-k dielectrics as alternativeinsulators, whose thermal conductivities are alsomuch lower than that of silicon dioxide (Figure 5),it is envisioned that thermal effects in

interconnects can potentially become anotherserious design constraint.

0

20

40

60

80

100

120

140

160

180

200

1997 1999 2001 2003 2006 2009 2012

Year of First Product ShipmentTechnology Generations

Fun

ctio

nal D

ensi

ty

(Tra

nsis

tors

/cm

2 in

Mill

ions

)

250nm

180nm

150nm

130nm

100nm

70nm

50nm

3.0 3.4 3.854.3

5.2

6.2

7.5Chip Size (cm2)

Figure 2 Present and projected functional density andchip size of microprocessors for different technologynodes and year of first product shipment. Thefunctional density is expected to increase from 3.7million in 1997 to 180 million in 2012.

0

1

2

3

4

5

6

7

8

9

10

1997 1999 2001 2003 2006 2009 2012

Year of First Product Shipment Technology Generations

Inte

rcon

nect

Lev

els

250nm

180nm

150nm

130nm

100nm

70nm

50nm

640/590 460/420

400/360 340/300 260/240

190/170

140/130Minimum InterconnectPitch (nm)

Figure 3. Present and projected interconnect levels andminimum contacted/non-contacted interconnect metalpitch of logic circuits for different technology nodes andyear of first product shipment.

0

50

100

150

200

250

300

350

400

1997 1999 2001 2003 2006 2009 2012

Year of First Product ShipmentTechnology Generation

Min

imum

Con

tact

/Via

CD

[nm

]

250nm

180nm

150nm

130nm

100nm

70nm

50nm

Via

Contact

Figure 4. Present and projected minimum contact/viacritical dimensions (CD) of logic circuits for differenttechnology nodes and year of first product shipment.

0

0.2

0.4

0.6

0.8

1

1.2

1.4

Oxide HSQ Polyimide Air

Dielectric Material

Th

erm

al C

on

du

ctiv

ity

(W/m

0 K )

k = 3.9

k = 3.3

k = 2.2

k = 1.0

Figure 5. Thermal conductivity and approximatedielectric constants (k) of some insulating materialsused (or being introduced) in high performance circuits.

l

(a)

stVtrV

Rtr

pC

lr ⋅

lc⋅LC

(b)

Figure 6 (a) An interconnect of length l between twobuffers (b) The equivalent RC circuit. Vst is the voltageat the input capacitance that controls the voltage sourceVtr. Rtr is the driver transistor resistance, Cp is theoutput parasitic capacitance and CL is the loadcapacitance of the next stage, r and c are theinterconnect resistance and capacitance per unit lengthrespectively.

A simple analysis to demonstrate theimplications of technology scaling on technologyperformance is now presented [4]. This analysis isinstructive since these in turn have importantimplications on thermal effects and on reliabilityrequirements for interconnects. Consider aninterconnect segment of length l between twoinverters as shown in Figure 6 (a). Figure 6 (b)shows the equivalent distributed RCrepresentation. Here the inverter on the left that isdriving the interconnect is represented as a voltagesource controlled by the voltage Vst at the inputcapacitance. Rtr is the equivalent transistor

resistance, Cp is the parasitic capacitancecomposed mainly of the drain capacitance of thetransistors. CL is the load capacitance or the inputcapacitance of the second inverter. Also, c and rare the capacitance and resistance per unit lengthof the interconnect line.

Using this simple model the performance of atechnology can be most simply summarized by theoverall delay time τ for a signal, which can beexpressed as,

( ) ( ) 2LtrLptr rcl

2

1lrCcRCCR ++++=τ (1)

Rtr, Cp, and CL are functions of the transistor designand the circuit design W/L ratios used. Theinterconnect resistance per unit length, r, dependson the resistivity of the interconnect metal while cdepends on the dielectric constant of thesurrounding insulating material, interconnect metalpitch, interconnect geometry, and underlyinginsulator thickness [14]. The three terms on theright hand side of (1) represent the intrinsic gatedelay, the load delay, and the interconnect delaycontributions, respectively. The factor of half inthe interconnect delay arises due to the distributednature of the interconnect. A more generalexpression for τ will be provided later.

Now if s is the scaling parameter, which can bedefined as the ratio of the feature size at a newertechnology node to the feature size at an olderreference technology node, then s is always lessthan one. There are two simplified scalingscenarios for interconnects:

• Scale metal pitch (W + S) at constant metalthickness (H) (see Figure 1)

• Scale metal pitch and the metal thickness

Under the first scenario, the load delay, line delayand current density will scale as 1/s, 1/s2, and 1/srespectively. Under the second scenario, the loaddelay, line delay and current density will scale as1/s2, 1/s2, and 1/s2 respectively. In either case, itcan be seen that interconnect delays begin todominate technology performance, and that currentdensity increases with scaling.

The interconnect scaling requirements driveseveral technology enhancements. Use of low-kmaterials lowers the interconnect capacitance perunit length c (particularly intra-level) in (1) andtherefore lowers the total interconnect delay

(0.5rcl2). Lower interconnect capacitance alsohelps in minimizing cross-talk noise. Furthermore,lower interconnect capacitance also helps inreducing the dynamic power dissipation (Pdyn)during the switching of gates in digital circuits,which can be estimated by

fVC2

1P 2

dyn α= (2)

where α is the activity factor or switchingprobability, C is the total capacitance, V is thepower supply voltage and f is the clock frequencyof the circuit.

Hence, it is the minimization of interconnectcapacitance that is driving the introduction of low-k dielectric materials. Similarly, lowerinterconnect resistance and higher current densityrequirements drive the use of new metallization(namely Cu). Since these low-k materials alsohave lower thermal conductivity than silicondioxide (Figure 5), heat dissipation becomes evenmore difficult. Thus VLSI technology scaling hasimportant implications on thermal effects asdiscussed in this section. The various trends intechnology scaling that causes increased thermaleffects in interconnects can be summarized as:

• Increasing current density• Increasing number of interconnect levels• Introduction of low-k dielectric materials• Increased thermal coupling

1.2 Implications of Thermal Effects onReliability and Performance

In current VLSI interconnect designs, currentdensity design rules are typically based on EMlifetimes [6]. However, the actual current densitiesare determined by the interconnect parameters(resistance and capacitance per unit length and thelength of the interconnect) and the strength of thebuffer which is driving the interconnect length. Ina typical design, long interconnects, which canpotentially have large current densities, are usuallysplit into buffered segments to improveperformance (signal slew and delay) [15]. Thesignal line length and buffer sizes are optimized togive maximum performance for a giventechnology. Signal lines longer than the optimumlength would increase interconnect delay whilebuffer sizes larger than the optimum would result

in an increase in buffer delay. Moreover,increasing buffer size would increase the currentdensity of the signal line connected to the outputand may also cause excessive power dissipation.Hence, it is important to quantify whether theassociated current densities in signal linesoptimized for maximum performance also meet theEM design limits.

As mentioned earlier, in DSM technologies,low-k materials invariably have poor thermalproperties and therefore the use of such materialscan significantly impact the EM design limits. Onthe other hand, the use of Copper, which has lowerresistivity, alleviates the problem to some extent.It is therefore important to quantify whether EMreliability or performance is the dominant factordetermining the optimal signal line length invarious low-k/Cu based interconnect systems.

Recently a methodology for quantitativecomparison of the impact of EM, thermal effectsand performance on the optimization of the signalline length has been formulated [16]. Themethodology has been applied to various low-k/Cuinterconnect systems [17]. The next two sectionsdeal with this methodology. In Section 2, effect ofself-heating on EM is briefly discussed followedby an analysis of the self-consistent designapproach that takes quasi-2D heat conduction intoconsideration. The modified self-consistentapproach is then used to quantify the impact ofnew interconnect materials (Cu and low-kdielectrics) on allowed current density limits.Section 3 introduces the methodology forcomputing the current densities from performanceconsiderations only, and then provides a directcomparison between the reliability andperformance based current density design limits[17].

2 Interconnect Reliability

2.1 Influence of Self-Heating on EM

EM lifetime reliability of metal interconnectsis modeled by the well known Black’s equation [5]given by,

)Tk

Q(expjATTF

mB

n−= (3)

where TTF is the time-to-fail (typically for 0.1%cumulative failure). A is a constant that is

dependent on the geometry and microstructure ofthe interconnect, j is the DC or average currentdensity. The exponent n is typically 2 undernormal use conditions, Q is the activation energyfor grain-boundary diffusion and equals ~ 0.7 eVfor Al-Cu, kB is the Boltzmann’s constant, and Tm

is the metal temperature. The typical goal is toachieve 10 year lifetime at 100 0C, for which (3)and accelerated testing data produce a design rulevalue for the acceptable current density, j0, at thereference temperature Tref. However, this designrule value does not comprehend self-heating.

The effect of self-heating can be analyzed fromthe following: The metal temperature, Tm in (3) isgiven by,

heatingselfrefm TTT −+= ∆ (4)

and,

( ) θ∆ RRITTT 2rmsrefmheatingself =−=− (5)

where Tref is typically taken as ~100 0C, ∆Tself-heating

is the temperature rise of the metal interconnectdue to the flow of current, R is the interconnectresistance, and Rθ is the effective thermalimpedance of the interconnect line to the chip. Irms

is the RMS current for a time varying currentwaveform, or the DC current for a constant currentstress. It can be observed from (3) and (4), that asself-heating increases, the metal temperatureincreases, and hence the EM lifetime decreasesexponentially. Therefore, it is important toaccurately account for self-heating in (3).

2.2 Self-Consistent Interconnect DesignAnalysis

In this sub-section the formulation of the self-consistent solutions [18], [16] for allowedinterconnect current density is summarized, andthen applied to analyze low-k/Cu interconnects inthe next sub-section. The ∆Tself-heating ininterconnects given by (5) can be written in termsof the RMS current density as,

( ))T(Wtt

WKTTj

mmmmins

effinsrefm2rms ρ

−= (6)

Here tm and Wm are the thickness and width ofinterconnect metal line, and ρm(Tm) is the metal

resistivity at temperature Tm. Note that the thermalimpedance Rθ in equation (5) has been expressedas,

effins

insWLK

tR =θ (7)

Here tins is the total thickness of the underlyingdielectric, Kins is the thermal conductivity normalto the plane of the dielectric, and L is the length ofthe interconnect. In this expression for the thermalimpedance, Weff has been modeled as the effectivewidth of the metal line taking quasi-2D heatconduction [16] into consideration fromexperimental data for high aspect ratio lines.

Now, in order to achieve an EM reliabilitylifetime goal mentioned earlier, we must have thelifetime at any (javg) current density and metaltemperature Tm, equal to or larger than the lifetimevalue (eg. 10 year) under the design rule currentdensity stress j0, at the temperature Tref. This valueof j0 is dependent on the specific interconnect metaltechnology. Therefore we have,

20

refB

2avg

mB

j

Tk

Qexp

j

Tk

Qexp

≥

(8)

Using the relationship between javg, jpeak, jrms, and rfor a rectangular unipolar pulse, (javg = r jpeak, & jrms

= r0.5 jpeak) we have after eliminating jpeak,

rj

j

2rms

2avg = (9)

Substituting for 2rmsj from (6) and 2

avgj from (8) in

(9) we get the self-consistent equation given by,

( ) effinsrefm

mmmmins

refB

mB20 WKTT

)T(Wtt

Tk

Qexp

Tk

Qexp

jr−

=ρ

(10)

Note that this is a single equation in the singleunknown temperature Tm. Once this self-consistenttemperature is obtained from (10), thecorresponding maximum allowed jrms and jpeak canbe calculated from (6) and the current density

relationships given above. The self-consistentequation given by (10) for unipolar pulses is alsovalid for more general time varying waveformswith an effective duty cycle reff [19].

1.0E+05

1.0E+06

1.0E+07

1.0E+08

1.0E+09

0.0001 0.001 0.01 0.1 1

Duty Cycle r

Max

imum

j rm

s [A

/cm

2 ]

1.0E+05

1.0E+06

1.0E+07

1.0E+08

1.0E+09

Max

imum

j pea

k [A

/cm

2 ]

Kins

X 10-6 W/m0K

1.15 (SiO2)

0.60 (HSQ)

0.25 (Polyimide k)0.024 (Air)

Figure 7. Self-consistent solutions for maximumallowed values of jrms and jpeak for Metal 6 in 0.25-µmtechnology for different values of Kins. Interconnectmetal is Cu with ρm(Tm) = 1.67 x 10-6 [1 +6.8 x 10-3 0C-1

(Tm - Tref)] Ω-cm. The activation energy is assumed tobe same as that for AlCu.

100

200

300

400

500

600

700

800

0.0001 0.001 0.01 0.1 1

Duty Cycle r

Sel

f-C

onsi

sten

t Met

al T

empe

ratu

re T

m

[0 C]

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1.0E+08

1.0E+09

Max

imum

j pe

ak [A

/cm2

]

Air

SiO2

SiO2

6.09.013.520.3

javg X 105 A/cm2

Figure 8. Self-consistent metal temperature and themaximum allowed jpeak for Metal 6 in a 0.25-µm Cutechnology, as a function of duty cycle for differentvalues of javg (or j0) for SiO2 and air as the dielectric.

2.3 Impact of New Materials on CurrentDensity Limits

Allowed interconnect current densities areexpected to be strongly influenced by low-kmaterials, which cause increased Joule-heating dueto their lower thermal conductivity [12], [20].Therefore we begin by analyzing the effect ofintroducing new interconnect and dielectric

0

1

2

3

4

5

6

7

Oxide HSQ Polyimide Air

Dielectric

Max

imum

Allo

wed

jpe

ak

(MA

/cm

2)

Cu: javg = 1.8 MA/cm2

Cu: javg = 0.6 MA/cm2

AlCu: javg = 0.6 MA/cm2

0.1-µm/Metal 8r = 0.1

Figure 9. Comparison of the maximum allowed jpeak

values for AlCu and Cu lines with two different javg

values for Metal 8 of a 0.10-µm technology shown fordifferent dielectric materials.

0.1

1

10

Oxide HSQ Polyimide

Dielectric

Max

imu

m A

llow

ed j p

eak (M

A/c

m2 )

Signal Lines

Power Lines

0.1 µm/Metal 8

Figure 10. Comparison of the maximum allowed jpeak

values for signal (r = 0.1) and power lines (r = 1.0) forMetal 8 of a 0.10 µm technology shown for differentdielectric materials. The lower values of jpeak in powerlines is because of their higher temperature rise resultingfrom carrying DC current.

materials on allowable current density limits. InFigure 7 the self-consistent values of jrms and jpeak

are plotted as a function of the duty cycle r, fordifferent dielectrics. It can be observed that jrms

and jpeak decrease significantly as dielectrics withlower thermal conductivity are introduced. Forsmall values of r, jrms varies very slowly with r.This is due to increased Joule-heating. In Figure 8we plot jpeak and Tm as a function of r for SiO2 andair as the dielectric for different values of thedesign current density, javg. It can be observed thatjavg does not change jpeak appreciably, and as rreduces, the increase in jpeak with javg becomesnegligible. Furthermore, for a dielectric materialwith low thermal conductivity such as air, jpeak isalmost independent of javg. This indicates thatintroduction of better interconnect materials

becomes increasingly ineffective in increasing jpeak

for dielectrics with poor thermal properties.Figure 9 summarizes the impact of low-kdielectrics on allowed jpeak for both Cu and AlCuinterconnect systems. It can be observed that thedifference between the maximum allowed jpeak forAlCu and Cu interconnects reduces as dielectricmaterials with poor thermal properties areintroduced. For the specific case of air as thedielectric, the jpeak values are very similar for AlCuand Cu. This is demonstrated for two differentvalues of javg for Cu, one value identical to that ofAlCu and the other three times higher than thisvalue, which accounts for the improved EMperformance in Cu. We also compared currentcarrying capabilities of signal and power lines andthe results are shown in Figure 10. Consistent withFigure 7, it can be observed that the jpeak values areabout an order of magnitude lower for the powerlines due to increased thermal effects.

3 Interconnect Performance3.1 Implications of Performance Optimization

on Signal Line Current Densities

As a next step we demonstrate a methodologyfor computing current density from performanceconsiderations only [16], [17]. Consider aninterconnect of length l between two buffers. Theschematic representation is shown in Fig. 6(a).Fig. 6(b) shows an equivalent RC circuit for thesystem. The voltage source (Vtr) is assumed toswitch instantaneously when voltage at the inputcapacitor (Vst) reaches a fraction x, 0 ≤ x ≤ 1 of thetotal swing. Hence the overall delay of onesegment is given by:

( ) ( ) ( ) ( ) ( ) 2LtrPLtr lcrxalCrRcxbCCRxb ++++=τ

(11)

where a(x) and b(x) only depend on the switchingmodel, i.e., x. For instance, for x=0.5, a=0.4 andb=0.7 [21]. If r0, c0 and cp are the resistance, inputand parasitic output capacitances of a minimumsized inverter respectively then Rtr can be writtenas r0 / s where s is size of the inverter in multiplesof minimum sized inverters. Similarly CP = s cp

and CL = s c0. If the total interconnect of length Lis divided into n segments of length l = L/n, thenthe overall delay is given by,

( ) ( ) ( )

( )rclLxa

Lsrcs

rcxbccrxb

l

LnT 0

0p00delay

+

+++== τ

(12)It should be noted in the above equation that s andl appear separately and therefore Tdelay can beoptimized separately for s and l. The optimumvalues of l and s are given as:

( )( )rcxa

)cc(rxbl

p00opt

+= (13)

0

0opt cr

crs = (14)

Note that sopt is independent of the switchingmodel, i.e., x.

Since, for deep sub-micron technologies, asignificant fraction of interconnect capacitance, c,is contributed by coupling and fringingcapacitances to neighboring lines as shown inFigure 11, a full 3D-capacitance extraction usingSPACE3D [22] for signal lines at various metallevels was used to obtain the values of c for SPICEsimulations.

This inverter-interconnect structure is used as adelay stage in a multi-stage ring oscillator and thecurrent waveforms and current densities along theinterconnect are be obtained. In practice, the inputcapacitance CL of the inverter is almost constantbut the output resistance Rtr and output parasiticcapacitance CP are bias dependent and thereforechange during the output transition. Thereforeaccurate values of optimal interconnect length andbuffer size need to be determined by SPICEsimulation. For this, we take advantage of the factthat the optimal interconnect length does notdepend on the buffer size. Therefore, we first setthe buffer size to an appropriate value and sweepthe interconnect length and find the optimumlength which minimizes the ratio of the ringoscillator stage delay and interconnect length.Using this optimum length, we subsequently sweepbuffer sizes and find the optimum buffer size,which minimizes the stage delay. This allows us toobtain the values of lopt and sopt taking into accountthe bias dependence of transistor resistances andcapacitances and the switching model.

Figure 11. Typical Interconnect Structure.

jrms (max)

sopt sopt

lopt

Figure 12. Optimized buffer and interconnect segmentshowing location of maximum current density.

This analysis is carried out for every metal layer inthe two technologies under study.

Note that due to the distributed nature of theinterconnect, the maximum current density occursclose to the buffer output (Figure 12). Hence, weneed to verify whether this maximum currentdensity, which is obtained from performanceconsiderations (j-performance) only, also meets the EMcurrent density limits (j-reliability) obtained earlierusing the self-consistent approach.

The interconnect current waveform in themetal lines for 0.25-µm and 0.1µm technologies,as obtained from SPICE simulations, were found tobe bipolar as expected (Figure 13). It should benoted that (3) represents the EM lifetime reliabilityequation for a unipolar pulse or dc current. TheEM lifetime under bipolar stress conditions isknown to be higher than that under the unipolarcase. In this work, the unipolar EM lifetimereliability equation is used as a worst case limit.

Also, the relative rise and fall skew was foundto be same across both technologies. From oursimulations it was observed that drivers andinterconnects optimized using (13) and (14),maintain good slew rates for rising and fallingtransitions for all the metal layers and across bothtechnologies with an effective duty cycle (reff =

2avgj / 2

rmsj ) of 0.12 ± 0.01 as shown in Table 1.

-2.0E-02

-1.5E-02

-1.0E-02

-5.0E-03

0.0E+00

5.0E-03

1.0E-02

1.5E-02

14 15 16 17 18 19 20

Time [ns]

Cur

rent

[A]

0.25 µm

-2.0E-02

-1.5E-02

-1.0E-02

-5.0E-03

0.0E+00

5.0E-03

1.0E-02

1.5E-02

2.0E-02

6 6.5 7 7.5 8

Time [ns]C

urre

nt [A

]

0.1 µm

Figure 13. Current waveforms in the top layer metallines obtained from SPICE simulations for the 0.25 µmand the 0.1 µm technologies.

Since for the signal lines the current waveformis symmetric and bipolar, javg and jrms are computedover half the time-period to obtain reff. Table 1also lists the maximum values of the average andpeak current densities.

In the above analysis it was assumed that theline capacitance per unit length is constant. In anactual design this is not necessarily the case.Consider the interconnect structure shown inFigure 11. The total interconnect capacitance Ctotal

can be viewed as a sum of capacitance to lines onthe same metal layer Cneighbor and lines on othermetal layers Cother (shown by solid and dashed linesrespectively in Figure 11) Cneighbor and Cother

consist of both parallel plate and fringingcapacitances. Lines on adjacent metal layers aretypically routed orthogonal to each other. Hencethe total capacitance between metal lines at twoadjacent layers is very small. On the other handthe capacitance to neighboring lines is large. Thisis specially the case for deep sub-microntechnologies where the aspect ratio of the lines isgreater than 1 and as a result, (Cneighbor / Ctotal) isvery high (0.7 to 0.9). The effective capacitance ofthe line ranges from (2Cneighbor+Cother) to Cother

depending upon whether the neighboring line

Layer lopt

(mm)

sopt javg

(x105A/cm2

jpeak

(x105A/cm2)

reff

1 2.51 75 3.06 27.02 0.112 2.41 80 2.91 26.38 0.113 4.79 157 1.67 14.69 0.114 5.48 148 1.32 13.48 0.105 12.5 494 0.61 5.18 0.126 13.9 454 0.52 4.69 0.11

(a)

Layer lopt

(mm)

sopt javg

(x105A/cm2)

jpeak

(x105A/cm2)

reff

1 0.85 36 5.13 38.99 0.132 0.9 40 5.10 39.48 0.133 1.57 97 2.73 20.93 0.134 1.79 85 2.39 18.27 0.135 4.47 276 1.28 9.78 0.136 4.68 249 1.21 9.00 0.137 8.8 500 0.49 3.67 0.138 9.58 522 0.44 3.5 0.12

(b)Table 1. Optimized interconnect length (lopt), buffer size(sopt), corresponding average and peak current densitiesand duty cycle (r) for (a) 0.25-µm Cu technology withinsulator dielectric constant = 3.3 and (b) 0.1-µm Cutechnology with insulator dielectric constant = 2.0. Theoptimum repeater size given by sopt means that the widthof the NMOS and PMOS for this inverter are obtainedby scaling the width of the corresponding transistors ina minimum sized inverter by a factor of sopt.

signals are switching in the opposite direction orthe same direction.

Furthermore, it is observed from simulationand can be shown that the interconnect currentremains almost the same if the load capacitance ofa buffer changes. The rise and fall time will getaffected significantly but the interconnect currentdoes not change appreciably if the buffer drivestrength is unchanged. However, for the slowertransition, r increases and for the faster transition, rdecreases (typical values observed in simulationare 0.2 for slower transition and 0.05 for the fastertransition).

3.2 Comparisons between Reliability andPerformance Based Current Density Limits

Figure 14 shows the comparison ofjavg-performance with the values of javg-reliability for a 0.25-µm technology based on [13]. It can be observedthat javg-performance is always lower than javg-reliability forall the dielectrics. However, for low-k dielectricmaterials we find that the difference betweenjavg-reliability and javg-performance reduces. This is due tothe fact that these dielectrics have lower

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

Oxide HSQ Polyimide Air

Dielectric

j avg

[x10

5 A/c

m2 ]

Performance

Reliability

0.25-µm/Metal 6

Figure 14. Comparison of javg values obtained fromreliability and electrical performance considerations forMetal 6 of a 0.25-µm Cu technology. reff = 0.11.

thermal conductivity than oxide which leads togreater interconnect Joule-heating and thereforelower allowable current densities.

Finally, it should be noted that the javg-reliability

values generated above were for an isolated line.In real ICs with multiple layers of interconnect, theJoule-heating of interconnect lines is known to besignificantly more severe due to thermal couplingbetween neighboring lines [23]. Figure 15 showscomparison of javg-performance with the values ofjavg-reliability for a 0.1-µm technology including thejavg-reliability values for realistic interconnectstructures using finite element simulations todemonstrate an optimistic scenario of thermalcoupling using various dielectrics.

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Oxide HSQ Polyimide Air

Dielectric

j avg [x

105 A

/cm

2 ]

Performance

Reliability

Reliability-Multilevel

0.1-µm/Metal 8

Figure 15. Comparison of javg values obtained fromreliability and performance considerations for Metal 8of a 0.1-µm Cu technology. reff = 0.12. The effect ofthermal coupling in realistic multilevel interconnectarrays on the javg values is also shown here for variousdielectric materials.

It can be observed that the javg-performance valuesremain lower than the javg-reliability values even afterthermal coupling in realistic structures is taken intoaccount. However, in this simulation it is assumedthat reff = 0.12 at all times, which can actuallyincrease (to ~ 0.2), if neighboring lines switch inthe opposite direction as discussed earlier. Thisincrease in reff will further lower javg-reliability. Hence,impact of switching states of signal lines onallowed current density design rules is important.

4 Thermal Effects under High-Current StressConditionsIn this section we will briefly address

interconnect design issues for high-currentrobustness. Apart from normal circuit conditions,ICs also experience high current stress conditions,the most important of them being the electrostaticdischarge (ESD), that causes accelerated thermalfailures [24]. Semiconductor industry surveysindicate that ESD is the largest single cause offailures in ICs. ESD is a high current short-timescale phenomena that can lead to catastrophic opencircuit failures, and to latent damage [25].

Interconnect failure due to ESD is becomingan important issue as VLSI scaling continues. Asthe number of wired gates (G) per chip increases(see Figure 2) the number of I/O pins (NP) alsoincreases as per Rent’s Rule [26], which is givenby

βGKN P ⋅= (15)

where K is the average number of I/Os per gate,and β is the Rent exponent that can vary from 0.1to 0.7. As a consequence of this increasing I/Opins, the package floor planning is changing fromperipheral package connections to array grids inorder to accommodate the increased I/O pin count[27]. In the array architecture, the interconnectwidths between external pads and the ESDstructures must decrease to preserve chip wirabilityand to prevent timing delays in critical paths and inthe receiver and driver networks. This trend canincrease the susceptibility of interconnects to ESDfailure. Furthermore, technology scaling and thetransition to new interconnect and dielectricmaterials necessitates a growing need tocomprehend the high current behavior of thesestructures and analyze their failure mechanisms inorder to provide robust design guidelines.

In [7] it has been shown that the critical currentdensity for causing open circuit metal failure inAlCu interconnects is ~ 60 MA/cm2. A short timescale high-current failure model for designingrobust interconnects to avoid thermal failure underhigh peak current conditions is also formulated in[7]. This model can be used to determine thecritical current for open circuit metal failure interms of the pulse width and the line width asshown in Figure 16. These curves provide designguidelines for ESD protection circuit and I/Ointerconnects. For example, a typical HumanBody Model (HBM) ESD pulse, which can bedescribed as a ~100 ns/1.3 A event [24], wouldrequire the width of the metal line to be greaterthan ~2.5 µm. Similarly for an electrical overstress(EOS) event of 1 µs the minimum line widthshould be more than ~7 µm. Hence a safe designguideline for these stress conditions would be ~10µm. A study from IBM has shown that the modelcan also be applied to design damascence Cuinterconnects [27].

0

1

2

3

4

5

6

0 2 4 6 8 10 12

Line Width [µm]

I crit

[A]

100ns

200ns

500ns

1µs

2000V/1.3 A HBM ESD

1.3 A EOS

TiN/AlCu/TiN

dAlCu = 0.6 µm

ds = 0.8 µm

Figure 16. Design rules for high-current robustness [7].

As mentioned earlier, interconnects can alsosuffer latent damage if the lines resolidify aftermelting and this has been shown to degrade theEM lifetime [8]. Figure 17(a) shows a TEMmicrograph of an unstressed 3.0 µm wide AlCuline. It can be observed that the grain size is ~ 1.5µm. A TEM diffraction analysis result is alsoshown in Figure 17(b). The diffraction pattern,which consists of diffraction spots, confirms theinformation from the TEM micrograph, that theunstressed lines have small number of large grains.The sparse spatial formation of the diffraction

spots is typical for a polycrystalline material withsmall number of large grains. Figure 18(a) showsa TEM image of a line (segment) that has beenstressed by a high current pulse but has not shownany physical damage or change in line resistance.The change in the microstructure is clearly visible.The diffraction patterns shown in Figure 18(b) arering shaped, which is due to the presence of a largenumber of grains with random orientations,indicating that the defect areas have smaller grainsize. Such grain size reduction will result fromrapid resolidification from a molten state.

The model presented in [7] can also be used toavoid this latent reliability hazard. Theseinterconnect design rules must be obeyed for highcurrent robustness.

1.5 µm

(a)

(b)Figure 17 a) TEM micrograph of an unstressed AlCuline with the b) corresponding TEM diffraction pattern.All materials above and below the AlCu line (includingthe TiN layers) were removed by ion-milling process.

25 nm

(a)

(b)

Figure 18 a) Microstructure of the metal withinresolidified sections showing small grain sizes b) TEMdiffraction rings validating the presence of a largenumber of small grains with random orientations. Theinnermost faint ring (shown by the arrows) indicates theappearance of a new phase.

SummaryULSI scaling requirements are causing

increased thermal effects in interconnects due toincreasing metallization levels, current density andthermal coupling, along with the introduction oflow-k dielectric materials with poor thermalconductivity. Coupled analysis of EM, thermaleffects and interconnect performance optimizationis necessary to quantify their impact on currentdensity limits and to understand various tradeoffsbetween technology, reliability and performanceissues. A methodology, which allows

determination of both reliability and performancebased current density limits, was discussed. Thistechnique can be effectively applied to study theimpact of technology scaling and performanceoptimization on interconnect reliability. For thelow-k/Cu interconnect systems (based on NTRS),it was shown that as long as point-to-pointinterconnect performance can be optimized, EMdesign limits for those signal lines will be satisfied.

Additionally, high-current design rules forinterconnects in ESD and I/O circuits werediscussed, and a latent damage mechanism that cancause overall product reliability degradation wasalso examined.

In conclusion, thermal effects are a growingproblem for deep sub micron interconnects andrequire careful considerations. In fact, a recentstudy that employed full-chip thermal analysisusing data from the International TechnologyRoadmap for Semiconductors, showed that thetemperature of the global metal lines are increasinginspite of the total chip power density remainingmore or less constant across various technologynodes (180 nm to 50 nm) [28]. If reliability basedcurrent density limits begin to conflict with thosebased on performance, employing dummy thermalvias might provide a solution for alleviatingthermal problems [29].

AcknowledgmentsThe author would like to acknowledge supportfrom the MARCO Interconnect Focus Center atStanford and the SRC.

References

[1] M. T. Bohr, “Interconnect scaling-the real limiter to highperformance ULSI,” Tech. Dig. IEDM, 1995, pp. 241-244.

[2] W. J. Dally, “Interconnect limited VLSI architecture,”IITC, 1999, pp. 15-17.

[3] S. J. Souri, K. Banerjee, A. Mehrotra, and K. C. Saraswat,"Multiple Si layer ICs: Motivation, performance analysis,and design implications," ACM Design AutomationConference, 2000, pp. 213-220.

[4] K. Banerjee, "Thermal effects in deep sub-micron VLSIinterconnects," Tutorial Notes, IEEE InternationalSymposium on Quality Electronic Design, 2000.

[5] J. R. Black, “Electromigration – A brief survey and somerecent results,” IEEE Trans. Electron Devices, vol. ED-16,pp. 338-347, 1969.

[6] B. K. Liew, N. W. Cheung, and C. Hu, “Projectinginterconnect electromigration lifetime for arbitrary current

waveforms,” IEEE Trans. Electron Devices, vol. 37, pp.1343-50, 1990.

[7] K. Banerjee, A. Amerasekera, N. Cheung and C. Hu,“High-current failure model for VLSI interconnects undershort-pulse stress conditions,” IEEE Electron Device Lett.,vol. 18, No. 9, pp. 405-407, 1997.

[8] K. Banerjee, D. Y. Kim, A. Amerasekera, C. Hu, S. S.Wong, and K. E. Goodson, "Microanalysis of VLSIinterconnect failure modes under short-pulse stressconditions," IRPS, 2000, pp. 283-288.

[9] J. Ida et al, “Reduction of wiring capacitance with new lowdielectric SiOF interlayer film for high speed/low powersub-half micron CMOS,” Tech. Dig. VLSI Symp., 1994,pp. 59-60.

[10] MRS Bulletin, October 1997.[11] B. Shieh, K. C. Saraswat, J.P. McVittie, S. List, S. Nag,

M. Islamraja, R.H. Havemann, "Air-Gap formation duringILD deposition to lower interconnect capacitance," IEEEElectron Device Lett., vol. 19, no. 1, pp. 16-18, 1998.

[12] K. Banerjee, A. Amerasekera, G. Dixit and C. Hu, “Theeffect of interconnect scaling and low-k dielectric on thethermal characteristics of the IC metal,” Tech. Dig. IEDM,1996, pp. 65-68.

[13] The National Technology Roadmap for Semiconductors-NTRS, 1997 http://www.itrs.net/ntrs/publntrs.nsf

[14] T. Sakurai and K. Tamaru, “Simple formulas for two- andthree-dimensional capacitances,” IEEE Trans. ElectronDevices, vol. ED-30, no. 2 pp. 183-185, 1983.

[15] J. Culetu, C. Amir, and J. McDonald, “A practicalrepeater insertion method in high speed VLSI circuits,”ACM Design Automation Conference, 1998, pp. 392-395.

[16] K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli,and C. Hu, "On thermal effects in deep sub-micron VLSIinterconnects," ACM Design Automation Conference,1999, pp. 885-891.

[17] K. Banerjee, A. Mehrotra, W. Hunter, K. C. Saraswat, K.E. Goodson, and S. S. Wong, "Quantitative projections ofreliability and performance for low-k/Cu interconnectsystems," IRPS, 2000, pp. 354-358.

[18] W. R. Hunter, “Self-consistent solutions for allowedinterconnect current density – Part I: Implications fortechnology evolution,” IEEE Trans. Electron Devices, vol.ED-44, pp. 304-309, 1997.

[19] W. R. Hunter, “Self-consistent solutions for allowedinterconnect current density – Part II: Application todesign guidelines,” IEEE Trans. Electron Devices, vol.ED-44, pp. 310-316, 1997.

[20] K. E. Goodson and Y. S. Ju, “Heat conduction in novelelectronic films,” Annu. Rev. Mater. Sci., 29: pp. 261-293,1999.

[21] R. H. J. M. Otten and R. K. Brayton, “Planning forperformance,” Proc. 35th Annual Design AutomationConference, 1998, pp. 122-127.

[22] “Physical design modeling and verification project(SPACE),” http://cas.et.tudelft.nl/research/space.html

[23] S. Rzepka, K. Banerjee, E. Meusel, and C. Hu,“Characterization of self-heating in advanced VLSIinterconnect lines based on thermal finite element

simulation,” IEEE Trans. on Components, Packaging andManufacturing Technology-Part A, vol. 21, No. 3, pp. 1-6,1998.

[24] C. Duvvury and A. Amerasekera, “ESD: A pervasivereliability concern for IC technologies,” Proceedings ofthe IEEE, Vol. 81, No. 5, pp. 690-702, 1993.

[25] C. Duvvury and A. Amerasekera, “State-of-the-art issuesfor technology and circuit design of ESD protection inCMOS ICs,” Semiconductor Science. and Tech., pp. 833-850, 1996.

[26] B.S. Landman and R.L. Russo, “On a pin versus blockrelationship for partitions of logic graphs,” IEEE Trans.Computers, vol. C-20, no. 12, 1971.

[27] S. H. Voldman, “ESD robustness and scaling implicationsof aluminum and copper interconnects in advancedsemiconductor technology,” Proc. EOS/ESD Symposium,1997, pp. 316-329.

[28] S. Im and K. Banerjee, "Full chip thermal analysis ofplanar (2-D) and vertically integrated (3-D) highperformance ICs,” Tech. Dig. IEDM, 2000, pp. 727-730.

[29] T-Y Chiang, K. Banerjee, K. C. Saraswat, "Effect of viaseparation and low-k dielectric materials on the thermalcharacteristics of Cu interconnects," Tech. Dig. IEDM,2000, pp. 261-264.