transmission line effects version lpages.infinit.net/alcor/docs/math/transmission line effects...

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Transmission line effects (and a short note on crosstalk effects)

A practical presentation Michel Forté, Ultra Electronics, Canada, January 28th, 2004, rev L

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TABLE OF CONTENTS

1 SCOPE................................................................................................................................................ 4

2 INTRODUCTION.............................................................................................................................. 4

3 DEFINITION..................................................................................................................................... 6

4 ELECTRICAL CHARACTERISTICS.............................................................................................. 8

4.1 SHORT REVIEW LOAD AND SOURCE "V vs I" DIAGRAMS................................................ 8

4.2 MODEL DESCRIPTION.......................................................................................................... 12 4.3 EXAMPLE WITH A RESISTIVE LOAD................................................................................. 14 4.4 EXAMPLE WITH A CAPACITIVE LOAD.............................................................................. 18

4.5 BERGERON DIAGRAMS AS AN ANALYSIS TOOL.............................................................. 20

4.6 EFFECT OF SIGNAL RISE TIME........................................................................................... 28

5 PRACTICAL SITUATIONS............................................................................................................ 29

5.1 ACMOS, HCMOS AND OTHER DEVICES CHARACTERISTICS........................................ 29

5.2 PCB's USUAL IMPEDANCES.................................................................................................. 31

5.3 DESCRIPTION OF THE TWO MAIN TYPES OF SIGNALS.................................................. 32

5.4 ONE DRIVER, ONE RECEIVER, clock or data signals ........................................................... 33

5.5 ONE DRIVER, MANY RECEIVERS, clock signals .................................................................. 40

5.6 DATA, CONTROL AND ADDRESS BUSSES.......................................................................... 43

6 RULES OF THUMB ....................................................................................................................... 52

6.1 RULES OF THUMB TO MANAGE TRANSMISSION LINE EFFECTS................................. 52

6.2 RULES OF THUMB TO MANAGE CROSS TALK EFFECTS................................................ 53

7 REAL LIFE WAVEFORMS ........................................................................................................... 55

7.1 REAL LIFE WAVEFORMS (from CMA3000 MK2 avionics project)....................................... 55

7.2 REAL LIFE WAVEFORMS (from “SuperHighway” defence communications project)........... 66

7.3 APPENDIX 1: PCB STRIP LINES AND MICROSTRIP CHARACTERISTICS..................... 68

7.4 APPENDIX 2: COAXIAL CABLES.......................................................................................... 70 7.5 APPENDIX 3: MATHCAD PROGRAM FOR OPEN TRANSMISSION LINE EFFECTS...... 73

8 BIBLIOGRAPHY............................................................................................................................. 75

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LIST OF FIGURES Figure 1: Typical waveforms distortions....................................................................................................................................................4 Figure 2: Obvious termination problem.....................................................................................................................................................5 Figure 3: Multiple clocking on MUX-DEMUX ATE (GRC-512)...........................................................................................................6 Figure 4: Twisted pair equivalent circuit...................................................................................................................................................6 Figure 5: Coaxial cable equivalent circuit ................................................................................................................................................7 Figure 6: Strip line equivalent circuit.........................................................................................................................................................7 Figure 7: V versus I curve for a 5V (or 100 ma) source with a 50 ohms impedance.........................................................................8 Figure 8: "V versus I" curves for a TTL driver .........................................................................................................................................9 Figure 9: Source and load equivalent circuit............................................................................................................................................9 Figure 10: "V versus I" curves for a source and a load........................................................................................................................10 Figure 11: Finding VS and VL from Io,Vo, as in Bergeron’s diagram (to come).............................................................................10 Figure 12: TTL driver, its load and the Thévenin equivalent of its load ............................................................................................11 Figure 13: "V versus I" curves for a TTL driver and its load...............................................................................................................11 Figure 14: Energy traveling down a transmission line..........................................................................................................................12 Figure 15: Transmission line rule #2.......................................................................................................................................................13 Figure 16: Driving a resistive load through a coaxial cable................................................................................................................14 Figure 17: Driving an open circuit through a transmission line.........................................................................................................15 Figure 18: Driving a short circuit through a transmission line...........................................................................................................16 Figure 19: Driving a capacitor through a transmission line................................................................................................................18 Figure 20: Driving a capacitor through a transmission line, waveforms ..........................................................................................19 Figure 21: TTL driver and load.................................................................................................................................................................20 Figure 22: Bergeron diagram for a TTL driver/receiver pair, 0 to high transition, 50 Ω line ......................................................20 Figure 23: TTL driver - transmission line pair at t > 0, < 2 line delays............................................................................................21 Figure 24: Transmission line - TTL receiver pair at t > 1, < 3 line delays......................................................................................21 Figure 25: Transmission line - TTL driver pair at t > 2, < 4 line delays...........................................................................................22 Figure 26: Waveforms for a TTL driver/receiver pair, 0 to high transition, 50 Ω line ...................................................................23 Figure 27: Bergeron diagram for a TTL driver/receiver pair, high to low transition, 50 Ω line..................................................24 Figure 28: Waveforms for a TTL driver/receiver pair, high to low transition, 50 Ω line...............................................................24 Figure 29: Bergeron diagram for a TTL driver/receiver pair, both transitions, 25Ω line..............................................................25 Figure 30: Waveforms for a TTL driver/receiver pair, both transitions, 25Ω line...........................................................................26 Figure 31: Bergeron diagram for a 0Ω driver driving a short through a 100Ω line.......................................................................27 Figure 32: The effect of rise time ...............................................................................................................................................................28 Figure 33: LVDS (Low Voltage Differential Signaling)........................................................................................................................30 Figure 34: Microstrip and stripline...........................................................................................................................................................31 Figure 35: Strong driver, no termination.................................................................................................................................................33 Figure 36: Strong driver and high impedance receiver Bergeron diagram.......................................................................................34 Figure 37: Strong driver and high impedance receiver waveforms ....................................................................................................34 Figure 38: Strong driver, diode termination............................................................................................................................................35 Figure 39: Strong driver and diodes terminated receiver Bergeron diagram...................................................................................36 Figure 40: Strong driver and diodes terminated receiver waveforms.................................................................................................36 Figure 41: Series termination at the source ............................................................................................................................................37 Figure 42: Waveforms for series termination at the source..................................................................................................................37 Figure 43: Parallel termination at the load.............................................................................................................................................38 Figure 44: Waveforms for parallel termination at the load..................................................................................................................38 Figure 45: Parallel termination at the load with capacitor..................................................................................................................39 Figure 46: Waveforms for parallel termination at the load with capacitor.......................................................................................39 Figure 47: "Many receivers" preferred topology...................................................................................................................................40 Figure 48: "Many receivers" possible waveforms..................................................................................................................................40 Figure 49: Helping with a small serial resistor......................................................................................................................................41 Figure 50: Preferred topology for one driver, many receivers ............................................................................................................41 Figure 51: One driver, many receivers; dangerous star topology.......................................................................................................42 Figure 52: One driver, many receivers; dangerous star topology waveforms ..................................................................................42 Figure 53: Example of multipath net ........................................................................................................................................................43 Figure 54: Increasingly complex routing.................................................................................................................................................46 Figure 55: Driving in parallel n 50 ohms lines (n = 1,2,6, ∞) of length 20/n cm with a source impedance of 25, 50 and 100 ohms .................................................................................................................................................................................................................47 Figure 56: Scope waveforms obtained when driving nets with peculiar topologies.........................................................................48 Figure 57: General PCB layout to control cross talk and transmission line effects ........................................................................53 Figure 58: Extender PCB layout to control cross talk and transmission line effects .......................................................................54 Figure 59: Example of a one driver one receiver clock scheme (SED1386 40 MHz clock)............................................................55

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Figure 60: Waveform directly at driver output (point A) ......................................................................................................................56 Figure 61: Waveform after serial discrete resistor located near driver output (point B) ...............................................................57 Figure 62: Waveform at receiver (point C).............................................................................................................................................58 Figure 63: Measured 20MHz SED1386 at clock input pin without driver serial resistor...............................................................59 Figure 64: Measured 20MHz SED1386 at clock input pin with driver serial resistor....................................................................59 Figure 65: Serial IO clock scheme ............................................................................................................................................................60 Figure 66: Measured 10MHz serial IO clock at driver output without termination resistor..........................................................61 Figure 67: Measured 10MHz serial IO clock at first receiver input without termination resistor................................................61 Figure 68: Measured 10MHz serial IO clock at last receiver input without termination resistor.................................................62 Figure 69: Measured 10MHz serial IO clock at driver output with termination resistor...............................................................62 Figure 70: Measured 10MHz serial IO clock at first receiver input with termination resistor......................................................63 Figure 71: Measured 10MHz serial IO clock at last receiver input with termination resistor......................................................63 Figure 72: "Real life" example of a data bus routing ...........................................................................................................................64 Figure 73: "Real life" example of a data bus waveform.......................................................................................................................65 Figure 74: Power PC SDRAM control signal at driver. Total net length is 10.7 cm......................................................................66 Figure 75: PowerPC control signal worst case stabilization time measured at the driver............................................................67 Figure 76: PowerPC control signal waveform at the far end receiver..............................................................................................67

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1 SCOPE This presentation deals with the application of lossless transmission line theory, and its

implications regarding the integrity of digital signals. The presentation is addressed mainly to design engineers, technicians, cad-cam staff and field personnel. Its purpose is to help people prevent and/or correct interconnection problems: 1) Between instruments

2) Between PCBs 3) Between ICs of a PCB Please feel free to make comments as we go along, such as sharing past experiences.

2 INTRODUCTION As signals rise times diminish, transmission line effects, which were previously seen only when

using long (> 1 meter) interconnections, are now present on most PCB boards where they often become a source of major headaches. These effects distort the digital signals edges:

Figure 1: Typical waveforms distortions

These characteristic patterns are called ringing. Their end effect on the "well being" of the circuit can be: 1) Multiple clocking on clock lines (which is often fatal) 2) Increased delay on level sensitive lines (which can be fatal at high temperatures where circuits are slower). 3) Improper operation of parts subjected to those signals. Here is a typical interconnection problem, and a possible correction:

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-demo-

Figure 2: Obvious termination problem

Later in the presentation, we present applicable parts of the transmission line theory and the way

to apply it to avoid these difficulties. What makes these problems especially bad to diagnose is that they are often intermittent and will

maliciously appear at temperature extremes, where probing the circuit is so enjoyable… At high temperatures, circuits are slower and marginal timings may fail. Problems appear even more often at low temperature, where circuits are faster, thus providing sharper edges and at the same time being more susceptible to sharp edges. Here are 3 examples of those problems, which were diagnosed sometimes ago, at BAE Systems:

EXAMPLE 1: RAM memory write problem on GRC-512 BBU XMT-RCV PLL

cause: uncontrolled WRITE PULSE line layout solution: change the WRITE PULSE line layout from a star to a daisy chain.

EXAMPLE 2: Flash memory read problem on GRC-512 RFU CONTROLLER

Excessive ringing on address input caused, at low temperatures, a wrong data reading because the address input voltage value exceeded the chip supply value for a sufficiently long time (there was actually a spec for this).

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cause: uncontrolled WRITE PULSE line layout solution: terminate all address lines with a diode network (one diode to gnd, one to vcc). EXAMPLE 3: Multiple clocking on MUX-DEMUX ATE (GRC-512)

Figure 3: Multiple clocking on MUX-DEMUX ATE (GRC-512)

The Logic Analyzer is triggered spuriously because it expects a 0-5V level cause: wrong cable impedance matching solution: remove one of the 2 resistors, preferably the 50 Ω

3 DEFINITION

Physically, a transmission line is a set of two conductors which exhibit between themselves controlled mechanical and electrical characteristics.

examples: 1- Twisted pair

Figure 4: Twisted pair equivalent circuit

Zo ≅ 120 Ω

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2- Coaxial cable: (RG58 and the likes)- (see appendix 2)

Figure 5: Coaxial cable equivalent circuit

Z0 ≅ 50 - 75 Ω

3- Stripline: (designed on a PCB)- (see appendix 1)

Figure 6: Strip line equivalent circuit

Z0 ≅ 40 - 100 Ω

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4 ELECTRICAL CHARACTERISTICS

4.1 SHORT REVIEW LOAD AND SOURCE "V vs I" DIAGRAMS

4.1.1 Voltage sources and current sources

A time invariant voltage source and its equivalent current source are shown in the following diagram:

Both of these models are equivalent and are simply different ways of looking at the "V versus I"

curve which describes the source behavior; for the rest of the presentation, we will use the voltage source model since voltages are easier to measure than currents.

Figure 7: V versus I curve for a 5V (or 100 ma) source with a 50 ohms impedance

- 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 8 0 2 0 0- 1

0

1

2

3

4

5

6s o u r c e . m : V v e r s u s I c u r v e f o r a 5 V ( o r 1 0 0 m a ) s o u r c e w i t h a 5 0 o h m s i m p e d a n c e

I , m a

V,

volt

s

s l o p e = - 5 0 o h m s

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More generally, the curve V versus I is not a straight line. For example, a TTL driver curve looks like the following:

Figure 8: "V versus I" curves for a TTL driver

4.1.2 Sources and loads A time invariant voltage source and a load are shown in the following diagram. Note that the

load, which we would normally show as a resistor to ground, has been represented by another source to be more general to illustrate all kinds of loads such as pull-ups. In fact, the load cannot be distinguished from the source except for the fact that, by convention, the current enters it instead of leaving it.

Figure 9: Source and load equivalent circuit Because of the current I sign convention, the source "V versus I" curve has a negative slope -RS

whereas the load has a positive slope +RL. The voltage V and current I present in the circuit are simply obtained at the intersection of the source and the load curves as shown below:

- 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 5 1 0 1 5 2 0 2 5 3 0- 3

- 2 . 5

- 2

- 1 . 5

- 1

- 0 . 5

0

0 . 5

1

1 . 5

2

2 . 5

3

3 . 5

4

4 . 5

5t t l . m : " V v e r s u s I " c u r v e s f o r a T T L d r i v e r

I , m a

V,

volts

d r i v e r " h i g h "d r i v e r " l o w "

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- 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 8 0 2 0 0-1

0

1

2

3

4

5

6s o u - l o a d . m : V v e r s u s I c u r v e f o r a 5 V , 1 0 0 o h m s s o u r c e w i t h a 5 0 o h m s t o g r o u n d l o a d

I , m a

V,

volts

s l o p e = - 1 0 0 o h m s

s l o p e = + 5 0 o h m s

3 3 m a , 1 . 6 6 v o l t s

Figure 10: "V versus I" curves for a source and a load

Note also that if a point (Io,Vo) is known on a linear source curve of impedance RS, then the source voltage is Vo+IoRS. Also, if a point (Io,Vo) is known on a linear load curve of impedance RL, then the "load voltage" is Vo-IoRL, as shown in the picture below:

VS

VL

V

I

RS = 20

Source vs Load curves.vsd

RL = 70

Io,Vo

Io,Vo

Figure 11: Finding VS and VL from Io,Vo, as in Bergeron’s diagram (to come)

Obviously, the same line of reasoning applies if the curves are not straight lines as in the case of

real drivers and real receivers. Below is an example of a TTL gate driving a voltage divider connected between VCC and GND

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Figure 12: TTL driver, its load and the Thévenin equivalent of its load

Figure 13: "V versus I" curves for a TTL driver and its load

- 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 5 1 0 1 5 2 0 2 5 3 0- 3

- 2 . 5

- 2

- 1 . 5

- 1

- 0 . 5

0

0 . 5

1

1 . 5

2

2 . 5

3

3 . 5

4

4 . 5

5t t l - l o a d . m : " V v e r s u s I " c u r v e s f o r a T T L d r i v e r a n d i t s l o a d

I , m a

V,

volts

d r i v e r " h i g h "

d r i v e r " l o w "

l o a d c u r v e

( 8 . 2 0 7 6 , 2 . 6 0 1 1 )

( - 8 . 5 7 9 2 , 0 . 2 0 2 9 7 )

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4.2 MODEL DESCRIPTION

A transmission line is essentially a delay line in which waves of voltage and current circulate. The line stores energy in the form of voltage, stored in the line capacitance, and in the form of current, stored in the line inductance. When a voltage is applied or a current injected at one end of the line, a wave of voltage and current travels down the line at nearly the speed of light (which is 30 cm/nsec). When the waves encounter a discontinuity, there is an "energy exchange" between the voltage and the current waves and there are reflected waves. The diagram below illustrates how energy travels along the line:

Figure 14: Energy traveling down a transmission line

Where the source is turned on, a current I1 is injected in the first inductor, which "stores"

the current. This current charges the first capacitor, which discharges in the second inductor and so on, forming the propagating waves of voltage and current.

By solving the differential equations that describe this electrical system, and defining

we arrive at mathematical solutions for the voltage and current waveforms. In the above

definition of Zo, L is the inductance per unit length (Henries/meter) and C is the capacitance per unit length (Farads/meter)

The smaller the inner conductor, the larger is L and thus the larger Zo; the nearer the 2

conductors, the larger is C and the smaller is Zo. The mathematical solution can be interpreted to give the following model, which obeys a few

simple rules: rule 1) The waves travel at nearly the speed of light:

c is the speed of light = 3x108 m/sec εr is the dielectric constant (4.7 for PCB material G10) v ≅ 12 cm/nsec on a G10 board

CL

impedancesticcharacteriZo == ..

r

cv

ε=

13

rule 2) Each time there is a change at the driver/line or line/load interfaces, either because different values of voltage/current (Vo, Io) reach an interface or because the driver/receiver characteristics change, the new values V and I propagating back along the transmission line are calculated using the models in the figure below.

If the change occurred because the driver output or the load changed, then "Io, Vo" are

the values in the line when the change occurred; “I, V” are the new values of current and voltage given by the driver or accepted by the load, that are also propagating back along the line.

If the change occurred because a wave "Io, Vo" has reached the driver or the load, then

again, “I, V” are the new values of current and voltage given by the driver or accepted by the load, that are also propagating back along the line.

Figure 15: Transmission line rule #2

• The key concept is the expression Vo ± IoZo which shows that the energy is present in the form of both a voltage and a current.

N.B.: This is completely general, for any type of source or load: for example, the load driven by

the transmission line may be a short, an open, another transmission line, a capacitor, another source, a filter, etc.

rule 3) Each time a signal reaches the load or the source, if “I, V” are different from “Io,

Vo”, reflections occur. The amplitude of the reflected wave is the difference between the new signal value that appears at the load (or source) (= “I, V”) and the incident signal value (= “Io, Vo”).

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4.3 EXAMPLE WITH A RESISTIVE LOAD To help crystallize these rules, let us look at a few practical cases illustrated with the following

simple circuit:

Figure 16: Driving a resistive load through a coaxial cable

The following picture shows the progression of the voltage and current waves along the cable.

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4.3.1 First limit case, RL = ∞, open circuit: -demo-

Figure 17: Driving an open circuit through a transmission line

According to rule # 2, the source first sees the line as a 50 Ω resistor to ground, forming a divider network with the source impedance. A 2.5V, 50 ma wave starts toward the load.

According to rule #2, the load sees the line as a 2.5 V + 50ma*50Ω = 5 V source. Since there is no current, since the load is an "open", the voltage at the load becomes 5 V.

According to rule # 3, the reflected voltage wave is 5V at the load - 2.5V incident = 2.5V reflected. The reflected current wave is 0 ma at the load - 50ma incident = -50 ma reflected

As we can observe, the source "sees" the load 100 nsec late.

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4.3.2 Second limit case, RL = 0, short circuit: -demo-

Figure 18: Driving a short circuit through a transmission line


According to rule # 2, the load sees the line as a 50ma + 2.5V/50Ω = 100 ma source. There is a voltage of 0 volt since the load is a short

According to rule # 3, the reflected voltage wave is 0V at the load - 2.5V incident = -2.5V reflected. The reflected current wave is 100ma at the load - 50ma incident = 50 ma reflected

As we can observe, the source "sees" the short 100 nsec late.

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4.3.3 General case, RL = any value: -demo-

4.3.3.1 Voltage equations: According to rule # 2, the source first sees the line as a Zo Ω resistor to ground, forming a

divider network with the source impedance. A wave of amplitude "2.5V, 50ma = 2.5V/50Ω" starts toward the load. The load sees the line as a "5V = 2.5 V + 50ma*50Ω" source. The voltage VL at the load is:

The reflected voltage VR is the actual voltage VL minus the incident voltage (rule 3) or

The voltage reflection coefficient CRV is the ratio of the reflected to incident wave and is given

by the well known formula

If RL = Zo = 50Ω, there is no reflection; if RL > Zo, there is a positive reflection; the largest

positive reflection is obtained when RL = ∞, as shown in a previous wave diagram. If RL < Zo, there is a negative reflection; the largest negative reflection is obtained when RL = 0, as shown in a previous wave diagram.

4.3.3.2 Current equations: The load sees the line as a "2.5V/50Ω + 50ma = 100ma" source. The current IL at the load is:

The reflected current IR is the actual current IL minus the incident current (rule 3) or

The voltage reflection coefficient CRI is the ratio of the reflected to incident wave and is given by the well known formula

Note that CRI = -CRV. A positive voltage reflection, due to a large load resistor is thus associated

with a negative current reflection, and vice-versa.

Ω+

×=50

5L

LL R

RVV

Ω+Ω−

×=−

Ω+

×=5050

5.25.250

5L

L

L

LR R

RVV

RR

VV

+−

=

Ω+Ω−

=ZoRZoR

RR

CL

L

L

LRV 50

50

Ω+

Ω×=

5050

100L

L RmaI

+Ω−Ω

×=−

Ω+

Ω×=

L

L

LR R

Rmama

RmaI

5050

505050

50100

+−

=

+Ω−Ω

=L

L

L

LRI RZo

RZoRR

C5050

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4.4 EXAMPLE WITH A CAPACITIVE LOAD -demo-

Figure 19: Driving a capacitor through a transmission line

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Figure 20: Driving a capacitor through a transmission line, waveforms


According to rule # 2, the load sees the line as a 2.5 V + 50ma*50Ω = 5 V source, and charges to 5V with a time constant of 50Ω×1nF = 50 nsec.

According to rule # 3, the reflected voltage wave is the load waveform - 2.5V (incident) = 50 nsec RC capacitor charge from -2.5 to +2.5V. The reflected current wave is the load waveform -50ma (incident) = current discharge from +50ma to -50ma.

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4.5 BERGERON DIAGRAMS AS AN ANALYSIS TOOL

Bergeron diagrams are an analytical tool to visualize and predict line transmission effects for a single driver single receiver pair. As an example, we will consider the TTL driver and the receiver "V vs I" curves shown previously:

Figure 21: TTL driver and load

At time t = 0, the switch is closed, and the TTL driver, already in a high state, starts to drive the transmission line. This point in time is the START POINT in the diagram below. If the transmission line were infinitely short, the voltage and current would instantaneously jump to the END POINT. Because of the transmission line, the voltage and current change by steps as shown by the zigzag line and as explained below.

Figure 22: Bergeron diagram for a TTL driver/receiver pair, 0 to high transition, 50 Ω line

-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5ttl-high.m: Bergeron`s diagram for TTL driver/receiver pair and a 50 ohms line

I, ma

V,

volt

s

driver "high" curve

receiver curve

START POINT, t<0

END POINT

A(22.6,1.13)0<t<2

B(-.62,2.29)1<t<3

C(7.62,2.70)2<t<4

-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5


I, ma

V,

volt

s

driver "high" curve

receiver curve

START POINT, t<0

END POINT

A (22.6,1.13)0<t<2

B(-.62,2.29)1<t<3

C(7.62,2.70)2<t<4

-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5


I, ma

V,

volt

s

driver "high" curve

receiver curve

START POINT, t<0

END POINT

A(22.6,1.13)0<t<2

B(-.62,2.29)1<t<3

C(7.62,2.70)2<t<4

-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5


I, ma

V,

volt

s

driver "high" curve

receiver curve

START POINT, t<0

END POINT

A(22.6,1.13)0<t<2

B(-.62,2.29)1<t<3

C(7.62,2.70)2<t<4

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By rule 2), at t = 0, when the switch is closed, the driver sees a 50 Ω resistor load to ground as shown below. The transmission line load curve is thus the straight line between the start point and point A.

Figure 23: TTL driver - transmission line pair at t > 0, < 2 line delays

A wave of voltage and a wave of current start traveling down the line. The voltage and current values are given by the coordinates of intersection point A: 22.6 ma, 1.13 volts.

At t = 1 transmission line unit delay, the waves reach the load, to which, by rule 2), they appear as a source of 2.26 volts with 50Ω impedance as shown below: V + I×Zo = 1.13 + 22.6 ma × .050 KΩ =2.26 volts.

Figure 24: Transmission line - TTL receiver pair at t > 1, < 3 line delays

The transmission line source curve is thus the straight line between point A and B. The voltage and current values at the load are given by the coordinates of intersection point B: -.62 ma, 2.29 volts. By rule 3), there are reflected waves of amplitude such that what remains in the line is what is seen by the load (-.62 ma, 2.29 volts).

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These waves travel back toward the source where they make the transmission line look like a load of 2.321 volts with 50Ω impedance as shown below: V - I×Zo = 2.29 - -.62 ma * .050 KΩ = 2.321 volts.

Figure 25: Transmission line - TTL driver pair at t > 2, < 4 line delays

The transmission line source curve is thus the straight line between point B and C. The voltage and current values at the source are given by the coordinates of intersection point C: 7.62 ma, 2.70 volts. Again, parts of the wave are reflected back. By iterating, we slowly converge toward the END POINT.

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On a practical point of view, what is important is to determine the moment where the load will see a high level (2.0 volts). In this case, the first incident wave carries 2.29 volts and is thus enough so that the delay to get a "one" is the minimum value of one line delay. This can be better observed in the following time diagrams extracted from the Bergeron diagram. The waveform at the driver is also supplied. These can of course be seen on a scope.

Figure 26: Waveforms for a TTL driver/receiver pair, 0 to high transition, 50 Ω line

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

ttl-high.m: driver

t, units of line delay

V,

volts

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

ttl-high.m: receiver


V,

volts

24

4.5.1 A FEW OTHER EXAMPLES OF BERGERON DIAGRAMS

4.5.1.1 HIGH TO LOW TRANSITION ON THE PREVIOUS TTL DRIVER-RECEIVER PAIR (50 Ω LINE)

The Bergeron diagram and the corresponding waveforms are given below:

-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5ttl-low.m: Bergeron`s diagram for TTL driver/receiver pair and a 50 ohms line

I, ma

V, v

olt

s

receiver

driver "low"

driver "high"

END POINT

START POINT

Figure 27: Bergeron diagram for a TTL driver/receiver pair, high to low transition, 50 Ω line

Figure 28: Waveforms for a TTL driver/receiver pair, high to low transition, 50 Ω line

Note that the delay to a guarantied 0 at the load is 3 line delays instead of 1, and that there is a slight undershoot.

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

ttl-low.m: driver


V,

volt

s

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

ttl-low.m: receiver


V,

volt

s

25

4.5.1.2 BOTH TRANSITIONS ON THE PREVIOUS TTL DRIVER-RECEIVER PAIR (25 Ω LINE)

The Bergeron diagram and the corresponding waveforms are given below for a 25Ω line

-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5ttl-25.m: Bergeron`s diagram for TTL driver/receiver pair and a 25 ohms line

I, ma

V,

volts

receiver

driver "low"

driver "high"

Figure 29: Bergeron diagram for a TTL driver/receiver pair, both transitions, 25Ω line

26

Figure 30: Waveforms for a TTL driver/receiver pair, both transitions, 25Ω line

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

low transition: driver


V,

volts

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

low transition: receiver


V,

volts

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

high transition: driver


V,

volts

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

high transition: receiver

t, units of line delayV

, vo

lts

27

Note that the delay to a guarantied 1 at the load is 3 line delays, and to a 0 is 5 line delays instead of 1. A 25Ω line equivalent is obtained when many receivers are regularly connected along the line (such as in memory address and data lines). Each receivers adds to the line distributed capacitance.

4.5.1.3 LIMIT CASE OF A 0Ω DRIVER DRIVING A SHORT THROUGH A 100Ω LINE

The Bergeron diagram and the corresponding waveforms are given below:

Figure 31: Bergeron diagram for a 0Ω driver driving a short through a 100Ω line

We see that the first current wave is 5V/100Ω = 50ma. There is a reflected wave of 50 ma for a total of 100 ma which comes back towards the source where another 50 ma adds up, and so on. The short builds itself up by 50 ma on every time interval, which corresponds one line delay.

-500 -400 -300 -200 -100 0 100 200 300 400 500-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10short.m: Bergeron`s diagram for a 0 ohm driver driving a short through a 100 ohms line

I, ma

V,

volt

s

receiver = short

driver "high"

START POINT

28

4.6 EFFECT OF SIGNAL RISE TIME -demo-

So far we have only considered sources with 0 nsec rise time. This is not the case in real life where rise times range from below 1 nsec for ECL devices to 1-2 nsec for the fastest CMOS devices to 10-20 nsec for the slowest CMOS devices. As can be seen below, on a worst case situation of low impedance driver and high impedance receiver, when the rise time reaches 4 times the line delay, the waveform is almost monotonous. It is probably reasonable to use a factor 4, i.e. the line delay should be smaller than 1/4 the rise time tr to keep ringing small enough. At 12 cm/nsec, the line length in cm should be shorter than 12 × 1/4 tr or 3 × tr. The number to remember is 3 cm maximum per nsec of rise time.

Figure 32: The effect of rise time

29

5 PRACTICAL SITUATIONS

To see transmission line effects with the rising times we are dealing with nowadays, be prepared to use a >300 MHz scope, with possibly an active high impedance probe. The measurement is ruined by using a ground wire and disturbed by using the probe hook. Remove the hook to keep only the tip and use the small spring as a ground connection to be connected to the ground plane less than 1 cm from the signal being probed. A trick I use often, is short (1 cm) pieces of wire which I wirewrap around the tip and the spring and which I solder to the points of interest to keep my hands free. Of course, it is nice to be able to see these effects, but it is much better to avoid them in the first place, as we show below.

5.1 ACMOS, HCMOS AND OTHER DEVICES CHARACTERISTICS Old HCMOS devices (1980…) have delays of the order of 25 nsec and rise times of the order of 16 nsec, so that transmission line effects start to appear for line delays of 16 nsec x 3 cm/nsec, or 48 cm on a G10 board. The drivers have a symmetrical up and down drive capability and an output resistance of ~ 120 ohms. Inputs and outputs are clamped with diodes (~1.4V clamping voltage observed). Inputs have high impedance (< 10 uA leakage). ACMOS devices have delays of the order of 8 nsec and rise times of the order of 2 nsec, so that transmission line effects start to appear for line delays of 2 nsec x 3 cm/nsec, or 6 cm on a G10 board. The drivers have a symmetrical up and down drive capability and an output resistance of 23 ohms maximum guaranteed to be able to drive a 50 ohms line; the wave that leaves the driver has an amplitude of 50/(22+50) = 70% of VCC which is the minimum input to guarantee a high level. If necessary, many drivers from the same chip can be paralleled. Inputs and outputs are clamped with Schotky diodes (~ .8V clamping voltage observed). Inputs have high impedance (< 10 uA leakage). Popular ICs and FPGAs nowadays use 3.3 volts I/Os with TTL levels (<.8V low, >2.0V high) input characteristics. Most inputs are high impedance inputs, with ESD protection diodes which may help quench reflections. Drivers are often not very well characterized; most of the time also, the typical drive is much higher than the guaranteed minimum. In fact, the rise times nowadays are typically 2 nsec or faster, and the drive on large ICs or CPUs is typically ~20 to 50 ohms, depending on signals. As we will see soon, these source resistances are well suited for most situations. There are now a large number of new families on the market, each with its advantages in terms of speed, noise, drive, etc. A few of them are listed in the table below:

Family name

Company Power supply Drive Speed

HC Many 5V 4 ma 24 nsec AC Many 5 / 3.3V 24 / 12 ma 3.5 / 5 nsec

AHC Texas Instruments 5/ 3.3 V 8 / 4 ma 5.5 / 8.3 nsec VHC Fairchild 5 / 3.3 V 8 / ? ma 10.5 / ? nsec VCX Fairchild 3.3 / 2.5 V 24 ma 2.5 / 3.2 nsec LCX Fairchild 3.3 V 24 ma 6.5 nsec LVX Fairchild 3.3 V 4 ma 12 nsec LVQ Fairchild 3.3 V 12 ma 9.5 nsec LVT Fairchild 3.3 V 32 ma 4.1 nsec

ALVC Philips 3.3 / 2.5 / 1.2 V 24 ma 2.0 nsec at 3 V

30

LVDS (Low Voltage Differential Signaling) sets a new standard altogether. It is a way to communicate data at very high rates (gigabit/sec) using very low power by means of a differential low voltage (~ 350 mV) swing. It has been standardized as ANSI/EIA/TIA-644 and is supported by many semiconductor vendors. The figure below illustrates LVDS:

Figure 33: LVDS (Low Voltage Differential Signaling)

It is most interesting to draw the Bergeron diagram for such a differential driver.

31

5.2 PCB's USUAL IMPEDANCES From the microstrip and strip line charts in appendix 2, we have the following typical

impedances and capacitances, starting from the fact that the PCB's are often 100 mil thick with 8, 10 or 12 layers (=> ~10 mil between layers). 1 mil = 1/1000 inch = .0254 mm.

Figure 34: Microstrip and stripline

Z0

(ohms)

√εr × Z0 Microstrip

W/h Stripline

W/b = W/2h Stripline

W/h Microstrip W (mil) for h = 10 mil

Stripline W (mil) for h = 10 mil

Microstrip capacity

(pF/m) for h = 10 mil

Stripline capacity

(pF/m) for h = 10 mil

25 54 5 1.5 3 50 30 229 324 50 108 1.5 .4 .8 15 8 112 153 60 130 1.0 .25 .5 10 5 91 133 75 163 .5 .13 .26 5 2.6 64 108 100 217 .2 - - 2 - 47 83

Table 1: Usual PCB trace impedances and capacitances

We see that to obtain large impedances (> 50Ω), the dielectric thickness must be increased. High impedances are easier to obtain on a microstrip, on the PCB top or bottom layer, but the signals are not as well shielded. With a minimum trace width of 5 mil, we see that one can obtain Zo up to 75 Ω on the top layer (microstrip) and 60 Ω on the internal layers (stripline). One must keep in mind that ICs input are capacitive, and when many are connected across a line (such as an address bus line), the effective line impedance decreases. For example, consider a 60 Ω strip line with ten 5 pF IC inputs uniformly distributed along its 20 cm length. The line intrinsic capacitance is 26.6 pF (from 133 pF/m (see above table) multiplied by .2m). From 26.6, it increases to 76.6 (=26.6 + 10*5). Since Zo = √L/C, Zo decreases by 1.71 (=√76.6/26.6) to 35 Ω.

32

5.3 DESCRIPTION OF THE TWO MAIN TYPES OF SIGNALS The two main types of signals are 1) “data”, 2) “clock” or “edge sensitive” signals. Each type of signal has different requirements: whereas clock signals must show a monotonous transition from the low to high and high to low states, the only thing we are concerned about data signals is the final time to stabilize to a valid lo

Time

Maximum logic“0” value

clock vs data signals requirements.vsd

Minimum logic“1” value

Voltage

Not acceptable

Acceptable

“CLOCK” SIGNALS

Time

Maximum logic“0” value

Minimum logic“1” value

Voltage

Acceptable(weak driver) Acceptable if overshoot not too high

(strong driver)

“DATA” SIGNALSTotal turn-on time Total turn-on time

w or high state. This is illustrated below:

33

5.4 ONE DRIVER, ONE RECEIVER, clock or data signals

5.4.1 Worst case of a strong driver and high impedance receiver with no termination demo

Figure 35: Strong driver, no termination

As we see below, this topology does not provide a monotonous transition and is thus unacceptable for clock signals. For data signal, it could be acceptable if the excessive overshoot does not cause the receiver IC to misbehave.

34

-140 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10strong.m: Bergeron`s diagram for a strong driver, high impedance receiver, 50 ohms line

I, ma

V,

volts

driver "high" curve

receiver curve= vertical line

START POINT, t < 0

Figure 36: Strong driver and high impedance receiver Bergeron diagram

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

strong-high: driver


V,

volt

s

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

strong-high: receiver


V,

volt

s

Figure 37: Strong driver and high impedance receiver waveforms

35

5.4.2 Diodes termination (like ACMOS) demo

Figure 38: Strong driver, diode termination

A termination with diodes has many qualities, even if it is not as good as a resistor termination. 1) If they are part of the receiver, there is no extra hardware (such as ACMOS) 2) Most of the energy put in the transmission line goes back to the supply through the diodes instead of being wasted. 3) For multiple receivers, as we will see later, all one has to care is to drive the line hard and connect the receivers along a single main line.

At 3.3V or lower though, it is not as useful as at 5V, because of the non-negligible turn-on offset voltage (~ .5V).

36

-140 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10strong-d.m: Bergeron`s diagram for a strong driver, diodes terminated receiver, 50 ohms line

I, ma

V,

volt

s

driver "high" curve

receiver curve= vertical line

START POINT, t < 0

Figure 39: Strong driver and diodes terminated receiver Bergeron diagram

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

strong-diodes high: driver


V,

volts

0 1 2 3 4 5 6 7 8 9 10-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

UNDEFINED LEVEL

strong-diodes high: receiver


V,

volts

Figure 40: Strong driver and diodes terminated receiver waveforms

37

5.4.3 Series resistor at the source demo (Only useful if R source < line impedance)

Figure 41: Series termination at the source

The series resistor is chosen so that the total source impedance is equal to the line impedance. The voltage wave that travels down the line is 2.5V high. The high impedance receiver sees 5V because of the positive reflection. The reflection is entirely absorbed when it comes back to the driver. N.B.: another receiver which would be connected in the middle of the line would temporarily see a 2.5V level and may glitch. The waveforms are shown below.

Figure 42: Waveforms for series termination at the source

38

5.4.4 Parallel resistor at the load demo (Only useful if R source is small enough so that 5V × Zo/(R+Zo) > 3.5V (guaranteed

high level)

Figure 43: Parallel termination at the load

The parallel resistor is chosen equal to the line impedance. The voltage wave that travels down the line is > 3.5V high. The high impedance receiver sees 3.5V because there is no reflection.. N.B.: another receiver which would be connected in the middle of the line would see a > 3.5V level and would work correctly. On the average, the power dissipation is 52/50Ω × ½ = ¼ watt! The waveforms are shown below.

Figure 44: Waveforms for parallel termination at the load

See section 7.1.1 for a "real life" example

39

5.4.5 Combination resistor+capacitor at the load demo

Same as a resistor only, except that the power dissipation is halved:

Figure 45: Parallel termination at the load with capacitor

The parallel resistor is chosen equal to the line impedance. The voltage wave that travels down the line is > 3.5V high. The high impedance receiver sees 3.5V because there is no reflection.. N.B.: another receiver which would be connected in the middle of the line would see a > 3.5V level and would work correctly. The RC value should be larger than ~ 2 × longest period without transition. On the average, the power dissipation is (2.5)2/50Ω = 1/8 watt! The waveforms are shown below.

Figure 46: Waveforms for parallel termination at the load with capacitor

40

5.5 ONE DRIVER, MANY RECEIVERS, clock signals

5.5.1 Good topology:

Ideally, one should have a driver that has a low enough source resistance to drive a logic "1" level (or "0") on the first wave, and one should have all receivers (high impedance) connected with short stubs (<2 cm) to a single main line terminated at its end only.

Figure 47: "Many receivers" preferred topology

Unfortunately, receivers disturb the transmission line. The ACMOS simplest input model, for example, is:

The effect of these extra capacitances and stubs, if they are evenly distributed, is to lower the line impedance ( remember: Zo =√L/C) and to make the line harder to drive. We may then see the following waveforms (for a line delay of 2 nsec):

Figure 48: "Many receivers" possible waveforms

41

There are two problems with this situation, and surprisingly, the problems are more acute for the receivers nearest to the driver; for the first receiver, for example, 1) The delay to a logical guaranteed level "1" due to the line is ~5 nsec rather than 0. (If the

driver is weaker even more reflections may be needed. 2) Before the first reflection comes back, the line is left at 3 V, in an intermediate state for which, due to noise, multiple transitions at the receiver output may occur, things like:

For clock lines, which are edge sensitive signals, such a behavior will cause failures. Here are some possible solutions: 1) Use 2 or more drivers from the same chip connected in parallel. 2) Try to physically connect the receivers together (even if far from the driver) 3) Put a small resistor (20Ω) in the middle of the transmission line, forcing a small positive

reflection to come back right away, providing a cleaner edge.

Figure 49: Helping with a small serial resistor

5.5.2 Preferred topology: (especially for clock lines which need to reach all receivers at about the same time, i.e., without skew)

Figure 50: Preferred topology for one driver, many receivers

42

5.5.3 Dangerous topology demo Consider the following "star" connection:

Figure 51: One driver, many receivers; dangerous star topology

At node A, there is a discontinuity in the line impedance: a wave coming from any branch will see 50Ω||50Ω = 25Ω. There will be a negative reflection (25-50)/(25+50) = -1/3 = -33% in the branch and a transmission of 1 - 1/3 = 2/3 = 66% in the 2 other branches. If we go through the pain of adding up all the reflections, we get:

Figure 52: One driver, many receivers; dangerous star topology waveforms

Obviously, receiver 1 will not operate reliably because of the negative reflection back from node A.

43

5.6 DATA, CONTROL AND ADDRESS BUSSES In real life, such as with data and address busses, there are many drivers and receivers connected to the same net, only one driver being active at a time. Clearly, the simple model "one to one" developed above does not apply, if the devices are not connected in a daisy chain. It is almost impossible in that case to have guaranteed nice monotonous transitions; anyway, on address and data busses, these are not required. What we need to know though, is the stabilization delay on the net such as the one in Figure 53 below, because this delay must be subtracted from our timing margins.

DRIVER

RECEIVER 1

RECEIVER 0

RECEIVER 4

RECEIVER 3

DISPLAYCONTROLLER

EEPROM

FLASH

RAM

CPU

2004/jan/25 multipl.vsd

RECEIVER 2

Figure 53: Example of multipath net

Three practical questions arise: 1) What is the ideal source impedance 2) What is the routing strategy that will give us the smallest stabilization time ?, a star ?, a daisy chain ? 3) What will then be the worst case stabilization time (for any of the devices) ? This seemingly intractable problem can be solved for all practical purposes using the daisy chain and a little mathematics. Let us start by the daisy chain routing shown in the picture above in GREEN. We have already analyzed this simple system. and we know that the receiver closest to the driver is probably the one which will incur the largest delay. Let us assume, as a typical case, that we have a 20 cm long transmission line with an effective impedance is 50 ohms, after adding the effect of the distributed receivers capacitance (see section 5.2). The following waveforms illustrate what the closest (blue line) and the farthest (red line) receivers (# 0 & # 4) will see. We use the MATHCAD program given in Appendix 3 (section 7.5 and we consider 5 source impedances R: R = 5 such that R/Zo = 1/10, R = 25 such that R/Zo = ½, R = 50 such that R/Zo = 1, R = 100 such that R/Z0 = 2, R = 500 such that R/Zo = 10. Typical value for the driver are in fact from 15 to 50 ohms. We also assume there is no clamping at any receiver.

44

Line impedance = 50 ohms, Rsource = 5 ohms

0 5 .109

1 .108

1.5 .108

0

2

4

6

8

10Transmission line model

time (sec)

volta

ge

Vd 5 t,( )

Vl 5 t,( )

1.5

3.5

t


0 5 .109

1 .108

1.5 .108

0

2

4

6

8


time (sec)

volta

ge

Vd 25 t,( )

Vl 25 t,( )

1.5

3.5

t


0 5 .10 9 1 .10 8 1.5 .10 80

2

4

6

8


time (sec)

volta

ge

Vd 50 t,( )

Vl 50 t,( )

1.5

3.5

t

45


0 5 .10 9 1 .10 8 1.5 .10 80

2

4

6

8


time (sec)

volta

ge

Vd 100 t,( )

Vl 100 t,( )

1.5

3.5

t


0 5 .10 9 1 .10 8 1.5 .10 80

2

4

6

8


time (sec)

volta

ge

Vd 500 t,( )

Vl 500 t,( )

1.5

3.5

t

To have the fastest stabilization time, one would use a very strong driver and terminate the line into 50 ohms. Then the near receiver would stabilize in 0 nsec and the far receiver in one line delay. This is impractical though, because the termination would dissipate too much power, and drivers that strong would probably use too much real estate on the IC die. The next best stabilization time is twice as long and is obtained when the source impedance is about equal to the line impedance; the near receiver now stabilizes in 2 line delays and the far receiver in 1 line delay, like before. CPUs and FPGAs usually have source impedances between 25 and 50 ohms for that purpose.

46

Consider now another imaginary situation where a driver must be connected to n receivers using lines of total delay Td, while being free to move the receivers around. One could use a daisy chain as before, and obtain 2Td as a stabilization time. Or one could use 2 lines of length Td/2, or 3 lines of length Td/3, or even n lines of length Td/n. This is illustrated below:

multipl1.ds4

DRIVER 1

DRIVER

RECEIVER 2

2001/oct/16.ds4

RECEIVER 1

RECEIVER 1

RECEIVER 0

CASE 1: one to one net

DRIVER

RECEIVER 2

RECEIVER 0

CASE 2: one to two nets

line delay = Td

line delay = Td

line delay = Td/2

RECEIVER 1line delay = Td/2

total line delay = Td

DRIVER

RECEIVER 2

RECEIVER 0

CASE 3: one to n nets

line delay = Td/n

RECEIVER 1line delay = Td/n


RECEIVER nline delay = Td/n

CASE 4: one to n nets with random routing


RECEIVER 0

RECEIVER 3

Figure 54: Increasingly complex routing

47

Intuitively, we see that the driver sees a lower impedance as n increases; on the other hand, the reflections come back faster and compensate this effect. Again, we simulate this using again the MathCad program. The "voltage versus time" graphs show what happens when the net of length "Td" is split in n stubs (1, 2, 6 and 100) of length "Td/n".. The limit for n going to infinity is a simple formula.

Vd 1 25, t,( )

Vd 2 25, t,( )

Vd 6 25, t,( )

V i 25 t,( )

3.5

t0 5 10

91 10

81.5 10

82 10

80

2

4


time (sec)

volta

ge (v

olts

)

R = 25

Vd 1 50, t,( )

Vd 2 50, t,( )

Vd 6 50, t,( )

V i 50 t,( )

3.5

t0 5 10 9 1 10 8 1.5 10 8 2 10 8

0

2

4


time (sec)

volta

ge (

volts

)

R = 50

Vd 1 100, t,( )

Vd 2 100, t,( )

Vd 6 100, t,( )

V i 100 t,( )

3.5

t0 5 10 9 1 10 8 1.5 10 8 2 10 8

0

2

4


time (sec)

volta

ge (v

olts

)

R = 100

Figure 55: Driving in parallel n 50 ohms lines (n = 1,2,6, ∞) of length 20/n cm with a source

impedance of 25, 50 and 100 ohms

48

Looking at the simulation waveforms, we see that the case corresponding to the “one to one” net (red lines) is the one that gives the longest delays (case 1, Error! Reference source not found.). It also seems reasonable to extrapolate that even if the stubs are not the same length, or connected differently as in case 4, Error! Reference source not found., the situation at any point along the net will be better than for the “one to one” net. Even if the above reasoning does not constitute a mathematical proof, it seems highly reasonable to answer the three practical questions raised at the beginning of this section the following way: 1) The ideal source impedance is the effective transmission line impedance (taking into account the

distributed receiver capacitances) 2) The optimum routing is the one that yields the minimum total length, irrespective of the net

configuration (star, daisy chain, etc) 3) The worst case stabilization time is twice the path delay evaluated with the total net length The results could not be simpler or easier to implement: most modern drivers have source impedance of the order of the expected net impedances (25-50 ohms); the routing software should only care about minimizing the total net length, and twice the total net length is easy enough to implement. A typical 20

cm net thus incurs a stabilization time of 3.3 nsec 2*/12

20nscm

cm=

We confirmed these results with experimentation, using six 50 ohms coaxial cables totaling 43 meters (Td = 231 nsec), and trying all 4 cases in Error! Reference source not found. for R = 25, 50, and 100 ohms. The many waveforms shown on the scope correspond to different measuring points along the cables.

Figure 56: Scope waveforms obtained when driving nets with peculiar topologies

See next 3 pages (

49

multi25.ds4

DRIVER

2001/oct/18

RECEIVER 1

RECEIVER 0


DRIVER

RECEIVER 2

RECEIVER 0


line delay = Td = 231 nsec

line delay = Td/2


DRIVER

RECEIVER 2

RECEIVER 0

CASE 3: one to 6 nets

line delay ~= Td/6

RECEIVER 1line delay ~= Td/6


CASE 4: one to 4 nets~ random

DRIVER

RECEIVER 2RECEIVER 0

line delay ~= Td/3


RECEIVER 3

line delay ~= Td/6

RECEIVER 4

Td/6

Td/6

Td/6

SOURCE RESISTANCE R = 25 ohms, half the line impedance

limit for n => ∞

limit for n => ∞

limit for n => ∞

limit for n => ∞

50

multi50.ds4

DRIVER

2001/oct/18

RECEIVER 1

RECEIVER 0


DRIVER

RECEIVER 2

RECEIVER 0



line delay = Td/2


DRIVER

RECEIVER 2

RECEIVER 0


line delay ~= Td/6




DRIVER


line delay ~= Td/3


RECEIVER 3

line delay ~= Td/6

RECEIVER 4

Td/6

Td/6

Td/6

SOURCE RESISTANCE R = 50 ohms, same as the line impedance

limit for n => ∞

limit for n => ∞

limit for n => ∞

limit for n => ∞

limit for n => ∞

51

multi100.ds4

DRIVER

2001/oct/18

RECEIVER 1

RECEIVER 0


DRIVER

RECEIVER 2

RECEIVER 0



line delay = Td/2


DRIVER

RECEIVER 2

RECEIVER 0


line delay ~= Td/6




DRIVER


line delay ~= Td/3


RECEIVER 3

line delay ~= Td/6

RECEIVER 4

Td/6

Td/6

Td/6

SOURCE RESISTANCE R = 100 ohms, twice the line impedance

limit for n => ∞

limit for n => ∞

limit for n => ∞

limit for n => ∞

limit for n => ∞

limit for n => ∞

limit for n => ∞

limit for n => ∞

52

6 RULES OF THUMB

6.1 RULES OF THUMB TO MANAGE TRANSMISSION LINE EFFECTS These rules to be followed in descending order of priority:

6.1.1 Use low voltage devices if possible (3.3V, 2.5V, 1.8V).

6.1.2 Do not use faster devices than required; faster devices have shorter rise times and more crosstalk. (ACMOS rise times are 8 times shorter than HCMOS, 2 versus 16 nsec). Use devices from families where OEC (Output Edge Control) has been implemented.

6.1.3 If possible, keep total trace length (cm) shorter than 3 × rise time (nsec) to stay away from reflection effects (~ 6 cm for ACMOS, ~ 48 cm for HCMOS)

6.1.4 For signals that are edge sensitive:

6.1.4.1 If good clamping diodes are available at receivers Use a transmission line (50Ω) and a strong driver (< 23 ohms); drivers in the same chip can be paralleled.

6.1.4.2 If no good clamping diodes are available at receivers 1) Use multiples drivers and a series resistor at each driver output 2) Use one driver and a single main line with short connecting stubs and terminate the line with

clamping diodes, resistor or resistor/capacitor to ground.

6.1.4.3 For GigaHertz performance, use point to point LVDS (Low Voltage Differential Signaling)

6.1.5 For signals that are not edge sensitive, use a driver with a source impedance equal to the line impedance and minimize the total net length. The stabilization time is twice the delay that corresponds to the total net length.

Beware: a reflection too strong at a device input can cause the device to malfunction.

53

6.2 RULES OF THUMB TO MANAGE CROSS TALK EFFECTS Cross talk effects are the contamination of a signal by another one nearby. Even though the

presentation did not deal with cross talk effects, they are as important to signal integrity as transmission line effects. That is why we give a few tips here.

6.2.1 Do not use faster devices than required; faster devices have shorter rise times and more crosstalk. (ACMOS rise times are 8 times shorter than HCMOS, 2 versus 16 nsec)

6.2.2 Keep traces as far as possible from one another, and don’t have fast signals run parallel to each other for a long distance (~ 5 cm). Keep them perpendicular to one another as much as possible. Beware of parallel traces on adjacent layers. Crosstalk is less if the signals in parallel lines run in opposite directions.

6.2.3 For very high speed (GHz), balanced drivers and receivers (such as LVDS) are best to minimize cross talk. Keep balanced lines very close to one another.

6.2.4 Keep the current loops small in dimension: keep the signal between a driver and a receiver near the ground surface that joins them.

6.2.5 Use decoupling capacitors (.1, .01 or .001 uF) and ferrite beads freely.

6.2.6 One of the best practical scheme in signal integrity control is illustrated below, integrating cross talk and transmission effects control:

Figure 57: General PCB layout to control cross talk and transmission line effects

54

6.2.7 One of the best practical scheme in signal integrity control for extender boards is illustrated below, integrating cross talk and transmission effects control, and using as few possible PCB layers as possible; this simple and efficient scheme is made possible by the fact that all traces are parallel.

Figure 58: Extender PCB layout to control cross talk and transmission line effects

55

7 REAL LIFE WAVEFORMS These clocks waveforms were measured with an Infinium Agilent scope with a 1160A 10Mohms, 9pF, 1.5 m probe. When driven by a 50 ohms device, the overall system bandwidth is 500 MHz. Probing was made using very short (< 1cm) spring ground connection to a nearby ground via. (Without this precaution, the waveforms are distorted and not useful except for frequency measurements). The waveforms illustrate the importance of properly taking into account the transmission line effects. Also, cross-talk effects were almost eliminated by using a special layer enclosed between two ground planes, spreading the lines, making a ground fill and using as many vias as possible to connect the ground fill a reas with the adjacent ground planes. Note that the only important waveforms (for trouble free operation) are the waveforms measured at the receivers. Waveforms at the driver and elsewhere were taken to check and illustrate the design concept.

7.1 REAL LIFE WAVEFORMS (from CMA3000 MK2 avionics project)

7.1.1 Clock waveforms for all clocks except one All clocks except a serial IO clock are routed using the one driver - one receiver scheme as illustrated in the example below:

TRANSMI.DS42001/jul/30, 10:30

~ 30 ohms pull down~ 50 ohms pull up

discreteexternal

adaptationserial

resistorlocated

near U16

internaldriver

resistor

~ 55 ohms, 0.5 nsec transmission line

HIGH IMPEDANCERECEIVER

located in SED1386Display Controller

U11-64~ 22.1 ohms

IDT74FCT3807QIDRIVER U16

AB

C

Figure 59: Example of a one driver one receiver clock scheme (SED1386 40 MHz clock)

Here are the waveforms observed at points A, B and C.

56

Figure 60: Waveform directly at driver output (point A)

The driver sees a 77 (=55+22) ohms impedance. We see that the driver intrinsic output impedance is higher on the rising edge where the final 3V level is obtained only after the first reflection comes back.

57

Figure 61: Waveform after serial discrete resistor located near driver output (point B)

We see that the driver + resistor combination is matched to the line impedance (55 ohms). On the rising edge, it is perfectly matched since the "shoulder", which is the level of the outgoing voltage wave, is exactly half way to the final value 3V. On the falling edge, since the driver is stronger, the match is not as good.

58

Figure 62: Waveform at receiver (point C)

This is the only waveform that matters, really. We see that, as expected from the previous waveform, the rising edge is perfect and there is a slight (-550mV) overshoot on the falling edge, most probably due to the stronger driver on the "down side".

59

As a matter of fact, we made a small mistake on the original schematic for another clock (SED_PCLK_20MHZ), forgetting to put the serial resistor, and we measured a considerable negative overshoot on the waveform; after adaptation, the situation was largely corrected. See next two waveforms:

Figure 63: Measured 20MHz SED1386 at clock input pin without driver serial resistor

Figure 64: Measured 20MHz SED1386 at clock input pin with driver serial resistor

We see that the negative overshoot has disappeared and that the positive overshoot has decreased

60

7.1.2 Clock waveforms for the serial IO clock Since this clock is routed to 6 receivers (shift registers) for which the relative skew is important, a strong driver, daisy chain routing and termination resistor scheme was preferred, as illustrated below:

TRANSM1.DS42001/aug/15, 10:30

total driverinternal impedance~ 10 ohms (=~20/2)

terminationresistorlocatednear U27

~ 55 ohms transmission line, ~15 cm

3.3V 74AC04DRIVER U23

A B C

6 receivers spread ina daisy chain over ~ 10 cm

8

12

CLOCKSIGNAL

U37

2

U27

11 50ohms

Figure 65: Serial IO clock scheme

The clock frequency is 10 MHz. The original design, which had to be modified, did not have any termination resistor - we were counting (wishful thinking…) on the input protection diodes to clamp the reflections, but there were none!

61

7.1.2.1 Waveforms before adding the 50 ohms termination resistor at the last receiver

7.1.2.1.1 Waveform at the driver (U23-8) - point A

Figure 66: Measured 10MHz serial IO clock at driver output without termination resistor

7.1.2.1.2 Waveform at the first receiver, ~ 15 cm from the driver (U37-2) - point B

Figure 67: Measured 10MHz serial IO clock at first receiver input without termination resistor

62

7.1.2.1.3 Waveform at the last (sixth) receiver (U27-11) - point C

Figure 68: Measured 10MHz serial IO clock at last receiver input without termination resistor

7.1.2.2 Waveforms after adding the 50 ohms termination resistor at the last receiver

7.1.2.2.1 Waveform at the driver (U23-8) - point A

Figure 69: Measured 10MHz serial IO clock at driver output with termination resistor

7.1.2.2.2 Waveform at the first receiver, ~ 15 cm from the driver (U37-2) - point B

63

Figure 70: Measured 10MHz serial IO clock at first receiver input with termination resistor

7.1.2.2.3 Waveform at the last (sixth) receiver (U27-11) - point C

Figure 71: Measured 10MHz serial IO clock at last receiver input with termination resistor

64

7.1.3 Data bus waveforms; The routing is as shown below:

CPU

CIAASIC

FLASH

RAM

CMA3000 MK2 FLIGHT DISPLAYAND CONTROL SYSTEM

DATA62.DS42001/OCT/20

total length = 28.4 cmstripline trace with

W = .006" and b = .060"Zo = 74 ohms

driving,yellow trace

yellowtrace

Figure 72: "Real life" example of a data bus routing

65

The corresponding waveforms, as expected, were the following:

Figure 73: "Real life" example of a data bus waveform

The expected delay to get from the CPU to the ram is 28.4/12 = 2.37 nsec; we measure 2.437 nsec;

It is also clear from the yellow trace that the first reflection is enough to get the driver output to a valid logic level. The overall net delay to use in timing analyzes would thus be 2 * 2.43 nsec, or 4.9

nsec

66

7.2 REAL LIFE WAVEFORMS (from “SuperHighway” defence communications project) The signal measured is CPU_PSD_CAS generated by a PowerPC XPC8250 to drive the column inputs of 4 SDRAM ICs (Synchronous Dynamic RAM). The bus speed is 66.66 MHz (15 nsec clock)

Figure 74: Power PC SDRAM control signal at driver. Total net length is 10.7 cm

According to section 5.6, DATA, CONTROL AND ADDRESS BUSSES, for a net of 12.7 cm, we

should have a worst case stabilization time of 2 net delay, one net delay being 1.06 ns nscm

cm/12

7.12= . We

are thus expecting a stabilization time better than 2.12 nsec.

67

Figure 75: PowerPC control signal worst case stabilization time measured at the driver

The 2 nsec stabilization time (which must be added to the driver delay and rise time) is the time it takes for a useful reflection to come back.

Figure 76: PowerPC control signal waveform at the far end receiver

As expected, the signal does not show any runt or “plateau” like is seen at the driver

68

APPENDICES

7.3 APPENDIX 1: PCB STRIP LINES AND MICROSTRIP CHARACTERISTICS

69

capacitances:

for a microstrip: h

WK

LC

***84.8 ε= pF/m

Microstrip fringe factor

0

1

2

3

4

5

6

7

8

9

10

0 2 4 6 8 10 12

h/W

K

example for W = 50 mil, h = 10 mil: h/W = .2, C/L = 8.84 * 4.7 * 1.1 * 50/10 = 229 pF/m

for a stripline: b

WK

LC

***84.8*4 ε= pF/m

Stripline fringe factor

0

1

2

3

4

5

6

7

8

9

10

0 2 4 6 8 10 12 14 16 18

b/W

K

example for W = 2.6 mil, b = 2h = 20 mil: b/W = 7.7, C/L = 4 * 8.84 * 4.7 * 5 * 1/7.7 = 108 pF/m

70

7.4 APPENDIX 2: COAXIAL CABLES

73

7.5 APPENDIX 3: MATHCAD PROGRAM FOR OPEN TRANSMISSION LINE EFFECTS Michel Forté, 2001, Oct 16: transmission line delays MathCad file "line delays.mcd"

R is the source impedance and Zo is the line impedance; what really matters is R/Zo

c is the speed of light = 3*10 8 m/sec

ε is the dielectric constant of the PCB ( = 4.3)

*******************************************************************************************************************************************

If we consider the transmission line as such, with an infinite load impedance, the load will see:1) After one line delay: Vt = 2.Zo/(R+Zo)2) After three line delays: Vt = 2.Zo/(R+Zo) + 2.Zo/(R+Zo).(R-Zo)/R+Zo) where (R-Zo)/(R+Zo) is the reflection coefficient3) After n line delays, solving the geometrical series, we get, at the receiver, for a 1 volt driver:

Vt 1

R

Zo1

RZo

1

n 1

2

ZoZo

At the driver, andat receiver 0 we have: which is the same as at the receiver

minus the last reflection.Vt 1

R

Zo1

R

Zo1

n

2

Zo

R Zo

R

Zo1

R

Zo1

n

21

.ZoZo

*******************************************************************************************************************************************

74

ε 4.3 v3 108.

ε

v 1.45 108.= m/sec

d = total net length d .2 Td = line delay in seconds Tdd

vTd 1.38 10 9.=

Zo 50 ohms = intrinsic impedance R 50

n = number of stubs; effective impedance becomes Zo/n and effective net delay becomes Td/n

t 0 .02 10 9., 20 10 9...

Voltage at the end of the linefor a 5 volt driver =

Vl n R, t,( ) 5 1

R

Zo

n

1

R

Zo

n

1

floor

t

T d

n

1

2

.

Voltage at the 5 volt driver output = Vd n R, t,( ) 5 1

R

Zo

n

1

R

Zo

n

1

floor

t

T dn

21

Zo

n

Zo

nR

R

Zo

n

1

R

Zo

n

1

floor

t

T dn

2

..

Using the fact that when n goes to infinity, (1+ a/n)n = ea

Voltage at the 5 volt driver output for n very high Vi R t,( ) 5 1 e

Zo

R

t

T d.

.

The net simply behaves like a charging capacitor of time constant Td x (R/Zo)

75

8 BIBLIOGRAPHY 1- Foundations for microstrip circuit design, T. C. Edwards, John Wiley & Sons 2- Design Guidelines for Electronic Packaging Utilizing High-Speed Techniques, IPC STANDARD 1989, IPC-D-317 3- Motorola MECL handbook, HB205, REV1 4- Motorola High-Speed CMOS (HCMOS) logic data, DL129, REV 2 5- Motorola FACT (ACMOS) Data, DL138 6- Signals, Electronic Engineering Times, July 3, 2000 (New technologies for signal integrity control) 7- High-Speed Digital Design: A Handbook of Black Magic, Howard Johnson, Prentice-Hall, 1993 8- www.planetanalog.com 9- Capacitances, inductance, and crosstalk analysis, Charles S. Walker, Attach House, Boston, London.

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