transistors for ever! · ibm research 7 ibm l | data abundant systems ws april 2014 © 2006 ibm...

IBM Research

© 2006 IBM Corporation IBM l | Data Abundant System WS April 2014

1

Transistors for ever! Wilfried Haensch

IBM Research

© 2006 IBM Corporation IBM l | Data Abundant Systems WS April 2014 2

Outline

State of the art

– Devices

– Materials

– A bit of physics

CMOS compatible switches

– Tunnel FET

– Carbon electronics

Post CMOS FETs

– Graphene FETs

– Piezo FETs

More exotic stuff

– Spin for digital logic

Summary

IBM Research


Late 1920s – first patent for MESFETs

and depletion MOSFETs

1958 – first working FET

1963 – first CMOS circuit

1965 – Moore’s law

1972 – Dennard’s scaling theory

Julius Edgar Lilienfeld

(1881-1963) The Beginnings …

p substrate, doping *NA

Scaled Device

L/xd/

GATE

n+ source

n+ drain

WIRINGVoltage, V /

W/

tox/

US Patent 1,900,018. First known patent

describing a depletion mode MOSFET

http://www.google.com/imgres?imgurl=http://web.mit.edu/newsoffice/2005/lemelson-dennard.jpg&imgrefurl=http://web.mit.edu/newsoffice/2005/lemelson-dennard.html&h=205&w=154&sz=18&hl=en&start=2&tbnid=fUjyU_0JJ6RWtM:&tbnh=105&tbnw=79&prev=/images%3Fq%3Dof%2Brobert%2Bdennard%26svnum%3D10%26hl%3Den%26lr%3D%26rls%3DGGLJ,GGLJ:2006-32,GGLJ:en

IBM Research

© 2006 IBM Corporation IBM l | Data Abundant Systems WS April 2014 4 4

High m options: liner stress,

eSiGe, SMT, HOT, SSDOI, ..

Gate stack: high-k, Metal gate

Junction engineering

Body control SCE will enable

length scaling without

aggressive dielectric scaling

G

Si NW

D

5 nm Hf-based dielectric & TaN

Poly-Si SiO2

Sarunya Bangsaruntip VLSI 2009

Gate Length vs Body Thickness

0

5

10

15

20

25

30

35

40

45

0 2 4 6 8 10 12

Body Thickness, Diameter (nm)

Ga

te L

en

gth

(n

m)

GAA-cyl

SG

DG

GAA-rec

□ ○

Device Evolution

S

20 nm

m, e

Bulk

SOI

FDSOI

Back gate

Vt control

FinFET/

TriGate

ETSOI

Non planar

Doping controlled

Nano

wire

m, e m*

IBM Research


Performance: Data-driven projection

Properly-scaled III-V FETs have < 1.3 x FO3 speed with respect to Si NFETs.

When we extrapolate the most strained III-V channel to LG/ = 5, we expect ~ 1.8 x FO3 speed enhancement with respect to Si NFETs.

Increasing channel strain

IBM Research


g

0 0.5 1 1.5 20

1

2

3

4

K2s 2 0.2, t,( )

K2b 1 0.06, t,( )

K2b 1 0.02, t,( )

t

f

0 0.5 1 1.5 20

10

20

30

Ks 2 0.2, t,( )

Kb 1 0.06, t,( )

Kb 1 0.02, t,( )

t

New Materials – Scattering (Si) vs Ballistic (III/V)

Current drive advantage for

III/Vs disappears for thinner

gate dielectric

Delay advantages remains

Current drive Delay (FO3)

m* 0.2, 0.02, 0.06 ~ x 1.7

tinv tinv

L=20nm

Rext=150Wmm

Cov=0.250fF/mm

Vth=200mV

S=80mV/dec

Vdd=0.5V

Si

III/V

IBM Research


10 1

10 2

10 3

10 4

10 5

10 6

10 -2

10 -1

10 0

10 1

10 2

10 3

Delay, ps

En

erg

y, f

J

CMOS HP

CMOS LP

IIIvTFET

HJTFET

gnrTFET

GpnJ

SpinFET

STT/DW

SMG

STTtriad

STOlogic

ASLD

SWD

NML

32bit adder

Worse

Better

Fast Slow

Limited by

Capacitor charging

Steep turn-on/off (TFETs)

Limited by

spin dynamics

Magneto-electric

Potentially Nonvolatile

Switching Time and Energy (device concept)

Nikanov & Young IEDM 2013 Tutorial

IBM Research


10 1

10 2

10 3

10 4

10 5

10 6

10 -2

10 -1

10 0

10 1

10 2

10 3

Delay, ps

En

erg

y, f

J

CMOS HP

CMOS LP

IIIvTFET

HJTFET

gnrTFET

GpnJ

SpinFET

STT/DW

SMG

STTtriad

STOlogic

ASLD

SWD

NML

32bit adder

Worse

Better

Fast Slow

Limited by

Capacitor charging

Steep turn-on/off (TFETs)

Limited by

spin dynamics

Magneto-electric

Potentially Nonvolatile

Switching Time and Energy (device data)

Nikonov & Young IEDM 2013 Tutorial

IBM Research


I. Basic science - idea

II. Prototype - engineering

III. Commercialization - application

IV. Mass production - cost

Gestation for Technologies

*) after Ralph Cavin SRC

Market production (Established

Technology)

Research

Publications

Background/Infrastructure

Prototype built

Commercialization

T1~ 20years ~12 years

T2 T3

Too long!

IBM Research


The System Value Stack

Design

Architecture

Software

Technology

Device Design

IBM Research


Processor Chip Model

Key to a meaningful analysis: Realistic processor chip model

– A must to capture relative importance of technology parameters

– Activity factors, wiring vs. gates, logic vs. memory, clock power, etc...

Our work: Calibrated to IBM POWER processors

– Assume fixed # cores, each w/specified # of logic gates

– Focus on core logic: Clock/memory assumed to scale accordingly

– Assume core-to-core/core-to-memory communication not dominant

11

Treated by simple scaling from

core logic (delay, power, area)

Clock

Logic Cache

Repeaters

Treat in

detail

IBM Research


Processors: More Than Just Logic

Scale logic optimization result to full

chip w/POWER processor model

Focus: Logic technology optimization

– A full system optimization would need

separate cache and I/O models

Logic “Other” Caches, Controllers, I/O Power: L

og

ic

Clk, RF, L1

Caps/ un-

used Caches (SRAM/DRAM) Controllers, I/O, etc. Area:

Cores

Cores

0% 100%

Model scales entire chip from this core logic

12

IBM Research


Communication Dominates Power

70-80% of total logic power is for communication

– Need proper consideration of wires!!

13

0%

20%

40%

60%

80%

100%

0.5 GHz 1.5GHz 4.0 GHz

Pe

rce

nt

of

To

tal

Po

we

r

logic wire buffer dynamic buffer static

Optimized 22nm

PDSOI processors

13

Devices

IBM Research


State of the art!

Performance was boss in the past,

now power has caught up at last.

The technology itches

due to lack of new switches,

We scratch … and move on really fast!

IBM Research


Area Model

Thermal

Model

Wiring

Statistics

Fixed Parameters

Wire

Capacitance

Delay

Tolerance

Adjustments

Adjust for Latency

of Long Paths Total Power

Leakage Power

Tolerance

Adjustments

I-V Model Leakage

Model

Device Structure

Variables: Initial Guess

Constrained

Optimizer

New Values:

Improved

Guess

Processor

Chip Model

Technology Optimization Program

Frank, et al., Proc. IEEE ‘01

Frank, IBM J. R&D, ’02

Frank, IEDM ’02

Frank, et al., IBM J. R&D, ’06

Frank, et al., IEDM ‘11

Analytical models spanning

technology, circuits, and

systems

IBM Research


Area Model

Thermal

Model

Wiring

Statistics

Fixed Parameters

Wire

Capacitance

Delay

Tolerance

Adjustments

Adjust for Latency

of Long Paths Total Power

Leakage Power

Tolerance

Adjustments

I-V Model Leakage

Model

Device Structure

Variables: Initial Guess

Constrained

Optimizer

New Values:

Improved

Guess

Processor

Chip Model

Technology Optimization Program: Some trends

Frank, et al., Proc. IEEE ‘01

Frank, IBM J. R&D, ’02

Frank, IEDM ’02

Frank, et al., IBM J. R&D, ’06

Frank, et al., IEDM ‘11

Analytical models spanning

technology, circuits, and

systems

IBM Research


0.1

1

10

1.E+13 1.E+14 1.E+15 1.E+16

Performance (transitions/sec)

En

erg

y/t

ran

sit

ion

(fJ

)

FinFET III-V 2x III-V 4x

1x (=Si)

2x (~GaAs)

4x (~InGaAs)

Drive current multiplier:

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0 2 4 6 8 10 12 14 16

Frequency (GHz)

Su

pp

ly V

olt

ag

e (

V)

Fin 2x 4x

Approximate III-V benefit by increasing mobility in FET model:

Higher III-V mobility enables lower voltage

III-V FETs: Adjust m

1x (=Si)

2x (~GaAs)

4x (~InGaAs)

IBM Research


Tunnel FETs: Adjust k and m

18

Approximate TFET tradeoff by decreasing Boltzmann’s constant and

mobility in FET model:

0

500

1000

1500

2000

2500

3000

0 20 40 60 80 100

Sub-VT swing (mV/dec)

Pe

rfo

rma

nc

e (

arb

un

its

) 1x

0.6x

0.4x

0.25x

0.15x

0.04x

0.01x

0.003x

0.001x

0.0003x

Highest drive current

Lowest drive current

Mobility multiplier:

11nm Node

25W/cm2

IBM Research


Some Intuition: Si vs. III-V vs. TFET

0.01

0.1

1

10

1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

Frequency (Hz)

En

erg

y p

er

log

ic t

ran

sit

ion

(fJ

)

PDSOI 22nm

PDSOI 16nm

PDSOI 11nm

FinFET Si

FinFET GaAs

FinFET InGaAs

TET 1x

TFET 1/3x

TFET 1/10x

PDSOI

TFET (~30mV/dec)

FinFET

High-freq

III-V: A little boost for high-freq applications

TFET: A win for low-freq application only w/FET-like Ion

Low-freq

Hacking generic FET model:

III-V: Adjust m

TFET: Adjust k, m

IBM Research


Outline

State of the art

– Devices

– Materials



– Tunnel FET


Post CMOS FETs

– Graphene FETs

– Piezo FETs

More exotic stuff


Summary

IBM Research


Tunnel FETs – beat the 60mV/dec SS limit

Need Con Solution

EG Small band

gap for high

Ion

Large band

gap for low

Ioff

Hetero

Structures

with

appropriate

band off sets

m Small tunnel

mass for

high Ion

(band-to-

band

tunneling)

Large tunnel

mass for low

Ioff (S/D

tunneling)

Hetero

structures with

large channel

mass

Small tunnel

distance for

high Ion

Planar

multigate

Wire, CNT

G

G

EmGE

EB

G

eE

eE

EI

2

32

~~

3

IVVDV

VS

dsgsgs

gs~

),(2~

2

S

Vgs

S= 60mV/dec

Log Ids

High Vth low

power space

Krishna K. Bhwalka et al. 2005

IBM Research


Ion is the problem

105 103 104

Vds swing ~ 0.5V

Vgs swing is 1.5V

Proper comparison

needs same swing on Vds

and Vgs

Ionesco IEDM 2013 Tutorial Ionesco IEDM 2013 Tutorial

106

IBM Research


Ion is the problem

Ionesco IEDM 2013 Tutorial

Vdd=0.5V fixed lkg

105 103 104 106

IBM Research


Ion is the problem


Vdd=0.5V fixed lon

105 103 104 106

IBM Research


G. Zhou et al, EDL 33,2012

32nm HP at 0.5V

Ion is the problem


105 103 104 106

IBM Research


Model predictions at 5nm node

Ion ~ 10mA/mm at 10pA/mm lkg

U. Avci et al. IEDM 2013

No PFET advantage

IBM Research


Model predictions at 5nm node Ion ~ 10mA/mm at 10pA/mm lkg

U. Avci et al. IEDM 2013

g g

0 0.5 1 1.5100

1 103

1 104

1 105

1 106

1 107

1 108

1 109

Ron_off Vdd 2, 0.090, ( )

Ron_off Vdd 2, 0.04, ( )

Ron_off Vdd 4, 0.09, ( )

Ron_off Vdd 4, 0.04, ( )

Ron_off Vdd 8, 0.09, ( )

Ron_off Vdd 8, 0.04, ( )

Vdd

0 2 4 6 81 10

6

1 104

0.01

1

100

Ioff_2 beta L 103

, 106

Ion_2 0.3 0.3, beta, 0.09, L, ( ) 106

Ion_2 0.3 0.3, beta, 0.04, L, ( ) 106

beta

=4

=2

g g

0 0.5 1 1.5100

1 103

1 104

1 105

1 106

1 107

1 108

1 109

Ron_off Vdd 2, 0.090, ( )

Ron_off Vdd 2, 0.04, ( )

Ron_off Vdd 4, 0.09, ( )

Ron_off Vdd 4, 0.04, ( )

Ron_off Vdd 8, 0.09, ( )

Ron_off Vdd 8, 0.04, ( )

Vdd

0 2 4 6 81 10

6

1 104

0.01

1

100

Ioff_2 beta L 103

, 106

Ion_2 0.3 0.3, beta, 0.09, L, ( ) 106

Ion_2 0.3 0.3, beta, 0.04, L, ( ) 106

beta

Ioff

Ion

S=90mV/dec

Ion

S=40mV/dec

I (m

A/m

m)

Vdd=300mV

I on/I

off

S=90mV/dec

S=40mV/dec

High

Performance

Ultra Low Power

3.2

21

passive

active

th

P

P

SV8

passive

active

P

P

IBM Research


0.1

1

1.E+08 1.E+09 1.E+10

Frequency (Hz)

Su

pp

ly V

olt

ag

e (

V)

TFET FinFET

FinFET

TFET

1

10

100

1.E+08 1.E+09 1.E+10

Frequency (Hz)

Dim

en

sio

n (

nm

)

TFET diam FinFET tsi FinFET h

Fin height

TFET diameter

Fin width

Optimizing InAs/GaSb TFETs

28 28

Combine TFET model with InAs/GaSb band structure

– IBM internal tool for band structure calculations [S. Laux]

Optimization w/proper model defines practical TFET targets:

– Target TFET Vdd are lower than FinFET

– Fin pitch can be tighter than TFET nanowire pitch, indicating lower

integration density for TFETs

Solomon, et al., DRC ‘11

IBM Research


Carbon Electronics - Material properties

29

Graphene Carbon Nanotube (CNT) Buckyball (C60)

http://www.nano-enhanced-wholesale-technologies.com/faq/carbon-forms.htm

s

cmv f

810

1*,

dmEg

Carbon Nano Tube

10 times faster than Si!

(n,m) chirality

IBM Research


Graphene (Eg=0) vs CNT (Eg ≠ 0)

Ion/Ioff < 10

10-11

10-10

10-9

10-8

10-7

10-6

10-5

I d (

A)

-1.0 -0.5 0.0 0.5Vgs (V)

Vds = -0.4 V

Lch = 9 nm

Lch = 18 nm

Lch = 41 nm

Lch = 320 nm

dCNT = 1.3 nm

Ion/Ioff ~ 104

14

12

10

8

6

4

2

0

I d (µ

A)

-0.4-0.3-0.2-0.10.0Vds (V)

Vgs - Vth = -0.9 V to 0.1

in 0.2 V steps

Perfect scalability CNT Lg=9nm

Low gain G= gm/gd

Low Ion/Ioff ratio

Current saturation provides high gain

IBM Research


0

500

1000

1500

2000

2500

3000

14nm

10nm 7n

m5n

m

CNT_a

s is

CNT_o

pt

CNT_o

pt

CNT_o

pt

Ids

at

(uA

/um

)

500

600

700

800

900

1000

Vd

d (

mV

)

Id sat

Vdd

Si Roadmap

14

12

10

8

6

4

2

0

I d (µ

A)

-0.4-0.3-0.2-0.10.0Vds (V)

Vgs - Vth = -0.9 V to 0.1

in 0.2 V steps

Projected 5nm design point • GC pitch 36nm • Lg ~ 12nm • Idsat = 1600uA/um at Vdd = 750mV

CNT at 8nm pitch exceeds ITRS

targets • Idsat = 798uA/um at Vdd=750mV • With optimized device (emb. gate)

−Idsat= 2593uA/um at Vdd=750mV −Idsat= 1600uA/um at Vdd=600mV

2011 scaling result • Lg ~ 9nm • Ion/Ioff ~ 104

• No optimized Rext

ITRS roadmap (HP)

0

10

20

30

40

50

60

70

80

90

14nm

10nm 7nm

5nm

CNT_a

s is

CNT_o

ptCNT_o

ptCNT_o

pt

CP

P (

nm

), L

g (

nm

)

CPP

Lg

IBM Research


0

200

400

600

800

1000

1200

14nm

10nm 7n

m5n

m

CNT_a

s is

CNT_o

pt

CNT_o

pt

CNT_o

pt

Ids

at

(uA

/um

)

500

600

700

800

900

1000

Vd

d (

mV

)

Id sat

Vdd

Si Roadmap

14

12

10

8

6

4

2

0

I d (µ

A)

-0.4-0.3-0.2-0.10.0Vds (V)

Vgs - Vth = -0.9 V to 0.1

in 0.2 V steps

Projected 5nm design point •GC pitch 36nm • Lg ~ 12nm • Idsat = 533uA/um at Vdd = 750mV

CNT at 8nm pitch exceeds ITRS

targets • Idsat = 204uA/um at Vdd=750mV •With optimized device (emb. gate)

−Idsat= 1018uA/um at Vdd=750mV −Idsat= 534uA/um at Vdd=640mV

2011 scaling result • Lg ~ 9nm • Ion/Ioff ~ 104

• No optimized Rext

ITRS roadmap (LP)

0

10

20

30

40

50

60

70

80

90

14nm

10nm 7nm

5nm

CNT_a

s is

CNT_o

ptCNT_o

ptCNT_o

pt

CP

P (

nm

), L

g (

nm

)

CPP

Lg

IBM Research


Full Chip Optimization

33

0.01

0.1

1

10

1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

Frequency (Hz)

En

erg

y p

er

log

ic t

ran

sit

ion

(fJ

)

PDSOI

III-V TFET

FinFET CNTFET

Magic TFET (m*=.02, d=4nm)

Data above: An optimistic upper bound of CNTFETs/TFETs?

– Will the benefit be worth the development risk/cost?

– High-frequency vs. low-frequency applications?

IBM Research


Technology Requirements for 5 nm Node

Accurate placement of CNTs at 8 nm pitch

6 CNTs per device at high purity (no metallic CNTs) ~ < 3×10-6

Reliable transistor action at sub 10nm gate length

8 nm

30 nm

IBM Research


Contact scaling

35

Hero device!

Typically reported contact length is around 300nm

Need more focus on smaller contacts in the sub 20nm regime

IBM Research


Power performance optimization with correct contact scaling

0.1

1

10

1.E+09 1.E+10 1.E+11

Frequency (Hz)

En

erg

y (f

J)

22nm

14nm

10nm

7nm

5nm

3.5nm

2.5nm

1.7nm

1.2nm

7nm CNFET

5nm CNFET

3.5nm CNFETdL

nmkR

c

ext

267 W

FinFET

22nm …

CNT

7nm, 5nm, 3.5nm node

x5

IBM Research


Optimizer cross check

)),(2,),((0),(

1

1ln),(

2

0 2

1

2

1

0 extdgdextdggdg

k

kT

VE

kT

E

q

dg RVVIVRVVIVIVVI

e

e

qR

kTVVI

dkgsfs

kgsfs

e

e

eFs

Ev

Vgs Id Vds

Ec

eFd

E0

- -

Vs=0

ssdsgssfdsfs

kE kT

qgsf

g

f

g

g

fjg

CCVgCVgQQ

e

EgdqQ

Ev

Eg

E

nmd

mnjd

vE

mnmna

d

kg

fsk

j

j

ee

eee

e

e

e

ee

)()(),(),(

1

1),(),(

2

12

8),(

....eV ,434.2 ,217.1 ,609.0

4.1

)(3

122

)(3

2

0

2

1

2

2

22

IBM Research


γ 0.5:

0.2 0 0.2 0.40

5

10

15

I2 0.9 BB Vd1, γ,

10

6

I2 0.7 BB Vd1, γ,

10

6

I2 0.5 BB Vd1, γ,

10

6

Id_dat

Vd1 Vd1, Vd1, Vd_dat,

εfs 0.4

Rq 6.5 103

gaps0

0.609

BB 0.250

QG 5.0

QD 0.11

T0 300 QS 1

Vdd 0.5: L 0.010 P 1000 Ilk 32:

S 89300

300

:

y 1:

Model Calibration

14

12

10

8

6

4

2

0

I d (µ

A)

-0.4-0.3-0.2-0.10.0Vds (V)

Vgs - Vth = -0.9 V to 0.1

in 0.2 V steps

Match source and drain coupling to fit SCE : DIBL & SS

IBM Research


Comparison with optimizer

CNT diameter and Rs taken from optimizer results

– Modified work function to hit off current

– Modified effective gate capacitance to hit on current

Reasonable agreement of data based model with optimizer device!

Parameter Data

Lg 10

Gate bottom

Lc long

d 1.4 1.13 1.13 1.74 1.74

Cg (fF/mm) 0.118

Tdiel 3 2 2 2 2

eps diel 5

Rext W/cnt 5000 5500 5500 4100 4100

Vdd (V)

Ioff (nA/cnt) 32 32 108 108

Ion mA/cnt) 13 13.7 7.6 7.9Ieff (mA/cnt) 7.9 7.6 4.7 4.4

10 10

0.74 0.93

0.5 0.31

Opt1 Opt2

short short

20 20

GAA GAA

IBM Research


Rext - Data versus Model (Pd)

0

5

10

15

20

25

30

35

40

45

1 10 100 1000

Lc (nm)

Rc (

kO

hm

/ sid

e)

mod_260

mod_120

mod_65

Rc_Pd

Need reduction by x 2 to 3

Need a factor 2 to 3 improvement in contact resistance to obtain

power / performance benefit predicted by optimizer

10

s

c

sext R

dL

RR

IBM Research


0.1

1

10

1.E+09 1.E+10 1.E+11

Frequency (Hz)

En

erg

y p

er

tra

ns

itio

n (

fJ)

Rs=67 Rs=120 Rs=250

Impact of Rext at 5nm node

1

1.5

2

2.5

3

1.E+09 1.E+10 1.E+11

Frequency (Hz)

CN

T D

iam

ete

r (n

m)

Rs=67 Rs=120 Rs=250

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

1.E+09 1.E+10 1.E+11

Frequency (Hz)

Su

pp

ly V

olt

ag

e,

VD

D (

V)

Rs=67 Rs=120 Rs=250

Fin envelope

dL

nmkRR

c

sext

2W

Design space provides Rext and CNT

diameter trade-off

IBM Research


10

100

1000

1 10 100 1000

Lc (nm)

Re

xt

(Oh

m u

m /

sid

e)

Rext – comparison with Si technology

1s

CNTc

soc R

DL

RR

Rs0=65kW nm2

120 250

rc=2Wmm2

0.65 0.1

Si contact scaling

CNT contact scaling

(empirical)

Rext versus contact length

CNTs face a similar contact scaling challenge as Silicon, however only

Rc has to be reduced no extension or spreading resistance component

to Rext

CNT

Si d

cT

extension

T

c

T

cext

RL

RL

L

LR

r

r

coth

5nm node

today

IBM Research


Outline

State of the art

– Devices

– Materials



– Tunnel FET


Post CMOS FETs

– Graphene FETs

– Piezo FETs

More exotic stuff


Summary

IBM Research


Post CMOS logic Switch should have …

High drive current at sufficient low voltage

Sufficient On/Off ratio

Gain to restore signals

Input / Output isolation

Scalability

… if we continue along the path of combinatory logic

IBM Research


BisFET

Spontaneous coherence (BOSE-Einstein Condensate)

55.0

25.2

4

2

F

q

e

Vacuum

SiO2

Sodemann, Pesin, MacDonald Phys. Rev B 2012

n=p GaAs/AlGaAs double quantum wells

low temperatures,

presence of a magnetic field.

Eisenstein,MacDonald, Nature 432, 691 (2004).

IBM Research


BisFET

Initial predictions

VG

nVn

VG

p

Vp

Vds

Ids

MOSFET

BisFET

Graphene

electrons

holes

VG

nVn

VG

p

Vp

VG

nVn

VG

p

Vp

VG

nVn

VG

p

Vp

Vds

Ids

MOSFET

BisFET

Graphene

electrons

holes

Low voltage high performance

– Predicted supply voltage as low as 25mV at 100GHz clock frequency at 0.008aJ (inverter)

– Pulsed logic different from traditional CMOS operation

– Requires multiphase clock, providing clock is still a problem to achieve low power potential

0

0.2

0.4

0.6

0.8

1

0 0.5 1 1.5 2 2.5

alpha

2*d

ela

ta/E

_F

unscreened

screened

SiO2 Vaccum

kFd 0

Initial estimates

Banerjee et all, IEEE EDL, 30 (2) 158-160 (2009)

IBM Research


BisFET

Better understanding of BEC formation

VG

nVn

VG

p

Vp

Vds

Ids

MOSFET

BisFET

Graphene

electrons

holes

VG

nVn

VG

p

Vp

VG

nVn

VG

p

Vp

VG

nVn

VG

p

Vp

Vds

Ids

MOSFET

BisFET

Graphene

electrons

holes

Screening implies

– BEC needs to be imbedded in low e material

– Gates need to be removed from BEC (requires larger gate voltages)

– Critical density is controlled by control gate, to avoid switching of large voltages

0

0.2

0.4

0.6

0.8

1

0 0.5 1 1.5 2 2.5

alpha

2*d

ela

ta/E

_F

unscreened

screened

SiO2 Vaccum

kFd 0

screened unscreened

Register et al. ECS Transactions, 45 (4) 3-14 (2012)

Sodemann, Pesin, MacDonald Phys. Rev B 2012

IBM Research


Graphene pn junction

Over coming low Ion/Ipoff ratio of

graphene FET by introducing

energy filter function

Tilted junctions

Physical transport gaps R.Sajjad, A.Ghosh, Applied Phys. Lett. (2011); R, Sajjad, A. Ghosh,

arXiv:1305.7171 (2013).

IBM Research


Graphene pn Junction

2112

1

2211

),/(sin

sinsin

nnnn

nn

B

2112

1

2211

),/(sin

sinsin

eeee

ee

c

x

Klein tunneling

– Energy conservation

– ky-conservation

– Jx(x) conservation kx -kx, vx vx

– Conservation of pseudo spin no back scattering

E(x)

E

E

Ef

kx

kx

x e1

e2

x

y

op

tics

Kle

in tu

nn

elin

g

IBM Research



Transmission through pn junction

|VG1|= |VG2|

1

2

3 e

e

1 2

1

sinC

E(x)

E E

Ef

kx

kx qVj<0 ENP=-qVj

x

2

1 1010

1 1011

1 1012

1 1013

0

50

100

c 5 1012

5

n10

12,

180

5

n10

12

212105 cmn

p (cm-2)

c

IBM Research




|VG1|= |VG2| |VG1|> |VG2|

1

2

3 e

e

1 2

1

sinC

1

2

3

E(x)

E E

Ef

kx

kx

qVj<0

ENP=-qVj

x

E(x) E

E

Ef

kx

kx

qVj<0

ENP=-qVj

x

2

1 1010

1 1011

1 1012

1 1013

0

50

100

c 5 1012

5

n10

12,

180

5

n10

12

212105 cmn

p (cm-2)

c

IBM Research




|VG1|= |VG2| |VG1|> |VG2| VG2 = 0

1

2

3 e

e

1 2

1

sinC

1

2

3

1

2

3

E(x)

E E

Ef

kx

kx qVj<0 ENP=-qVj

x

E(x)

E E

Ef

kx

kx

qVj<0

ENP=-qVj

x

2

1 1010

1 1011

1 1012

1 1013

0

50

100

c 5 1012

5

n10

12,

180

5

n10

12

212105 cmn

p (cm-2)

c

E(x) E

E

Ef

kx

kx

qVj<0

ENP=-qVj

x

IBM Research


Graphene pn junction

c

2

1 1010

1 1011

1 1012

1 1013

0

50

100

c 5 1012

5

n10

12,

180

5

n10

12

212105 cmn

p (cm-2)

c

212105 cmp90º

OFF

B

C> B

C< B

IBM Research


Piezo Electric FET

In a mechanically clamped structure, the resulting pressure drives

an insulator metal transition in a piezoresistive (PR) film,

allowing a current, IS to flow – hence low RC time.

The area ratio aPR/APE << 1 steps up the pressure in the PR.

Supply voltage Scales with geometry & material properties

PR

PEPR

G

Y

L

A

a

Y

l

Vdp

33

VG

d33

IBM Research


Piezo Electric FET – fast low voltage switch

Desirable

Corner

Faster switching in

smaller devices

Inte

r sta

ge d

ela

y (

ps)

L=13.3nm

L=26.6nm

High performance, low supply voltage and high fan-out

capable

Piezo Electric FET is a CMOS compatible switch with

equivalent scaling rules

sound

L

IBM Research


(b)

Ir tipped

PR pillars

Sapphire

plate

IND

EN

TO

R

PR

substrate

metal

Plate

Spacer

support

array

PZ

T

AC

TU

AT

OR

Actuator

area

Ir

landing

pad

PR

RE

CE

IVE

R

Processed Sapphire Plate

sapphire plate

Indenter ball

0 -2 -4 -6 -8 -10 -12 -14 -16 -18

1E-7

1E-6

PR

Conducta

nce (

S)

VG (V)

Indentor

Displacement

(mm)

0

1

2

3

VD = +/- 100 mV

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0

-10µ

-5µ

0

5µ

10µ

-4

VPIEZO =:Indentor Displacement = 1 mm

SP displacement ~ 0.6 nm

Cu

rre

nt (A

)

Voltage (V)

0

-16-12

-8

GATE CHARACTERISTICS DRAIN CHARACTERISTICS

Piezo Electric FET – first device demonstration

IBM Research


Outline

State of the art

– Devices

– Materials



– Tunnel FET


Post CMOS FETs

– Graphene FETs

– Piezo FETs

More exotic stuff


Summary

IBM Research


Computing with Alternate State Variables

Many different device ideas being considered – some

‘likely’ attributes compared to CMOS

– Slower

– Denser / 3D

– Local interconnect focused

– Uniform arrays / sea-of-gates

– Variability still an issue

Architecture / System Question

– How to get high computation throughput with these attributes?

• Impact on software stack, legacy software

– Can we walk away from pushing single thread performance?

Proof of concept?

‘Switch’ ~ msecs

~108 MIPs

~30W

IBM Research


Propagation Velocities

Medium Vel.

(cm/s)

TOF

(-/mm)

TOF

(-/nm)

Electro-magnetic (Light)

TEM (metal wire)

2x1010

2x1010

5 ps

5 ps

electrons (crystal max.)

electrons (Si)

~108

107

1 ns

10 ns

10 fs

Spin Wave 106 100 ns 0.1 ps

Sound 5x105 200 ns 0.2 ps

Bio – reflex arc 5x103 20 ms

Bio – brain short-range 1 100 ms

E/M propagation has huge

speed advantage over all

others*.

How does the brain do so

much at such slow speeds?

– Huge architectural and

algorithmic efficiencies

Slow speeds are still useful

at intra-device (nm)

distances.

* Propagation down wires is a special case, Transverse Electric and Magnetic fields, with no long wavelength cut-off.

IBM Research


Considerations for spin logic operation

60

A controlled spin-current propagation scheme with high-density, high-speed operation in mind.

– “Spinwire” with lo loss coupling to the switch and low dissipation

A spin-signal-based amplifier with good saturation characteristics for signal-leveling.

Dissipation-less spin current-based logic only make sense if the volume of logic operation is performed in spin-space.

Alternatively, one has to go beyond von Neumann architecture. Concrete designs are still needed.

IBM Research


Considerations for spin logic operation

61

Speed: <tsw> (I – Ic0) of ~ 1 pA-sec (at 40nm-ish. Scales down with bit volume linearly).

Reliable logic state definition

– thermal barrier height Ic0 (1mA/kBTambient).

– Thermal broadening: Needs I >> Ic0 for 10-15 BER operation, depending on barrier height.

On-off ratio: likely limited by magnetic thermal fluctuations of the electrodes (unlikely to go beyond 1:100).

1 20:t0 0.425:

1 103

0.01 0.1 1 101 10

151 10

141 10

131 10

121 10

111 10

101 10

91 10

81 10

71 10

61 10

51 10

41 10

30.01

0.11

wer2 t t0, 1000, 1,( )

wer2 t t0, 100, 1,( )

wer2 t t0, 10, 1,( )

t

I/Ic0=10

1000

100

W sc MI 0

wer

Write time (ns)

(for spin torque switching)

K Munira, W H. Butler, and A W. Ghosh TED 2012

IBM Research


Summary State of the art

– Conventional devices will be carry the industry to the 7nm node

– To address power constraints supply voltage needs to de reduced, possibly to a lower limit of 0.5V

– High mobility channel materials might help, will possibly be used in relaxed density compared to silicon devices


– Tunnel FETs are elusive – what limits the on current? Is this fundamental

– CNTs seem to be the best match for CMOS operation. Most beneficial in low voltage operation. Purity & placement a major hurdles to overcome

Post CMOS FETs

– BisFET and pn jct offer the potential for low voltage operation. However device concept not yet demonstrated

– Piezo FET is a transducer ( mechanical electrical) device that would allow low voltage operation. Scaling properties are intriguing.

More exotic stuff

– Spin has its place for memory. For digital logic not there yet.

IBM Research


The roadmap in three stanzas!

At the beginning there were …

Sirs Walter and William and John

They had the ultimate fun

They conceived a device

That worked pretty nice

And the Si days had begun

… and along came Moore …

Gorden the knight from the west

Thought, I can explain it the best

He looked at the trend

It never did bend

So it is exponential at best! How small can we go?

Nano is pretty darn small

Its magic captures us all

Going smaller at last

Will continue the past

But remember - in the end there is nothing at all

transistors for ever! · ibm research 7 ibm l | data abundant systems ws april 2014 © 2006 ibm...

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