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PRINCIPLES AND APPLICATIONS OF ELECTRICAL ENGINEERINGPRINCIPLES AND APPLICATIONS OF ELECTRICAL ENGINEERINGTHIRD EDITION

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9Transistor Fundamentals

C H A P T E RC H A P T E R

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Figure 9.1 Controlled-source models of linear amplifier transistor operation

i ini in

(a) Current-controlled current source (b) Voltage-controlled voltage source

(d) Current-controlled voltage source(c) Voltage-controlled current source

v invin

v in iin

+

_

iin

+

_

v in

+_

+_

r i

ri

ro

ro

ro

ri

r iro

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Figure 9.2 Models of ideal transistor switches

iin

Voltage-controlled switch

Current-controlled switch

iin

vin v in

+

_

iin 0

vin 0vin 0

iin 0

+

_

ri

ri

ri

ri

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Figure 9.4 Bipolar junction transistors

Collector

Base

Emitter Circuit symbols

B

E

C

pnp transistor

p+

n

Collector

Base

Emitter Circuit symbols

B

E

C

npn transistor

p

n+

p n

B

E

C

B

E

C

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Figure 9.10 Determination of the operation region of a BJT

R B

40 k

E

B

C

RC

V CC

1k

RE

500

V BB

12 VV 1

V 2

V 3

4 V

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Figure 9.12 A simplified bias circuit for a BJT amplifier

IB

I BB

E

B

C

VBE

+

_

I C

+

_VCC

VCE

RC

By appropriate choice of I BB , RC and VCC , the desired Q point may be selected.

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Figure 9.13 Load-line analysis of a simplified BJT amplifier

0 1 2 3 4 5 6 7 8Collector-emitter voltage, V

9 10 11 12 13 14 15

IB = 250 A

QIB = 200 A

I B = 150 A

IB = 100 A

IB = 50 A

05 m

10 m15 m20 m25 m30 m35 m40 m45 m50 m

Col

lect

or c

urre

nt, A

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Figure 9.15 Circuit illustrating the amplification effect in a BJT

I B + I B

VBB

E

B

C

VCC

R C

R B

+_~

I C + IC

VB

+

–

VCE + VCE+

–

V BE + VBE

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Figure 9.16 Amplification of sinusoidal oscillations in a BJT

50

00 5 10 15

VCE (V)

IC (mA)

I B = 230 A

190 A

150 At

75 A

t

Q28.6

15.3 110 A22

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Figure 9.20 Practical BJT self-bias DC circuit

R1

R2

RC

RE

VCC

I B

I C

I E

VCE–

+

VBE–

+

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Figure 9.21 DC self-bias circuit represented in equivalent-circuit form

VCC

R1

R2 VCC RE

RC

VBBVCCIE

RC

VCE

_

+

VBE

+

_RB

IC

IB

IC

VCE

_

+

RE IE

VBE

+

_

IB

(a) (b)

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Figure 9.22 npn BJT large-signal model

IB = 0B

C

E

ICEO

VBE VIB = 0IC = ICEOVCE 0

Cutoff state conditions: IB

B

C

E

I C

VBE = VIB 0IC = IBVCE V

Active state conditions:

B

C

E

VBE = VIB 0IC IBVCE = Vsat

Saturated state conditions:

+V

+V

IB Vsat

+

IC

–

–

–

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Figure 9.30(a) An n-channel MOSFET is normally off in the absence of an external electric field

Source

Bulk (substrate)

Drain

Gate

n+ n+p

D iD

VDS VDDVDDG

S

_ +_

+_

+

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Figure 9.30(d) If the drain and gate supply voltages are both varied a family of curves (shown in Figure 9.31(b)) can be generated, illustrating the MOSFET cutoff, ohmic, saturation, and breakdown regions

D iD

VDS

VGS

V DD

G

S

_

_

+_

+

+VGG +

_

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Figure 9.32 n-channel enhancement MOSFET circuit and drain characteristic for Example 9.8

iD (mA)

vGS = 2.8 V

2.6 V

2.4 V

2.2 V

2.0 V

1.8 V1.6 V1.4 V

vDS (V)

100

80

60

40

20

00 2 4 6 8 10

VGG VON

RD

v GS

vDS

iDD

G

S

+

––

+

Q

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Figure 9.40(a) When the gate-source voltage is lower than -Vp, no current flows. This is the cutoff region

Source Drain

Gate

nChannel

p

p

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Figure 9.40(b) For small values of drain-source voltage, depletion regions form around the gate sections. As the gate voltage is increased, the depletion regions widen, and the channel width (i.e., the resistance) is controlled by the gate-source voltage. This is the ohmic region of the JFET

Source Drain

depletionregions

Gate

n Channel

p

p

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Figure 9.40(c) As the drain-source voltage is increased, the depletion regions further widen near the drain end, eventually pinching off the

channel. This corresponds to the saturation region

Source Drain

Pinched-offchannel

Gate

n Channel

p

p

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Figure 9.41 JFET characteristic curves

0 1.0 2.0 3.0 4.0 5.0

Drain-source voltage, V

6.0 7.0 8.0 9.0 10.00

800 u

2 m

2 m

3 m

4 m 0 V

– 0.5 V

–1.0 V

–1.5 V

–2.0 V–2.5 VVGS = –3 V

Dra

in C

urre

n t, A