track a: 2.5d/3d chip stacking supply chain integration/ kurt huang, ph.d
DESCRIPTION
TRANSCRIPT
![Page 1: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/1.jpg)
2.5D/3D Chip Stacking Supply Chain Integration
Kurt Huang, Ph.D.
Director, Corporate Marketing, UMC
ChipEx, 2013
![Page 2: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/2.jpg)
Outline
2.5D/3D Applications
Ecosystem Work Flow
Summary
P. 2
![Page 3: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/3.jpg)
2.5D/3D Applications
![Page 4: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/4.jpg)
2.5D Si Interposer Stacking
Logic/logic: FPGA, networking infrastructure
Logic/memory: Gaming, HPC
![Page 5: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/5.jpg)
3D Logic/Memory Stacking- Via-Middle TSV 28nm Logic + Memory Cube
Mobile WideIO, Computing WideIO, HMC
![Page 6: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/6.jpg)
Never-Enough Memory Bandwidth- Mobile AP Driving Wide IO Memory
Dimensioning use case: 3D video streaming playback to external display via wireless
+ on-line 3D gaming local
![Page 7: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/7.jpg)
Keeping Power Under Hood
•LPDDR3 @800Mhz dual-channel
•LPDDR3 @800Mhz
![Page 8: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/8.jpg)
Real Value Drives Adoption
Motivations:
Higher BW, lower W/BW, smaller form-factor
Opportunity of return on 3D IC investment:
Chip process node optimization Homogeneous partition Cross-node combinations
BOM cost optimization Less demanding substrate/PCB,
lighter cooling assembly, ...
Ultimately: better product, better margin
Xilinx Virtex 7
Micron HMC
![Page 9: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/9.jpg)
Application Examples
![Page 10: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/10.jpg)
Market Segment Overview
High performance driving 2.5DIC
Mobile AP driving 3DIC SoC + Mobile Memory
Next wave: heterogeneous 3DIC Logic + Memory +
Analog/RF Ecosystem more
complex Expect driving force
emerges after 3DIC matures
![Page 11: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/11.jpg)
Ecosystem Work Flow
![Page 12: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/12.jpg)
Example 2.5D Stacking Flow
![Page 13: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/13.jpg)
Various Work Models
Service scopes distinguished by MEOL inclusion Consult your foundry/OSAT
Work flow optimization may depend on BOM cost, stack recipe and test strategy
![Page 14: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/14.jpg)
Foundry TSV Design Collaterals
Consider TSV a passive device with rule decks/models Typical foundry engagement applies under ecosystem work flow
(UMC 2.5D Si interposer documents)
![Page 15: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/15.jpg)
Innovations by Open Eco-System Wafer thinning and handling
Thermal/stress
consideration
Testability
Reliability
3D EDA tool
Seamless business model
Cost
…
![Page 16: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/16.jpg)
Evolution Of the Supply Chain Technology exploration Feasibility study
Interface definition Handover criteria
Model convergence Flow standarization Cost down
Service differentiation Further innovation
![Page 17: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/17.jpg)
UMC Ecosystem Effort
1Q12
2Q12
1Q13
2Q13
![Page 18: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/18.jpg)
Summary
![Page 19: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/19.jpg)
Summary Foundry TSV process demonstrated
Applicable to both 2.5D/3D Leverage existing CMOS process technology Key process issues identified & conquered
Ecosystem work flow Typical foundry/OSAT engagement flow applies for both
2.5D/3D, among other models
Foundry TSV next step: ecosystem focus Product level reliability assessment 3D package level reliability demonstrated for open
ecosystem model Potential EDA collaboration for emerging 3D tools
![Page 20: TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D](https://reader035.vdocuments.site/reader035/viewer/2022062417/5491bcecb479598e6a8b54f5/html5/thumbnails/20.jpg)
BTW, Dreams Do Come True!