[total marks: 75] compulsory state the assumptions same … · (2½ hours) [total marks: 75] n. b.:...
TRANSCRIPT
(2½ Hours)
[Total Marks: 75]
N. B.: (1) All questions are compulsory.
(2) Make suitable assumptions wherever necessary and state the assumptions made.
(3) Answers to the same question must be written together.
(4) Numbers to the right indicate marks.
(5) Draw neat labeled diagrams wherever necessary.
(6) Use of Non-programmable calculators is allowed.
1. Attempt any three of the following: 15
a. Convert the following.
(i) (1051.36)10 = (?)8
Divide the integral part by 8 and multiply the fractional part with 8.
(1051.36)10 = (2033.27024)8
(ii) (F9A.D5)16 = (?)10
Multiply the hex number with powers of 16
(F9A.D5)16 = (3994.83203)10
b. What is Hamming code? A seven bit even parity hamming code is received as
1110101. What is the correct code?
Hamming code does not only detect the errors in the code but also corrects it. The basic
of hamming code is it uses parity bit, set for even parity over a selected bits.
D7 D6 D5 P4 D3 P2 P1
1 1 1 0 1 0 1
P4 = P4 D5 D6 D7 = 0111(odd parity) So P4=1
P2 = P2 D3 D6 D7 = 0111(odd parity) So P2=1
P1 = P1 D3 D5 D7 = 1111(even parity) So P1=0\
So P4P2P1 = 110 = (6)10. So the 6th bit is changed from 1 to 0.
Correct code = 1010101.
c. Certain number system has base 7. What is the hexadecimal equivalent of the
minimum and maximum number that is expressed using the base 7 and four bits?
Minimum number with base 7 expressed in 4 bits = (0000)7
Hex equivalent = (0000)16
So Minimum number = (0000)7= (0000)16
Maximum number with base 7 expressed in 4 bits = (6666)7
To find hex equivalent, we first need to convert it into decimal
(6666)7 = 6 x 73 + 6 x 72 + 6 x 71 + 6 x 70 = (2400)10
Now converting decimal to hex, we get
(2400)10 = (960)16
So Maximum number = (6666)7= (960)16
d. Solve the following.
(i) (111000.01)2 – (100111.00)2
Ans = (10001.01)2
(ii) (1010101)2 ÷ (11)2
Q = (11100)2 ; R = (1)2
e. Perform the following.
(i) (727)8 + (234)8
7 2 7
+ 2 3 4
1 1
1 9-8 6 11-8
1 1 6 3
(727)8 + (234)8 = (1163)8
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
(ii) (2C48)16 – (9AA)16 using 1C method.
1s complement 15 15 15 15
- 0 9 10 10
15 6 5 5
Minuend 2 12 5 8
1s C of subtrahend + 15 6 5 6
1 18-16 18-16 9 13
2 2 9 13
Add end around carry + 1
2 2 9 14
(2C48)16 – (9AA)16= (229E)16
f. Solve the following.
(i) Convert the following number to BCD and add them (11)10 + (9)10
(11)10 = 0001 0001
(09)10 = + 0000 1001
0001 1010
valid invalid
0001 1010
+ 0110
0010 0000
2 0
(11)10 + (9)10 = (20)10
(ii) Convert the following number to XS-3 &subtract them (53)10 – (28)10
XS-3 of (53)10 = 1000 0110
XS-3 of (28)10 = 0101 1011
1’s C of 28 = 1010 0100
Minuend 1000 0110
1s C of subtrahend + 1010 0100
1 0010 1010
Add end around carry 1
0010 1011
+ 0011 1101
0101 1000
2 5
(53)10 – (28)10 = (25)10
2. Attempt any three of the following: 15
a. Reduce the following using Boolean laws and theorems.
(i) 𝑾�̅�(𝑾 + 𝒀) + 𝑾𝒀(�̅� + �̅�)
𝑊𝑊�̅� + 𝑊�̅�𝑌 + 𝑊�̅�𝑌 + 𝑊�̅�𝑌 (Distributive Law)
𝑊�̅� + 𝑊�̅�𝑌 + 𝑊�̅�𝑌 + 𝑊�̅�𝑌 (AND law)
𝑊�̅� + 𝑊�̅�𝑌 + 𝑊�̅�𝑌 (OR law)
𝑊�̅� + 𝑊�̅�𝑌 + 0. 𝑌 (AND law)
𝑊�̅� + 𝑊�̅�𝑌 + 0 (AND law)
𝑊�̅� + 𝑊�̅�𝑌 (OR law)
𝑊�̅� (1 + 𝑌) (Distributive Law
𝑊�̅� . 1 (OR law)
𝑊�̅� (AND law)
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
(ii) 𝑿𝒀 + �̅��̅�𝒁 + (𝑿𝒀̅̅ ̅̅ + 𝒁)
𝑋𝑌 + �̅��̅�𝑍 + (�̅� + �̅�)𝑍 (Demorgans theorem)
𝑋𝑌 + �̅��̅�𝑍 + �̅�𝑍 + �̅�𝑍 (Distributive Law)
𝑋𝑌 + �̅�𝑍(�̅� + 1) + �̅�𝑍(Distributive Law)
𝑋𝑌 + �̅�𝑍 .1 + �̅�𝑍(OR law)
𝑋𝑌 + �̅�𝑍 + �̅�𝑍 (AND law)
𝑋𝑌 + 𝑍(�̅� + �̅�)
b. Write short notes on input bubbled AND gate and input bubbled OR gate.
Input bubbled AND gate
A and B are inverted and then given to AND gate
The modified representation can be shown using bubbled input
𝑌 = �̅�. �̅� = 𝐴 + 𝐵̅̅ ̅̅ ̅̅ ̅̅ = 𝑁𝑂𝑅 𝑔𝑎𝑡𝑒
Input Output
A B �̅� �̅� Y
0 0 1 1 1
0 1 1 0 0
1 0 0 1 0
1 1 0 0 0
So Bubbled AND gate = NOR gate
Input bubbled OR gate
A and B are inverted and then given to OR gate
The modified representation can be shown using bubbled input
𝑌 = �̅� + �̅� = 𝐴. 𝐵̅̅ ̅̅ ̅ = 𝑁𝐴𝑁𝐷 𝑔𝑎𝑡𝑒
Input Output
A B �̅� �̅� Y
0 0 1 1 1
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0
So Bubbled OR gate = NAND gate
c. Prove the following.
(i) �̅�𝑩𝑪 + 𝑨�̅�𝑪 + 𝑨𝑩�̅� + 𝑨𝑩𝑪 = 𝑨𝑩 + 𝑨𝑪 + 𝑩𝑪
According to Boolean law
A + A = A So A + A + A = A
LHS
�̅�𝐵𝐶 + 𝐴�̅�𝐶 + 𝐴𝐵𝐶̅ + 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶
�̅�𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴�̅�𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶̅ + 𝐴𝐵𝐶
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
𝐵𝐶(�̅� + 𝐴) + 𝐴𝐶(�̅� + 𝐵) + 𝐴𝐵(𝐶̅ + 𝐶)
BC + AC +AB
AB +AC +BC
RHS
(ii) (𝑨 + �̅�𝑩) (𝑪 + 𝑫 ̅̅̅̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ) = �̅��̅� + �̅�𝑫
LHS
(𝐴 + 𝐵)(𝐶 + �̅�)̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅ (𝐴 + �̅�𝐵 = 𝐴 + 𝐵)
(𝐴 + 𝐵)̅̅ ̅̅ ̅̅ ̅̅ ̅ + (𝐶 + �̅�)̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅ (Demorgans Theorem)
�̅� . �̅� + 𝐶̅. �̿� (Demorgans Theorem)
�̅��̅� + 𝐶̅𝐷 (Inverse law)
RHS
d. Simplify using K-map and realize it using minimum number of gates.
F(A,B,C,D,E) = ∑m(0,2,5,7,13,15,18,20,21,23,28,29,31)
�̅� �̅��̅� �̅�𝐸 𝐷𝐸 𝐷�̅�
�̅�𝐶̅ 1 0 0 1 0 3 1 2
�̅�𝐶 0 4 1 5 1 7 0 6
𝐵𝐶 0 12 1 13 1 15 0 14
𝐵𝐶̅ 0 8 0 9 0 11 0 10
𝐴 �̅��̅� �̅�𝐸 𝐷𝐸 𝐷�̅�
�̅�𝐶̅ 0 16 0 17 0 19 1 18
�̅�𝐶 1 20 1 21 1 23 0 22
𝐵𝐶 1 28 1 29 1 31 0 30
𝐵𝐶̅ 0 24 0 25 0 27 0 26
𝐹 = 𝐴𝐶�̅� + 𝐶𝐸 + �̅�𝐶̅𝐷�̅� + �̅��̅�𝐶̅�̅�
= 𝐶(𝐸 + 𝐴�̅�) + �̅�𝐶̅�̅�(�̅� + 𝐷)
e. Simplify using K-map and realize it using minimum number of gates.
F(A,B,C,D) = ∏M(4,6,8,9,10,12,13,14) +d(0,2,5)
𝐶 + 𝐷 𝐶 + �̅� 𝐶̅ + �̅� 𝐶̅ + 𝐷
𝐴 + 𝐵 X 0 1 1 1 3 X 2
𝐴 + �̅� 0 4 X 5 1 7 0 6
𝐴 ̅ + �̅� 0 12 0 13 1 15 0 14
�̅� + 𝐵 0 8 0 9 1 11 0 10
𝐹 = (�̅� + 𝐶). 𝐷
f. Minimize expression using Quine Mc Cluskey method.
f(W,X,Y,Z)=∑m(2,6,8,9,10,11,14,15)
Step 1 : list all minterms
Minterms Binary equivalent
W X Y Z
m2 0 0 1 0
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
m6 0 1 1 0
m8 1 0 0 0
m9 1 0 0 1
m10 1 0 1 0
m11 1 0 1 1
m14 1 1 1 0
m15 1 1 1 1
Step 2: group according to number of 1’s
Group Name Min terms W X Y Z
1 m2 0 0 1 0
m8 1 0 0 0
2
m6 0 1 1 0
m9 1 0 0 1
m10 1 0 1 0
3 m11 1 0 1 1
m14 1 1 1 0
4 m15 1 1 1 1
Step 3: form first reduction table
Group Name Min terms W X Y Z
1
m2-m6 0 - 1 0
m2-m10 - 0 1 0
m8-m9 1 0 0 -
m8-m10 1 0 - 0
2
m6-m14 - 1 1 0
m9-m11 1 0 - 1
m10-m11 1 0 1 -
m10-m14 1 - 1 0
3 m11-m15 1 - 1 1
m14-m15 1 1 1 -
Step 4: now list second reduction table
Group Name Min terms W X Y Z
1 m2-m6-m10-m14 - - 1 0
m2-m10-m6-m14 - - 1 0
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
m8-m9-m10-m11 1 0 - -
m8-m10-m9-m11 1 0 - -
2 m10-m11-m14-m15 1 - 1 -
m10-m14-m11-m15 1 - 1 -
The reduced table after removing the redundant rows is shown below.
Group Name Min terms W X Y Z
1
m2-m6-m10-m14 - - 1 0
m8-m9-m10-m11 1 0 - -
2 m10-m11-m14-m15 1 - 1 -
Further merging of the combinations of min terms from adjacent groups is not possible,
since they are differed in more than one-bit position. Each row will give one prime
implicant. Therefore, the prime implicants are 𝑌�̅�, 𝑊�̅�, 𝑊𝑌
The prime implicant table is shown below.
Prime Implicants 2 6 8 9 10 11 14 15
𝑌�̅� 1 1
1
1
𝑊�̅�
1 1 1 1
𝑊𝑌
1 1 1 1
The essential prime implicants are 𝑌�̅�, 𝑊�̅�, 𝑊𝑌
Therefore, the simplified Boolean function is f(W,X,Y,Z) = 𝑌�̅� + 𝑊�̅� + 𝑊𝑌
3. Attempt any three of the following: 15
a. The input to a combinational logic circuit is a 4 bit binary number. Design the logic
circuit with minimum hardware for the following
(i) Output Y1 = 1 if the input binary number is 5 or less than 5.
(ii) Output Y2 = 0 if the input binary number is 9 or more than 9.
Truth table for the combinational logic circuit is
Decimal Input Output
X3 X2 X1 X0 Y1 Y2
0 0 0 0 0 1 0
1 0 0 0 1 1 0
2 0 0 1 0 1 0
3 0 0 1 1 1 0
4 0 1 0 0 1 0
5 0 1 0 1 1 0
6 0 1 1 0 0 0
7 0 1 1 1 0 0
8 1 0 0 0 0 0
9 1 0 0 1 0 1
10 1 0 1 0 0 1
11 1 0 1 1 0 1
12 1 1 0 0 0 1
13 1 1 0 1 0 1
14 1 1 1 0 0 1
15 1 1 1 1 0 1
K-map
Y1 𝑋1̅̅̅̅ 𝑋0̅̅̅̅ 𝑋1̅̅̅̅ 𝑋0 𝑋1𝑋0 𝑋1𝑋0̅̅̅̅
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
𝑋3̅̅̅̅ 𝑋2̅̅̅̅ 1 0 1 1 1 3 1 2
𝑋3̅̅̅̅ 𝑋2 1 4 1 5 0 7 0 6
𝑋3𝑋2 0 12 0 13 0 15 0 14
𝑋3𝑋2̅̅̅̅ 0 8 0 9 0 11 0 10
Y1 = 𝑋3̅̅̅̅ 𝑋2̅̅̅̅ + 𝑋3̅̅̅̅ 𝑋1̅̅̅̅ = 𝑋3̅̅̅̅ + (𝑋2̅̅̅̅ + 𝑋1̅̅̅̅ ) = 𝑋3̅̅̅̅ . 𝑋2𝑋1̅̅ ̅̅ ̅̅ ̅ = 𝑋3 + 𝑋2𝑋1̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅
Y2 𝑋1̅̅̅̅ 𝑋0̅̅̅̅ 𝑋1̅̅̅̅ 𝑋0 𝑋1𝑋0 𝑋1𝑋0̅̅̅̅
𝑋3̅̅̅̅ 𝑋2̅̅̅̅ 0 0 0 1 0 3 0 2
𝑋3̅̅̅̅ 𝑋2 0 4 0 5 0 7 0 6
𝑋3𝑋2 1 12 1 13 1 15 1 14
𝑋3𝑋2̅̅̅̅ 0 8 1 9 1 11 1 10
Y2 = 𝑋3𝑋2 + 𝑋3𝑋0 + 𝑋3𝑋1 = 𝑋3 . (𝑋0 + 𝑋1 + 𝑋2)
Circuit is
b. Convert 4 bit gray to 4 bit binary. Draw the truth table, necessary k-maps and
logic circuit.
Truth table is
Decimal Input Output
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
3 0 0 1 1 0 0 1 0
2 0 0 1 0 0 0 1 1
6 0 1 1 0 0 1 0 0
7 0 1 1 1 0 1 0 1
5 0 1 0 1 0 1 1 0
4 0 1 0 0 0 1 1 1
12 1 1 0 0 1 0 0 0
13 1 1 0 1 1 0 0 1
15 1 1 1 1 1 0 1 0
14 1 1 1 0 1 0 1 1
10 1 0 1 0 1 1 0 0
11 1 0 1 1 1 1 0 1
9 1 0 0 1 1 1 1 0
8 1 0 0 0 1 1 1 1
K-map is
B3 𝐺1̅̅̅̅ 𝐺0̅̅̅̅ 𝐺1̅̅̅̅ 𝐺0 𝐺1𝐺0 𝐺1𝐺0̅̅̅̅
𝐺3̅̅̅̅ 𝐺2̅̅̅̅ 00 01 03 02
𝐺3̅̅̅̅ 𝐺2 04 05 0 7 0 6
𝐺3𝐺2 112 113 115 114
𝐺3𝐺2̅̅̅̅ 18 19 111 110
B2 𝐺1̅̅̅̅ 𝐺0̅̅̅̅ 𝐺1̅̅̅̅ 𝐺0 𝐺1𝐺0 𝐺1𝐺0̅̅̅̅
𝐺3̅̅̅̅ 𝐺2̅̅̅̅ 00 01 03 02
𝐺3̅̅̅̅ 𝐺2 14 15 17 16
𝐺3𝐺2 0 12 0 13 0 15 0 14
𝐺3𝐺2̅̅̅̅ 18 19 111 110
B3=G3 B2 = G3 ⨁ G2
B1 𝐺1̅̅̅̅ 𝐺0̅̅̅̅ 𝐺1̅̅̅̅ 𝐺0 𝐺1𝐺0 𝐺1𝐺0̅̅̅̅
𝐺3̅̅̅̅ 𝐺2̅̅̅̅ 00 01 13 12
B0 𝐺1̅̅̅̅ 𝐺0̅̅̅̅ 𝐺1̅̅̅̅ 𝐺0 𝐺1𝐺0 𝐺1𝐺0̅̅̅̅
𝐺3̅̅̅̅ 𝐺2̅̅̅̅ 00 11 03 12
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
𝐺3̅̅̅̅ 𝐺2 14 15 0 7 0 6
𝐺3𝐺2 012 013 115 114
𝐺3𝐺2̅̅̅̅ 18 19 011 010
𝐺3̅̅̅̅ 𝐺2 14 05 17 0 6
𝐺3𝐺2 0 12 113 0 15 114
𝐺3𝐺2̅̅̅̅ 18 0 9 111 0 10
B1 = G3 ⨁ G2 ⨁ G1 B0 = G3 ⨁ G2 ⨁ G1 ⨁ G0
Circuit is
c. Draw circuit and explain working of XS-3 adder.
Basic rules for XS-3 addition
(i) Convert given number in their XS-3 format.
(ii) Now add both the XS-3 numbers.
(iii) If carry generated then add 0011 to the sum else add 1101 to the sum and
neglect the carry.
For example add 8 and 4 in XS-3
XS-3 of 8 = 1011
XS-3 of 4 = + 0111
carry = 1 0010
+ 0011 0011
0100 0101 = 12
To decide whether to add 0011 or 1101 we need to check the value of carry bit. B3 B2 B1 B0
0 0 1 1 When carry=1
1 1 0 1 When carry=0
B0 is high in both situations. B2 and B3 are complement of B1.
When carry =1 then B1=1 and B2=B3=0
When carry =0 then B1=0 and B2=B3=1
Follows carry complement of carry
Finally we require two level of adder circuit
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
d. Design the Full Subtractor using K-map. Draw the circuit diagram for the same.
To overcome the problem of half Subtractor, we design the full Subtractor. Assume
A0 and B0 as one bit inputs and Bn as previous borrow input and output is difference
Dn and borrow Bn+1
The truth table is
Inputs Outputs
A0 B0 Bn Dn Bn+1
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Kmap is
D 𝐵0̅̅̅̅ 𝐵𝑛̅̅ ̅̅ 𝐵0̅̅̅̅ 𝐵𝑛 𝐵0𝐵𝑛 𝐵0𝐵𝑛̅̅ ̅̅
𝐴0̅̅̅̅ 00 11 03 1 2
𝐴0 14 05 1 7 0 6
Bn+1 𝐵0̅̅̅̅ 𝐵𝑛̅̅ ̅̅ 𝐵0̅̅̅̅ 𝐵𝑛 𝐵0𝐵𝑛 𝐵0𝐵𝑛̅̅ ̅̅
𝐴0̅̅̅̅ 00 11 13 1 2
𝐴0 04 15 1 7 16
D = A0 ⨁ B0 ⨁ Bn Bn+1 = 𝐴0̅̅̅̅ 𝐵𝑛 + 𝐴0̅̅̅̅ 𝐵0 + 𝐵0𝐵𝑛
The circuit diagram is
e. How Booths algorithm speeds up the multiplication process? Explain with an
example.
To avoid the problem of converting both multiplier and multiplicand to positive
numbers, perform the multiplication and eventually take two’s complement of the
result, if the sign of the two original numbers are different. This can be achieved using
Booths algorithm which also speeds up multiplication
The flowchart is
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
Consider an example using Booths algorithm as shown 6 X 5 where
M = 6 = 0110 and Q = 5 = 0101
f. Design single bit magnitude comparator. Draw truth table, K-mapand circuit
diagram for the same.
Consider two one bit numbers A and B. the truth table is as shown
Inputs Outputs
A B YA=B YA>B YA<B
0 0 1 0 0
0 1 0 0 1
1 0 0 1 0
1 1 1 0 0
K-Map is
YA=B �̅� 𝐵
�̅� 10 01
𝐴 02 1 3
YA>B �̅� 𝐵
�̅� 00 01
𝐴 12 1 3
YA<B �̅� 𝐵
�̅� 00 11
𝐴 02 0 3
YA=B= AʘBYA>B = 𝐴�̅�YA<B = �̅�𝐵
Circuit diagram is
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
4. Attempt any three of the following: 15
a. Implement full adder circuit using 8:1 MUX.
Truth table for full adder is as follows Inputs Outputs
A B C Sum (S) Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
The circuit is
b. Cascade Demultiplexer. Build 1:8 demux using 1:4 demux chips.
We are going to use 1:4 demux with enable terminal. A, B, C three variables are used
where A = MSB and C = LSB. B and C variables are given to select lines S1 and S0
respectively. A is directly given to lower demux and �̅� is given to upper demux. DIN of
both demux is tied together
c. 𝒀 = 𝑨 + 𝑩 + �̅�. Realize using a multiplexer.
The K-map for the above equation is
�̅�𝐶̅ �̅�𝐶 𝐵𝐶 𝐵𝐶̅ �̅� 10 01 13 1 2
𝐴 14 15 1 7 0 6
From K-map we can write the truth table for the above function
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
Input Output Input to Mux
A B C Y
0 0 0 1 D0
0 0 1 0 D1
0 1 0 1 D2
0 1 1 1 D3
1 0 0 1 D4
1 0 1 1 D5
1 1 0 1 D6
1 1 1 1 D7
Here there are three select lines A, B and C therefore inputs to a multiplexer will be 23
= 8. So we use 8:1 multiplexer for the function
𝑌 = 𝐴 + 𝐵 + 𝐶̅ The logic diagram is
d. Draw logic circuit diagram of D flip flop and describe with a truth table the
working of it.
To avoid the possibility of race condition in SR FF, we will change the design of FF.
The resulting circuit is called D FF. The symbol is
The circuit diagram is
The truth table is
Input Output
CLK D Qn+1 �̅�n+1
0 X NC(Qn) NC(�̅�n)
1 0 0 1
1 1 1 0
Qn+1 is simply copy of D input (data input). So functionally D FF produces output which is equal
to input but with some delay. Therefore it is called as Delay FF. It is most widely used in
computer system.
The state table is
Present state Next state
Qn D=0 D=1
0 0 1
1 0 1
State diagram is
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
State equation is
Qn+1 = D
e. How T flip-flop can be used to work as SR flip-flop? Explain.
Table will be
Inputs Transition Outputs
Q T Q to i S R
0 0 0→0 0 X
0 1 0→1 1 0
1 0 1→0 X 0
1 1 1→1 0 1
K-map is
�̅� 𝑇
�̅� 00 11
𝑄 X2 0 3
�̅� 𝑇
�̅� X0 01
𝑄 02 1 3
S= �̅�𝑇 R = QT
Circuit diagram
f. How flip-flop is used in eliminating keyboard debouncing? Explain.
We require ‘0’ and ‘1’ logic. Same can be generated either through oscillator circuit or
switch.
The waveform should change from 0V to 5V instantly and should get settle down. But
it is virtually impossible to obtain clear voltage transition from mechanical switch
because of contact debounce effect. Contact debounce means switch makes and breaks
contact, before coming to rest on contact point. The multiple transition last only for few
milliseconds but for many application this is not acceptable. Answer to this problem is
simple SR FF
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
Initially key is resting on position 1
∴ S = 0, R = 1, ∴ Q = 0
When switch is moved to position 2 then S = 1, R = 0
As the switch first makes the contact ∴ Q = 1.
Now if the switch debounce off contact 2 S = R = 1
∴ Q = Qn i.e. No change in output
∴ Q = 1. After some make and break switch will come to rest on contact 2. So problem
is solved.
5. Attempt any three of the following: 15
a. Design modulo 6 ripple counter.
The state diagram has 6 states – 0 to 5
Number of states N= 6
∴ n < N = 2m. So 6 < 2m
∴ m = 3
Truth table is
Input Output
Valid
Invalid
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
K-map is
�̅�𝐶̅ �̅�𝐶 𝐵𝐶 𝐵𝐶̅ �̅� 10 11 13 1 2
𝐴 14 15 07 0 6
𝑌 = �̅� + 𝐶̅ Counter is up counter. We have to cascade Q outputs. Negative edge triggered FF is
used and final output from Q. FF should have active low reset (clear) terminal.
Propagation delay presently assumed is 0 sec.
Circuit diagram is
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
b. Design 4 bit binary up/down counter with control input of up/down.
For 4 bit counter, 4 FFs are required. We will design a ripple counter. For up/down
terminal we use NOT gate where up/down = 0 → up operation and up/down = 1→ down
operation.
Circuit diagram is
We want one control terminal in such a way that the counter will start either up or down
counting. We cascade Q to �̅� and counter changes from up to down counting.
Case I – When up/down control terminal = 0, x=1. Therefore AND gate 1,3 and 5 will be
transparent thus cascades Q output whereas AND gate 2, 4 and 6 produces continuous LOW
output irrespective of�̅�. Therefore counter counts up.
Pn = 1, Q1 = 1, Qt = 1, Up= 1⊕ 1 ⊕ 1 = 1 → up counter.
Case II - When up/down control terminal = 1, x=0. Therefore AND gate 2, 4 and 6 will be
transparent thus cascades �̅� output whereas AND gate 1, 3 and 5 produces continuous LOW
output irrespective of Q. Therefore counter counts down.
Pn = 1, Q1 = 1, Qt = 0, Up= 1⊕ 1 ⊕ 0 = 0 → down counter.
c. Implement synchronous counter using JK FF for state diagram shown in figure
This is counter circuit with busing. The number of FFs required will be 2.
The truth table is
A
0
2 - 1
0
1 - 3
0 - 3
3 - 2
1
1
B 0 1 0 1
JA 0 1 X X
KA X X 1 0
JB 0 X 1 X
KB X 0 X 1
K-map is
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
�̅� 𝐵
�̅� 00 11
𝐴 X2 X 3
�̅� 𝐵
�̅� X0 X1
𝐴 12 0 3
�̅� 𝐵
�̅� 00 X1
𝐴 12 X 3
�̅� 𝐵
�̅� X0 01
𝐴 X2 1 3
JA = B
KA = �̅�
JB = A
KB = A
The circuit diagram is
d. Write a short note on buffer register.
Buffer register is simplest kind of register and stores digital word. The structure of
buffer register built is the edge triggered D type FF is
Working
1. Initially consider Q3Q2Q1Q0 = 00000
2. Apply data to be stored at input terminal Y3 – Y0. For example Y3Y2Y1Y0 =
1010.
3. Apply clock pulse
4. When the first clock edge arrives Y3Y2Y1Y0= Q3Q2Q1Q0 = 1010
5. Even though if now Y3Y2Y1Y0 = 0000, Q3Q2Q1Q0 = 1010 i.e. latched
Conclusion
1. There must be one FF for eacg bit in binary number. So for 4 bit we require 4 FFs.
2. Simultaneously Y3 – Y0 was applied and loaded to Q3 – Q0 by single clock pulse
i.e. at a time Q3 – Q0 was loaded.
3. The way we have applied the input and taken out makes it parallel in – parallel out
register as well.
e. Explain working of SIPO register.
In this function, data is entered serially and taken out in parallel. To take data parallel
out, it is necessary to have all data bits available as output at the same time and therefore
output of each FF is taken.
The circuit is
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just
been RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0”
i.e., no parallel data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse
the output of FFA and therefore the resulting QA will be set HIGH to logic “1” with all
the other outputs still remaining LOW at logic “0”. Assume now that the DATA input
pin of FFA has returned LOW again to logic “0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output
of FFBand QB HIGH to logic “1” as its input D has the logic “1” level on it from QA.
The logic “1” has now moved or been “shifted” one place along the register to the right
as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output
of FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets all the
outputs QA to QD back again to logic level “0” because the input to FFA has remained
constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the
right, and this is shown in the following table until the complete data value of 0-0-0-1 is
stored in the register. This data value can now be read directly from the outputs
of QA to QD.
Then the data has been converted from a serial data input signal to a parallel data output.
The truth table and following waveforms show the propagation of the logic “1” through
the register from left to right as follows.
The truth table is
Clock
Pulse QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0
Commonly available SIPO IC’s include the standard 8-bit 74LS164 or the 74LS594.
f. Write a short note on Johnson counter.
In ring counter output shift register was fed back to input of first FF. This technique
was referred as direct feedback. But if output of last FF are crossed and then connected
to inputs of first FF, the technique is called inverse feedback. The counter we get from
this technique is called Johnson counter or twisted ring counter.
The circuit is designed using positive edge triggered JK FF.
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit
The truth table is
Clock QD QC QB QA State Decimal
equivalent
Initially 0 0 0 0 1 0
1 0 0 0 1 2 1
2 0 0 1 1 3 3
3 0 1 1 1 4 7
4 1 1 1 1 5 15
5 1 1 1 0 6 14
6 1 1 0 0 7 12
7 1 0 0 0 8 8
8 0 0 0 0 1 0
1. Initially clock is made low and then high after some time. ∴ All FFs will be
cleared and output QDQCQBQA = DCBA = 0000.
2. Now inputs JD = JC = JB = 0 and KD = KC = KB = 1 and JA= 1 and KA = 0. So
when clock edge hits, A will change from 0 → 1. BCD are unchanged. ∴DBCA
= 0001.
3. Now inputs JD = JC = 0 and KD = KC = 1 and JA= JB = 1 and KA = KB = 0. So
when clock edge hits, D and C are unchanged, A is also unchanged but B will
change from 0 → 1. ∴DBCA = 0011.
4. Now inputs JD = 0 and KD = 1 and JA= JB = JC = 1 and KA = KB = KC = 0. So
when clock edge hits, C will change from 0 → 1.A, B and D are unchanged
∴DBCA = 0111.
5. Now inputs JD = JC = JB = JA = 1 and KD = KC = KB = KA = 0. So when clock
edge hits, D will change from 0 → 1. ABC are unchanged. ∴DBCA = 1111.
6. Because of the change of state of D, the inputs JD = JC = JB = 1 and KD = KC =
KB = 0 and JA= 0 and KA = 1. So when clock edge hits, A will change from 1 →
0. BCD are unchanged. ∴DBCA = 1110.
7. Now inputs JD = JC = 1 and KD = KC = 0 and JA= JB = 0 and KA = KB = 1. So
when clock edge hits, A, C and D are unchanged, but B will change from 1 →
0. ∴DBCA = 1100.
8. Now inputs JD = 1 and KD = 0 and JA= JB = JC = 0 and KA = KB = KC = 1. So
when clock edge hits, C will change from 1 → 0.A, B and D are unchanged
∴DBCA = 1000.
9. Now inputs JD = JC = JB = JA = 0 and KD = KC = KB = KA = 1. So when clock
edge hits, D will change from 1 → 0. ABC are unchanged. ∴DBCA = 0000.
Now cycle repeats from step 2.
The number of states of Johnson counter is double the number of FFS. Therefore for 4
FFs, states will be 8.
Johnson counter can also be designed using D FF
_____________________________
https://abdullahsurati.github.io/bscit
https://abdullahsurati.github.io/bscit