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2168-6777 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2940514, IEEE Journalof Emerging and Selected Topics in Power Electronics
1
Abstract—Aiming at fulfilling the desirable features of compact
structure, high efficiency, high reliability and multifunctionality
for the solid state transformers(SSTs), a single-cell matrix-type
SST as well as its control method is proposed as the interface
between the medium-voltage (MV) and the low-voltage(LV) levels
for direct MV AC to LV AC conversion. To achieve zero voltage
switching(ZVS) at both the MV and LV sides, a modulation
scheme to construct the special resonant currents during dead
time by actively controlling the MV and LV side gate signals is
implemented. Furthermore, the ZVS conditions of the MV and
LV side bridges are analyzed, and system parameters are
properly designed to ensure full range ZVS operation. A 1 kW
SST prototype is developed to verify the functionality and
effectiveness of the proposed methods. The experiments show that
sinusoidal input and output, bidirectional power flow capability
and ZVS at both sides over wide input voltage and load ranges are
achieved with the nominal efficiency of 96.1%. The experimental
results match the theoretical analysis and the simulation results
well.
Index Terms—solid state transformer(SST), direct AC-AC
power conversion, zero voltage switching(ZVS), matrix-type SST,
series resonant converter(SRC).
I. INTRODUCTION
The Solid State Transformer(SST) is considered as an
exciting and promising concept to establish the interface
between the medium-voltage (MV) and the low-voltage (LV)
levels, which provides galvanic isolation and voltage scaling
by means of a medium-frequency (MF) link [1]-[4]. Due to the
Manuscript received April 30, 2019; revised July 1, 2019; accepted for
publication August 30, 2019. This work was supported by the National Key
R&D Program of China under Grant 2017YFB1200900, the National Natural
Science Foundation of China under Grant 61873289, Hunan Provincial Key Laboratory of Power Electronics Equipment and Grid, the Project of
Innovation-driven Plan in Central South University under Grant 2019CX003,
the Major Project of Changzhutang Self-dependent Innovation Demonstration Area under Grant 2018XK2002.
Hui Wang is with the School of Automation, Central South University,
Changsha 410083, China, and also with the Wasion Group Co., Ltd., Changsha 410205, China (e-mail: [email protected]).
Yichun Zhang, Yao Sun and Kaiyuan Tan are with the School of Automation, Central South University, Changsha 410083, China (e-mail:
[email protected]; [email protected]; [email protected]).
Minghui Zheng is with the Department of Mechanical and Aerospace Engineering, University at Buffalo, Buffalo, NY 14260, USA (email:
Xiao Liang (corresponding author) is with the Department of Civil, Structural and Environmental Engineering, University at Buffalo, Buffalo, NY
14260, USA (email: [email protected])
Guanguan Zhang is with the School of Control Science and Engineering, Shandong University, Jinan 250013, China([email protected]).
Jianghua Feng is with the CRRC Zhuzhou Institute Co. Ltd., Zhuzhou
412001, China(e-mail:[email protected]).
advantageous features such as output voltage regulation,
controllable power flowing, reactive power compensation,
active power filtering, fault isolation, DC connectivity, as well
as potentially high conversion efficiency and high power
density, SSTs have attracted an increasing attention and are
regarded as the replacement for conventional line-frequency
transformers (LFTs) in many applications such as smart
distribution network, electric traction, distributed propulsion
ship and aircraft, and so on [5]-[16]. However, many technical
challenges on efficiency, power density, reliability, MF high
voltage insulation and protection, must be addressed before its
commercial use.
Aiming at achieving high conversion efficiency, low cost,
high power density, high reliability and multi-functionality,
many SST topologies have been proposed and studied
[17]-[24]. Among these topologies, the AC-DC-DC-AC
three-stage SSTs with the DC link are the most widely
investigated and adopted because of their good controllability
[17]-[20]. However, the major drawback of these topologies is
the relatively low conversion efficiency due to multi-stages
power conversions. Besides, the heavy and bulky energy
storage elements in the MV and LV DC links inevitably
decrease the power density and reliability of the SSTs.
Direct AC-AC SST topologies, or the so-called matrix-type
SSTs are attractive alternatives, which have the less power
conversion stages and no energy storage element in the DC
link, and then higher conversion efficiency, higher power
density and higher reliability are achieved in theory [21]-[24].
Among the various matrix-type SST topologies, the
phase-integrated matrix-type SSTs have the merits of
phase-modularity of electric circuit and magnetic circuit, as
well as flexible expansibility, which usually employ the
single-phase AC-AC converter cell with a front end unfolding
bridge. Therefore, the required input blocking voltage and
power rating in MV applications can be achieved by multi-cells
phase-integrated matrix-type SSTs based on the input series
output parallel(ISOP) configuration [23, 24]. However, this
configuration has the disadvantages of complex structures and
control methods [25]-[27], which cause the power density
reduction and reliability issue.
Recently, the development of SiC MOSFETs with extremely
high blocking voltage and excellent switching behavior makes
it possible to construct a single-cell matrix-type SST while
avoiding ISOP configuration, and therefore resulting in a
simple, reliable and compact SST structure [28, 29]. When
applying the single-cell matrix-type SST to MV applications,
one of the most significant challenges that need to be addressed
Topology and Control Method of a
Single-Cell Matrix-Type Solid State
Transformer Hui Wang, Yichun Zhang, Yao Sun, Member, IEEE, Minghui Zheng, Xiao Liang, Guanguan Zhang, Kaiyuan Tan, Jianghua Feng
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2940514, IEEE Journalof Emerging and Selected Topics in Power Electronics
2
is to achieve ZVS for all MOSFETs over an extremely wide
input voltage and load ranges. This is mainly for efficiency and
electro-magnetic interference (EMI) reasons, especially when
MOSFET switches at MVs. In general, although the dual active
bridge (DAB) topology has the merit of good ZVS capability
[30], the load and voltage-dependent ZVS characteristic make
it unsuitable for the direct AC-AC conversion applications. By
having the advantages of load-independent ZVS feature and
negligible turn off losses, the series resonant converter (SRC)
based single-cell SST is considered as an attractive solution for
direct MV AC to LV AC conversion [31]. In [32], a current-fed
SRC based single-cell matrix-type SST is presented, and ZVS
for MV side MOSFETs over a relatively wide input voltage
range is achieved. However, the ZVS operation of the LV side,
the controllability of the output and bidirectional power flow
are not realized, since the LV side bridge is only treated as an
uncontrolled diode rectifier. A single-cell two-stage AC-DC
SST is suggested for future data centers in [33], and a special
modulation scheme is developed for the SRC to achieve ZVS
on both MV and LV sides by introducing a small phase shift
between the gate control signals of the MV and LV sides.
Unfortunately, due to the nonlinearity of MOSFET’s output
capacitance versus the applied voltage, the ZVS realizations of
MV and LV sides in the single-cell matrix-type SST become
more complicated than that in a AC-DC SST with constant DC
link voltage. Therefore, ZVS conditions for the single-cell
matrix-type SST should be analyzed carefully, and system
parameters should be designed properly to ensure ZVS over
full input voltage and load ranges.
In this paper, a single-cell matrix-type SST, as well as its
control method, is proposed for direct MV to LV power
conversion. The concept of dual-active SRC in [33] is extend to
the direct AC-AC SST, and a modulation scheme that achieves
ZVS at both MV and LV sides over full input voltage and load
ranges is developed. For the LLC SRC stage of the developed
SST with extra wide input voltage and bidirectional power
flow directions, the ZVS condition is analyzed in the time
domain in detail, and a general design guide of the key system
parameters to meet ZVS condition over full input voltage and
load ranges is developed. The effectiveness of the methods is
verified by simulation and experimental results under different
operation conditions. Compared with the conventional SSTs,
the presented SST has the potential advantages in conversion
efficiency, power density, reliability and control complexity
because of reduced power conversion stage, ZVS at both
primary and secondary sides over full input voltage and load
ranges, absence of the bulky energy storage elements, direct
MV AC to LV AC conversion with a single-cell configuration,
and unified control method for both forward and reverse power
flow directions.
The remainder of this paper is organized as follows: Section
II introduces the topology and operating principles of the
presented SST; Section III presents the ZVS conditions
analysis of the MV and LV sides, followed by the ZVS design
ensuring ZVS operation over full input voltage and load ranges.
In Section IV, the control scheme of the SST is developed to
achieve controllable output voltage, and the sinusoidal input
current is also proofed; Section V shows the simulation and
experimental results to verify the correctness of the presented
topology and method; Section VI draws the conclusions.
II. TOPOLOGY AND OPERATING PRINCIPLES OF THE SST
A. Topology
io
S11 S13
S10 S12
S1
S2
S3 S5
S4 S6
T L
S7
S8
L
ui
-
+
C
ii
i o
Unfolding Bridge LLC SRC Inverter
C
Csudc1
+
-
p1
p2
up
-
+ ip im
Lm
is
us
-
+ucr -+ udc2
+
-
S9
S14
uo
+
-
Co RL
Lr
Cr
Cossp
Cossp Cosss
Cosss
Cosss
Cosss
1:n
iL
idc1 idc1 idc2
idc2
Fig. 1. Schematic diagram of the proposed SST topology.
The developed SST topology is shown in Fig. 1, which
consists of an unfolding bridge, a LLC SRC and a single-phase
full-bridge inverter.
For the topology shown in Fig. 1, the unfolding bridge acts
as a line-commutated bidirectional rectifier and provides the
absolute value of the input sinusoidal voltage for the rear-end
LLC SRC. The switching states of the unfolding bridge as well
as the MV-side (denoted as primary-side in the rest texts)
DC-link voltage udc1, are only determined by the instantaneous
value of the input voltage. The LLC SRC consists of a split
DC-link, a half-bridge on the primary-side, an MF transformer
providing galvanic isolation and voltage scaling, and a
full-bridge on the LV-side (denoted as secondary-side in the
rest texts). The LLC SRC is chosen as the isolated DC-DC
stage for its simple operation, the possibility to achieve ZVS
for all switches, as well as low conduction losses and
high-frequency effects related losses. The half-bridge
configuration on the primary-side has the merits of the simple
construction and the natural voltage step-down characteristic
by a factor of two, which is beneficial to the design of the MF
transformer. The input filter of the primary-side DC-link
consists of the input inductor Li and film capacitors Cp1 and Cp2 ,
which is mainly used for filtering the high-frequency currents
generated by the LLC SRC to produce sinusoidal input current.
B. Operating Principles
Referring to the topology shown in Fig. 1, the operating
principles are explained as follows. For the front-end unfolding
bridge, when the input voltage ui is positive, switches S1 and S4
of the unfolding bridge are turned on. Otherwise, switches S2
and S3 are turned on. As a result, the primary-side DC-link
voltage is the absolute value of the input sinusoidal voltage.
In the presented topology, the LLC SRC is only used to
provide galvanic isolation and voltage scaling, where the
output voltage is controlled by the inverter. Therefore, the LLC
SRC is operated at its resonance frequency, which acts as a DC
transformer and provides a fixed voltage gain. Consequently,
the primary-side DC-link voltage udc1 is converted to the
secondary-side DC-link voltage udc2 with different amplitudes.
Different from the conventional LLC SRC, both the primary
and secondary side bridges are actively controlled with 50%
duty cycle. Fig. 2 shows the voltage and current waveforms in a
switching period Ts, where Tdp, up and ip are the dead time, the
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2940514, IEEE Journalof Emerging and Selected Topics in Power Electronics
3
output voltage and the resonant current of the primary-side
bridge; Tds, us and is are the dead time, the output voltage and
the resonant current of the secondary-side bridge; im is the
magnetizing current of the MF transformer; Tp is the phase shift
between the primary and secondary side gate signals.
As can be seen from Fig. 2, the gate signals of the LLC SRC
with the presented dual-active control scheme are fixed and are
irrelevant to the power flow direction. During the voltage
transitions of the primary and secondary side, the tiny phase
shift Tp produces a small voltage-second product which is
applied to the resonant inductance Lr of the resonant tank,
causing tiny resonant current spikes at both sides of the MF
transformer. As a result, the spike generates a negative
resonant current at the secondary-side, discharging the
effective output capacitor of the MOSFETs to be turned on and
thus achieving ZVS operation of the secondary-side MOSFETs.
For the primary-side MOSFETs, the magnetizing current is
designed to be sufficiently high to discharge the effective
output capacitor of the MOSFETs during the dead time and
thus allow ZVS operation of the primary-side bridge.
Therefore, the presented control scheme is valid for both
forward and reverse power flow directions.
S5
S6
S7 S10&
S8 S9&
Gate
Co
ntr
ol
Vo
ltag
e
up us
Cu
rrent
ip is
im
t
t
TpTdp
Tds
Cu
rrent
ip is
im
-Ts/2 Ts/20
t
Forward power flow direction Reverse power flow direction
S5
S6
S7 S10&
S8 S9&
Gate
Co
ntr
ol
Vo
ltag
e
up us
t
TpTdp
Tds
-Ts/2 Ts/20
Fig. 2. Magnified voltage and current waveforms of the LLC SRC together
with the gate signals.
According to the requirements of the load, the single-phase
full-bridge inverter is modulated with high frequency, which
provides sinusoidal output voltage with the desired amplitude.
It can be found from the operating principle that the primary
and secondary sides DC-link voltages exhibit the absolute
value of the sinusoid shape waveform. The accurate feature of
the primary and secondary DC-link voltages can be analyzed
from the equivalent circuit of the SST shown in Fig. 3, where
the equivalent circuit is modeled as a second-order low pass
filter. It can be known from the equivalent circuit that both the
primary and secondary DC-link voltages exhibit the absolute
value of the sinusoidal shape except a tiny phase lag from the
input voltage and is irrelevant to the capacitance of the DC-link
capacitors in theory. Although the DC-link capacitors with
large capacitance are beneficial to suppress the voltage ripple,
it would cause unexpected input reactive power and decreased
power density. Therefore, a trade-off should be made between
the DC-link voltage ripple and the input power factor and
power density when choosing the DC-link capacitors.
L
ui/2-
+
2iii/4
2Cp
LdcRdc
Cs
io
-
+udc1/2
-
+udc2/n
Fig. 3. Equivalent circuit of the SST.
The time-varying primary and secondary side DC-link
voltages post a challenge to realizing ZVS of both sides across
the entire input voltage range. As a result, the ZVS conditions
should be examined carefully and the system parameters
should be designed properly to ensure ZVS operation over the
entire input voltage range. Besides, an appropriate control
scheme should be developed for the inverter for achieving
sinusoidal input and output waveforms simultaneously.
III. ZVS CONDITION ANALYSIS AND ZVS DESIGN
In general, high conversion efficiency is one of the most
desirable features for the SSTs. Therefore, it is preferable to
implement ZVS at both sides of the LLC SRC. Because both
the magnetizing current and the effective output capacitor of
the MOSFETs are time variable due to the absolute value of the
sinusoid shape DC-link voltages, the ZVS condition analysis
and ZVS design become more complicated.
A. ZVS Condition Analysis of the Primary-Side
As can be seen from Fig. 2, the turn off the loss of the
MOSFETs in the primary-side bridge can be ignored since the
MOSFETs turn off at the peak of the magnetizing current
whose magnitude is relatively small. Thus, this section mainly
focuses on the analysis of ZVS turn on.
As can be known from the operating principle of the LLC
SRC, the ZVS turn on behavior of the primary-side MOSFETs
is related to the primary-side DC-link voltage, the magnitude of
the magnetizing current, the primary-side dead time as well as
the effective output capacitor of the primary-side MOSFETs.
Assuming that the input voltage ui is given by
sini im iu U t (1)
where Uim and i represent the magnitude and angular
frequency of the input voltage. Then the magnitude of the
magnetizing current, denoted as Imp, can be expressed as
| sin | /8 mmp im i sI U t L f (2)
where fs is the switching frequency of the LLC SRC. In order to
realize ZVS turn on of the primary-side MOSFETs, Imp should
be large enough to fully discharge the effective capacitor
presented across the primary-side. Therefore, the ZVS
condition of the primary-side is described as
( | sin( ) | /8 ) 2 | sin( ) | mmp dp im dp i s ossp stray im iI T U T t L f Q C U t
(3)
where Qossp and Cstray are the charges associated with the
effective output capacitor of the primary-side MOSFET and
the total stray capacitance presented across the resonant tank
impedance, respectively.
It can be known from [30] that Qossp is a nonlinear function
of the applied voltage which is roughly given by
| sin( ) | | sin( ) |ossp im i im iQ a U t bU t (4)
where a and b are the specific parameters associated with the
MOSFET. Thus for the given system parameters including the
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2940514, IEEE Journalof Emerging and Selected Topics in Power Electronics
4
magnetizing inductance and primary-side dead time, the
primary-side ZVS condition changes with the instantaneous
input voltage, and the lower absolute value of the input voltage,
the smaller ZVS margin of the primary-side. Therefore, the
switching frequency, the magnetizing inductance as well as the
primary-side dead time should be designed properly to ensure
ZVS operation of the primary-side across the entire input
voltage range. Besides, the generated tiny current spike to
realize the ZVS operation of the secondary-side would slightly
decrease the magnitude of the primary-side resonant current
during the dead time, which should be taken into consideration
when making the ZVS design of the primary-side.
B. ZVS Condition Analysis of the Secondary-Side
Different from the ZVS principle of the primary-side, ZVS
operation of the secondary-side is achieved by producing a tiny
spike in the secondary-side resonant current by introducing a
small phase shift between the gate control signals of the
primary and secondary sides. Thus, the current spike used to
discharge the effective output capacitor of the secondary-side
MOSFET so as to achieve ZVS, should be analyzed carefully.
Referring to the topology depicted in Fig. 1 and the
magnified waveforms of the LLC SRC in Fig. 2, the ZVS turn
on condition of the secondary-side MOSFETs can be analyzed
as the follows. The spike in the primary-side resonant current
during the dead time, denoted as pi , is given by
( / )
)
dp
p sp
rT
u u ni dt
L
(5)
where n is the turns ratio of the MF transformer. Accordingly,
the secondary-side resonant current during the dead time can
be written as
/s pi i n (6)
Assuming that the slope of up and us are constant during the
dead time, then the maximum possible charge that can be
discharged by the secondary-side resonant current during the
dead time is expressed as
[6 ( ) ]/122 3p ds s p rzvsmax p dsQ = k T T + k -k T nL (7)
where kp and ks are the slope of up and us during the turn of
process, respectively. Because kp and ks can be approximated as
| sin( ) | / , | sin( ) | / p im dp s im dsi ik U t T k nU t T (8)
Thus, equation (7) can be further deduced as 2 2 3| sin( ) |[6 ] /12 im ds dp r dpzvsmax i p ds dsQ U t T T nT T T nL T (9)
Since Tp+Tds Tdp, Qzvsmax can be expressed as 2 3 2 3| sin( ) |[( 3) ( 1) (2 3) 6 ]
12
im dp pi p dp dp p
zvsmaxr dp
U t n T T n T n T T TQ
nL T
(10)
If the charge associated with the effective output capacitor of
the secondary-side MOSFET and the total stray capacitance
presented across the secondary-side is smaller than Qzvsmax, then
ZVS turn on at the secondary-side can be guaranteed.
C. ZVS Design of the LLC SRC
As have been described in (3), the system parameters
including the switching frequency, the magnetizing inductance
and the primary-side dead time, can be properly designed to
fulfill ZVS constrain at the primary-side. When designing an
acceptable switching frequency, there are several factors that
may need consideration. The lower the switching frequency is,
the bulkier the converter, and the lower the turn off switching
losses. A higher switching frequency makes the benefits of the
LLC SRC more pronounced, but the additional magnetic-core
and turn off switching losses, the PCB-layout and system EMI
concerns, may have to be considered. Thus, fs =60 kHz is
selected in this work to make a trade-off between the efficiency
and the power density.
Once having determined fs, all that remains is to select a
proper Lm and Tdp. As can be seen from (3), both decreasing Lm
and increasing Tdp benefit achieving ZVS of the primary-side.
In general, smaller Lm produces higher turn off current and
higher RMS resonant current, which would cause both higher
switching losses and conduction losses. Similarly, longer dead
time leads to higher RMS resonant current and consequent
higher conduction losses. Therefore, a trade-off also needs to
be made when choosing Lm and Tdp. Besides, as having been
described in (4), the dead time required to achieve ZVS of the
primary-side at full udc1 range is nonlinear, and a longer dead
time is needed to realize ZVS at low udc1. As a result, a very
large Tdp or a variable Tdp according to the instantaneous udc1
would be required to achieve ZVS at full udc1 range. To keep
the dead time arrangement simple and maintain a low
conduction loss in the meanwhile, a constant dead time scheme
is designed. Therefore, there exists a tiny zone near the
zero-crossing point of udc1 that primary-side ZVS cannot be
achieved. This is reasonable because the switching losses can
be ignored due to the low switching voltage of the MOSFET.
By considering these factors, Lm and Tdp are designed as 100
µH and 1.4 µs in the prototype.
After determining fs, Lm and Tdp, the phase shift Tp to achieve
ZVS of the secondary-side can be selected based on the
specific turns ratio n and the chosen secondary-side MOSFET
according to (10). In this paper, Tp is designed as 100 ns.
IV. CONTROL SCHEME OF THE SST
Since the unfolding bridge is commutated with line
frequency and the LLC SRC is operated as a DCX, the control
of the unfolding bridge and the LLC SRC are relatively simple.
Thus, this section mainly focuses on the control of the rear-end
inverter.
A. Control Scheme of the Inverter
The overall control scheme of the rear-end inverter is shown
in Fig. 4, where*ou ,
*oi , iL and uinv represent the expected output
voltage of the inverter, the reference current of the output
inductor, the load current and the modulation voltage of the
inverter, respectively. A conventional voltage and current
double closed-control structure is adopted here, and the
proportional-resonant (PR) controller is selected to track the
sinusoidal voltage and current. The voltage and current PR
controller are designed as 2 2
20( ) 0.35
5 (100 )v
sG s
s s
and
2 2
30( ) 4.5
(100 )i
sG s
s
, respectively. And the detailed
design procedure using conventional frequency-domain
analysis tools is not given here for the sake of brevity. To
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5
improve the dynamic tracking speed, the practical output
voltage is used as a feed-forward term and added to the output
of the current controller. The final modulation voltage of the
inverter is then fed into the carrier-modulation module to
generate the gate control signals of the inverter.
Fig. 4. Control scheme of the inverter.
The carrier-modulation is given briefly as follows.
Assuming that the modulation voltage is given by
sinrefinv iu U t (11)
where Uref represents the magnitude of the modulation voltage.
Since the secondary-side DC-link voltage is featured by the
absolute value of the sinusoid shape, it is necessary to
compensate it by normalizing the initial modulation voltage
according to the instantaneous secondary-side DC-link
voltage:
2/inv inv dcu u u (12)
where invu is the normalized modulation voltage of the
inverter. Finally, the generated gate signals are applied to the
switches of the inverter, and expected output voltage is
obtained.
B. Analysis of the Input Current
For the presented SST, the goal of sinusoidal input current
and output voltage should be guaranteed simultaneously. As
can be inferred from the control scheme of the inverter, the
sinusoidal output voltage can be obtained easily by properly
synthesis, as shown in part A of Section IV. However, whether
the sinusoidal input current could be achieved should be
examined. Thus, this part gives a detailed analysis of the input
current.
Assuming that the output current is given by
sin o om ii I t (13)
where Iom and are the magnitude and initial phase of the
output current. Then the averaged value of the current '
2dci ,
denoted as '2dci , can be written as
'
2 2/ 2 / | sin( ) | imdc inv o dc inv o ii u i u u i nU t (14)
In steady state, the averaged value of the current 2dci ,
denoted as 2dci , equals to '2dci . Thus, the peak value of the
sinusoidal resonant current at the secondary-side, denoted as
spi , is expressed as
2/ 2sp inv o dci u i u (15)
Accordingly, the peak value of the resonant current at the
primary-side, denoted as ppi , is described as
pp spi ni (16)
Because of the direct AC-AC conversion without any energy
storage, the averaged value of the current 1dci , denoted as 1dci ,
also equals to the averaged value of the current '
1dci :
1 /dc ppi i (17)
Substitute (13)-(16) into (17), 1dci can be deduced as:
1 sin sin / | sin | ref om imdc i i ii U I t t U t (18)
When the input voltage satisfies ui>0, switches S1 and S4 in
the unfolding bridge are conducted. Thus, the input current ii
can be expressed as
1 sin / / i ref om im ref imdc i oi i U I t U U i U (19)
According to (19), the input current is sinusoidal with the
same initial phase as that of the output current. For the case of
ui<0, the same result can be obtained, and the derivation
process is not repeated here. Thus sinusoidal input current is
achieved under the developed scheme.
V. SIMULATION AND EXPERIMENTAL RESULTS
In this section, the functionality and performance of the SST
were firstly evaluated by simulation and then were validated
experimentally. The parameters in simulation and experiments
are listed in Table I. TABLE I
SYSTEM PARAMETERS OF THE SST
Parameter Simulation Value Experimental Value
Input voltage ui 5773 Vrms 220 Vrms
Input frequency i 314 rad/s 314 rad/s
LLC switching frequency fs 60 kHz 60 kHz
LLC resonant inductor Lr 100 µH 7.6 µH
LLC resonant capacitor Cr 8.5 µF 0.2 µF
Magnetizing inductance Lm 3 mH 100 µH
Turns ratio n 0.04545 2.15
LLC primary bridge switch - FCH072N60F
LLC secondary bridge switch - FCH072N60F
LLC dead time 1.4 µs 1.4 µs
Input inductor Li 5 mH 200 µH
Capacitor Cp1 and Cp2 500 nF 6.6 µF
Capacitor Cs 20 µF 2.2 µF
Inductor Lo 200 µH 400 µH
Capacitor Co 30 µF 3.3 µF
Inverter switching frequency 20 kHz 20 kHz
Power rating 30 kW 1 kW
A. Simulation
Fig. 5 shows the steady waveforms of the SST with forward
power flow direction. The input voltage was 5773Vrms and the
output parameters were set as *
ou =311V and RL=2 Ω ,
respectively. The waveforms shown in Fig. 5 consist of the
input voltage ui, the input current ii, the output voltage uo and
the output current io. As can be seen from Fig. 5, the input
current is nearly sinusoidal and in phase with the input voltage,
except for a slight phase advance caused by the capacitive
current drawn by the input capacitor. Besides, the output
voltage uo is also sinusoidal and tracks the reference very well.
Thus, it is clear that the presented SST is able to generate
sinusoidal input current and controllable output voltage.
In Fig. 6, a single-phase grid-connected inverter is used as
the active load to test the bidirectional power flow capability of
the SST. The load and power flow direction of the SST can be
changed by regulating the active component of the
grid-connected current iref of the grid-connected inverter. In
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6
this simulation, the active component of the grid-connected
current is set as 195A. Again, the desirable features of
sinusoidal input and output currents and precise tracking of the
output voltage are achieved. Besides, the input current is out of
phase with the input voltage, demonstrating reverse power
flow direction of the SST. The simulation result verifies the
bidirectional power flow capability of the SST.
Fig. 5. Simulated waveforms of the SST with forward power flow direction.
Fig. 6. Simulated waveforms of the SST with reverse power flow direction.
Fig. 7 shows the dynamic test of the system. In Fig. 7(a), iref
is set as -155A at first. Then iref is step from -155A to +195A.
The setup in Fig. 7 (b) is the same as that in Fig. 7 (a) except for
an initial iref of +195A and a final value of -155A. As can be
seen from Fig. 7, the system can change over between the two
power flow directions fast and smoothly, demonstrating the
good dynamic performance of the system.
(a)
(b)
Fig. 7. Simulated waveforms of the SST with iref stepping from (a) -155A to
+195A and (b) +195A to -155A.
(a)
(b)
(c)
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7
(d)
(e)
(f)
Fig. 8. Simulated waveforms of the LLC SRC. (a) and (d): DC-link voltage and resonant current of the primary and secondary sides. (b) and (e): Drain to
source voltage and the gate to source voltage of the primary and secondary
sides MOSFETs. (c) and (f): Magnified view of the drain to source voltage and the gate to source voltage of the primary and secondary sides MOSFETs
nearby the peak and zero cross point of the input voltage. (a)-(c) are the
waveforms under full-load condition and (d)-(f) are the waveforms under light-load condition.
Fig. 8 presents the simulated waveforms of the LLC SRC,
where udsp, ugsp, udss and ugss are the drain to source voltage
of the primary-side MOSFET, the gate to source voltage of
the primary-side MOSFET, the drain to source voltage of
the secondary-side MOSFET and the gate to source voltage
of the secondary-side MOSFET, respectively. Figs. 8(a)-(c)
show the waveforms under full-load condition. As a
comparison, the results under light-load condition are
depicted in Figs. 8(d)-(f). Fig. 8(a) and Fig. 8(d) show the
DC-link voltage and the resonant current of the
primary-side and the secondary-side under full-load and
light-load conditions, respectively. Fig. 8(b) and Fig. 8(e) depict the drain to source voltage and the gate to source
voltage of the primary-side MOSFET and the
secondary-side MOSFET under full-load and light-load
conditions, respectively. Fig. 8(c) and Fig. 8(f) are the
magnified view of the waveforms nearby the peak(left) and
the zero cross point(right) of the input voltage in Fig. 8(b)
and Fig. 8(e), respectively.
As can be seen from Fig. 8(a) and Fig. 8(d), the DC-link
voltage of the primary and secondary sides exhibits the
absolute value of the sinusoid shape, and the envelope of the
resonant current of the primary and secondary sides are
sinusoidal corresponding to the input voltage. Besides, it can
be noticed from Fig. 8(c) and Fig. 8(f) that for the both sides
MOSFETs, the rising edge of the gate to source voltage lags
behind the falling edge of the drain to source voltage over full
input voltage and load ranges, which verifies the presented
ZVS scheme and careful ZVS design of the LLC SRC.
B. Experiments
To validate the theoretical analysis and simulation results, a
SST prototype was built, as shown in Fig. 9. Due to the lack of
the MV experimental facilities and laboratory space at present,
a 1 kW 220Vrms to 220Vrms low voltage prototype was
implemented. For the switches of the unfolding bridge and the
LLC SRC, the conduction losses are the major part, thus 600V,
72 mΩ MOSFET FCH072N60F from ON Semiconductor is
selected. While for the switches of the inverter, high speed
650V, 40A IGBT FGA40N65SMD is used.
The experimental results shown in Figs. 10-13 correspond to
the simulation results shown in Figs. 5-8, and the experimental
conditions are similar as these in the simulation except the
voltage and power levels. As can be seen from Figs. 10-13, the
experimental results match the simulation results well, except
for higher distortions of the input and output currents during
the reverse power flow direction. The main reason can be
attribute to the poor current control performance of the external
grid-connected inverter. Because the SST only controls the
output voltage, and the input and output currents of the SST are
determined entirely by the grid-connected inverter.
Fig. 9. Prototype of the developed SST.
Fig. 10. Experimental waveforms with forward power flow direction.
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8
Fig. 11. Experimental waveforms with reverse power flow direction.
(a)
(b)
Fig. 12. Experimental waveforms of the SST with iref stepping from (a) -6.3A
to +6.3A and (b) +6.3A to -6.3A.
(a)
(b)
(c)
(d)
(e)
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9
(f)
Fig. 13. Experimental waveforms of the LLC SRC. (a) and (d): DC-link
voltage and resonant current of the primary and secondary sides. (b) and (e): Drain to source voltage and the gate to source voltage of the primary and
secondary sides MOSFETs. (c) and (f): Magnified view of the drain to source
voltage and the gate to source voltage of the primary and secondary sides MOSFETs nearby the peak and zero cross point of the input voltage. (a)-(c) are
the waveforms under full-load condition and (d)-(f) are the waveforms under
light-load condition.
Fig. 14. Measured nominal efficiency of the SST prototype.
To evaluate the efficiency feature of the SST, the system
efficiency is measured by the HIOKI 3390 power analyzer, as
shown in Fig. 14. The measured nominal efficiency achieves
96.1%. This is acceptable for a low voltage/power rating direct
AC-AC SST. It can be known from the calculated loss
distribution that the LLC SRC conduction losses account for
the largest part of the converter losses. Accordingly, by simply
replacing the half-bridge configuration of the LLC SRC with
the full-bridge configuration, the conduction losses could be
roughly decreased by a factor of two, resulting in a higher
efficiency for the low voltage prototype. It should be noted that
the power consumed by the auxiliary power supply is also
taken into account in the measurement.
It can be seen from the experimental results above that,
sinusoidal input current and output voltage, bidirectional
power flow capability and both ZVS operation at the primary
and secondary sides of the LLC SRC over full input voltage
and load ranges are achieved in the presented SST. Thus the
correctness and feasibility of the SST topology and control
scheme are verified by the experiments.
VI. CONCLUSION
In this paper, a single-cell matrix-type SST based on direct
AC-AC topology is developed for the direct MV AC to LV AC
power conversion, where the LLC SRC with fixed voltage gain
is the isolated stage and it has simple operation and the
capability to achieve ZVS in all MOSFETs over full input
voltage and load ranges. An active control scheme is
implemented for the LLC SRC to realize ZVS on both sides, by
inserting a tiny phase shift between the primary and the
secondary side gate signals. Furthermore, the ZVS implements
for both the primary and secondary sides are analyzed in details,
and the system parameters optimum design method for
achieving ZVS over extremely wide input voltage and load
ranges is presented.
A PR control scheme of the inverter stage is presented, it
simultaneously controls the output voltage and synthetize input
currents where sinusoidal input currents and output voltages
are achieved. Finally, a low voltage/power SST prototype is
built, and the full functions and system performance of the SST
are tested and evaluated, experimental tests at different power
levels and power flow directions show that all the MOSFETs in
the LLC SRC are operated under ZVS over wide input voltage
and load ranges, and sinusoidal input current and controllable
output voltage are achieved, the measured nominal efficiency
of the SST reaches 96.1%, and the correctness of the proposed
methods are verified.
By having the advantageous features of direct AC-AC
conversion without energy storage element, high reliability,
high power density, sinusoidal input and output, the presented
SST also have the merits of ZVS operation over full input
voltage and load ranges, bidirectional power flow capability
and simple structure, which makes it potential to replace the
LFTs in the distribution network applications.
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Hui Wang received the B.S., M.S. and Ph.D. degrees
from Central South University, Changsha, China, in 2008, 2011 and 2014, respectively. Since 2016, he
has been with School of Automation, Central South
University. His research interests include matrix converter, DC/DC converters and solid-state
transformer.
Yichun Zhang was born in Hunan, China, in 1996.
He received the B.S. degree in electrical engineering
and automation from China University of Mining and Technology, Xuzhou, China, in 2017. He is currently
pursuing the M.S. degree in electrical engineering at
Central South University, Changsha, China. His research interests include modeling and control of
solid-state transformer.
Yao Sun (M’13) was born in Hunan, China, in 1981.
He received the B.S., M.S. and Ph.D. degrees from
the School of Information Science and Engineering,
Central South University, Changsha, China, in 2004,
2007 and 2010, respectively. He is currently with the School of Automation, Central South University,
China, as a Professor.
His research interests include matrix converter, micro-grid and wind energy conversion system.
Minghui Zheng received the B.E. and M.E. degrees,
in 2008 and 2011 respectively, from Beihang University, Beijing, China, and the Ph.D. degree in
Mechanical Engineering, in 2017, from University of
California, Berkeley, USA. She joined University at Buffalo, in 2017, where she is currently an assistant
professor in Mechanical and Aerospace Engineering.
Her research interests include advanced learning,
estimation, and control with applications to
high-precision systems.
Xiao Liang received the B.E. degree from Hunan
University, Changsha, China, in 2010, and M.S. and Ph.D. degrees from University of California,
Berkeley, USA, in 2011 and 2016, respectively, all in
Civil Engineering. He joined the Department of Civil, Structural and Environmental Engineering at
the University at Buffalo in 2018. His research
interests include health monitoring and inspection of infrastructure systems through advanced data
analytics, model-based and machine learning.
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2940514, IEEE Journalof Emerging and Selected Topics in Power Electronics
11
Guanguan Zhang received the B.S. degree and the
Ph.D. degree in automation and power electronics
and power transmission from Central South University, Changsha, China, in 2012 and 2018,
repectively. From December 2016 to December 2017,
she was a joint Ph.D. student supported by the China Scholarship Council with the Department of Energy
Technology, Aalborg University, Aalborg, Denmark,
where she focused on the reliability analysis of wind power system. She is currently a Postdoctoral
Research Fellow with the School of Control Science and Engineering,
Shandong University, Jinan, China. Her research interests include power converters, motor control and wind power system.
Kaiyuan Tan was born in Henan, China, in 1993. He received the B.S. degree from Central South
University, Changsha, China, in 2016. From 2016 to
2018, He worked for Pinggao Group Co., Ltd., which is a constituent company of State Grid of China. He is
currently pursuing the M.S. degree in electrical
engineering at Central South University, Changsha, China. His research interests include solid-state
transformer, fault diagnosis and fault-tolerant
control.
Jianghua Feng was born in Hengyang, China, on November, 19, 1964. He received the B.S. degree and
the M.S. degree in Electric Machine and Control
from Zhejiang University, Hangzhou, China respectively in 1986 and 1989 and his Ph.D. degree
in Control Theory and Control Engineering from
Central South University, Changsha, China in 2008. In 1989, he joined the staff of CSR Zhuzhou Institute
Co. Ltd., Zhuzhou, China, where he is CTO since
2010. His research interest is electrical system and its
control in rail transportation field, and now is a
professorate senior engineer and has several journal papers published in Proceedings of China Internat, IEEE International Symposium on Industrial
Electronics, International Power Electronics and Motion Control Conference,
IEEE Conference on Industrial Electronics and Applications, IPEC, IECON, ICEMS.