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ELET 3232Topic 18b: The I 2C Bus

Microcontroller Systems

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ObjectivesTo understand the basics of the I 2C busTo understand the format of a serialtransmission between I 2C devicesTo understand how AVR devicesimplement the I 2C bus

TWI: Two Wire Interface

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I2C IntroductionLow end serial communication optionDeveloped by Philips

Short for Inter-IC (integrated circuit) busOften used to communicate acrosscircuit-board distances

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I2C IntroductionI2C provides support for communication with:

Slow, on-board peripheral devices that are accessedintermittently

It is a simple, low-bandwidth, short-distanceprotocol.Most I 2C devices operate at speeds up to400Kbps

Some operate in the low megahertz rangeI2C has a built-in addressing schemeUsed to link multiple devices together

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I2C IntroductionPhilips originally developed I 2C forcommunication between devices inside ofa TV setExamples of I 2C-compatible devicesinclude:

EEPROMsThermal sensorsReal-time clocks

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I2C IntroductionI2C is also used as a control interface to signalprocessing devicesFor instance, it is commonly used in multimedia

applications including:RF tunersVideo decoders and encodersAudio processors

Philips, National Semiconductor, Xicor,Siemens, and other manufacturers offerhundreds of I 2C-compatible devices.

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I2C IntroductionI2C is appropriate for interfacing to devices on asingle board

Can be stretched across multiple boards inside a closedsystem, but not much further.

An example:A host CPU on a main embedded board using I 2C tocommunicate with user interface devices located on aseparate front panel board.

A second example:SDRAM DIMMs: can feature an I 2C EEPROM containingparameters needed to correctly configure a memorycontroller for that module

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SDA and SCLI2C is a two-wire serial bus

The two I 2C signals are serial data (SDA)and serial clock (SCL)

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Central

Microcontroller

Peripheral Device #1




SDA

SCL

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SDA and SCLSDA and SCL support serial transmission of8-bit

bytes of data-7-bit device addresses pluscontrol bits-over the two-wire serial bus.

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Central

Microcontroller





SDA

SCL

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SDA and SCLThe device that initiates communication isthe master

The master normally controls the clock signal.A device being addressed by the master is called aslave

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Central

Microcontroller





SDA

SCL

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Masters and SlavesAn I2C slave can hold off the master during atransaction

Uses what's called clock stretching (the slave keepsSCL pulled low until it's ready to continue)Most I 2C slave devices don't use this feature, but everymaster should support it.

The I 2C protocol supports multiple mastersMost system designs include only one

There may be one or more slaves on the busBoth masters and slaves can receive and transmitdata bytes

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Masters and SlavesEach I 2C-compatible slave device comeswith a predefined device address

The lower bits of which may be configurable atthe board levelThis limits the number of identical slave deviceson an I 2C bus without contention

The limit set by the number of user-configurableaddress bits (typically two bits, allowing up tofour identical devices)

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Masters and SlavesThe master transmits the device address of theintended slave at the beginning of everytransaction

Each slave is responsible for monitoring the bus andresponding only to its own address

There are four potential modes of operation for agiven bus device, although most devices only usea single role and its two modes:

master transmit master node is sending data to a slavemaster receive master node is receiving data from a slaveslave transmit slave node is sending data to a masterslave receive slave node is receiving data from the master

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Masters and Slaves

The master begins the communication by issuing thestart condition (S)

initially in master transmit mode

The master then sends a unique 7-bit slave deviceaddress, with the most significant bit (MSB) first

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Masters and Slaves

The eighth bit after the start, (read/not-write),specifies whether the slave is now to receive (0) orto transmit (1) dataThis is followed by an ACK bit issued by thereceiver, acknowledging receipt of the previous byte.

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Masters and Slaves

Then the transmitter (slave or master, as indicated bythe R/W bit) transmits a byte of data starting with theMSB.

At the end of the byte, the receiver (whether master orslave) issues a new ACK bit.This 9-bit pattern is repeated if more bytes need to betransmitted

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Masters and Slaves

When the master is done transmitting all of the databytes it wants to send in a write transaction (slavereceiving), it monitors the last ACK and then issuesthe stop condition (P)

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Masters and Slaves

In a read transaction (slave transmitting)The master acknowledges all bytes it receives (sends andACK bit) except the last one

It does not sends and ACK bit for the final byte it receives,it issues the stop conditionThis tells the slave that its transmission is done.

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How does the AVR implement

I2

C protocols?

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TWI: Two Wire InterfaceThe TWI protocol allows the systems designer tointerconnect up to 128 different devices using onlytwo bi-directional bus lines:

One for clock (SCL) and one for data (SDA).The only external hardware needed to implementthe bus is a single pull-up resistor for each of theTWI bus lines.

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The bus drivers of all TWI-compliantdevices are open-drain or open-collector.

This implements a wired-AND functionwhich is essential to the operation of theinterface.

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TWI: Two Wire InterfaceEach data bit transferred on the TWI bus isaccompanied by a pulse on the clock line.The level of the data line must be stable when the

clock line is high.The only exception to this rule is for generating startand stop conditions.

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TWI: Two Wire InterfaceThe master initiates and terminates a datatransmissionThe transmission is initiated when the master issues

a START condition on the busIt is terminated when the master issues a STOPcondition.Between a START and a STOP condition, the bus isconsidered busy, and no other master should try toseize control of the bus.

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Start/Stop/Repeated StartA special case occurs when a new START condition is issuedbetween a START and STOP condition.

Referred to as a REPEATED START conditionUsed when the master wishes to initiate a new transfer without

relinquishing control of the bus.After a REPEATED START, the bus is considered busy untilthe next STOP.START (and REPEATED START) and STOP conditions are

signaled by changing the level of the SDA line when the SCLline is high

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AddressesAll address packets are 9 bits long:

7 address bitsOne Read/Write control bit

If Read/Write = 1, a read operation will be performedIf Read/Write = 0, a write operation will be performed

One acknowledge bitWhen a slave recognizes that it is being addressed, it shouldacknowledge by pulling SDA low in the ninth SCL (ACK) cycle

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Typical Data TransmissionA transmission consists of a START condition, aSLA+R/W, one or more data packets, and a STOPcondition

SLA = Slave Address

An empty message, consisting of a START followedby a STOP condition is illegal.

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Using the TWI

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Interrupt BasedThe AVR TWI:

Byte-orientedInterrupt basedInterrupts are issued after all bus events:

Ex: reception of a byte or transmission of a START condition.

Two Control bits enable interrupts:TWI Interrupt Enable (TWIE) bit in TWCRGlobal Interrupt Enable bit in SREG

If both are enabled: assertion of the TWINT flag will generate an interruptrequestIf the TWIE bit is cleared (disabled), the application must poll the TWINTflag in order to detect actions on the TWI bus

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Interrupt BasedWhen the TWINT flag is asserted (high), the TWI has finishedan operation and awaits application response

The TWI Status Register (TWSR) contains a value indicating thecurrent state of the TWI bus

The TWINT flag is set in the following situations:After the TWI has transmitted a START/REPEATED START conditionAfter the TWI has transmitted SLA+R/WAfter the TWI has transmitted an address byteAfter the TWI has lost arbitrationAfter the TWI has been addressed by own slave address or general callAfter a STOP or REPEATED START has been received while still addressed as aslaveAfter the TWI has received a data byteWhen a bus error has occurred due to an illegal START or STOP condition

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TWI Bit Rate Register

TWBR selects the division factor for the bit rate generatorThe bit rate generator is a frequency divider which generates the SCL clock frequency in theMaster modes

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TWI Control Register

The TWCR is used to control the operation of the TWIEnables the TWIInitiates a master access by applying a START condition to the busGenerates a receiver acknowledgeGenerates a stop conditionControls halting of the bus while the data to be written to the bus are

written to the TWDRIndicates a write collision if a data write is attempted to the TWDRwhile the register is inaccessible

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TWINT:TWI Interrupt FlagThis bit is set by hardware when the TWI has finished its current joband expects application software responseIf the I-bit in SREG and TWIE in TWCR are set, the MCU will jump tothe TWI interrupt vector (the ISR)

While the TWINT flag is set, the SCL low period is stretched

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TWINT:TWI Interrupt FlagThe TWINT flag must be cleared through software by writing a logic one to it .Note that this flag is not automatically cleared by hardware whenexecuting the interrupt routine

Also note that clearing this flag starts the operation of the TWI, so allaccesses to the TWI Address Register (TWAR), TWI Status Register(TWSR), and TWI Data Register (TWDR) must be complete beforeclearing this flag.

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TWEA:TWI Enable Acknowledge BitThe TWEA bit controls the generation of the acknowledge pulse

If a one is written to the TWEA bit, the ACK pulse is generated on the TWI bus ifthe following conditions are met:

The devices own slave address has been receivedA general call has been received, while the TWGCE bit in the TWAR is setA data byte has been received in Master Receiver or Slave Receiver mode

By writing a 0 to the TWEA bit, the device can be virtually disconnected from the Two-wire Serial Bus (temporarily)

Address recognition can then be resumed by writing the TWEA bit to one again

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TWSTA:TWI START Condition BitThe application writes a 1 to the TWSTA bit when it desires tobecome a master on the Two-wire Serial BusThe TWI hardware checks if the bus is available, and generates aSTART condition on the bus if it is free

If the bus is not free, the TWI waits until a STOP condition is detected, and thengenerates a new START condition to claim the bus Master status

TWSTA must be cleared by software when the START condition hasbeen transmitted

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TWWC:TWI Write Collision FlagThe TWWC bit is set when attempting to write to the TWI DataRegister (TWDR) when TWINT is lowThis flag is cleared by writing data to the TWDR Register whenTWINT is high

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TWEN:TWI Enable BitThe TWEN bit enables TWI operation and activates the TWI interface.When a one is written to TWEN, the TWI takes control over the I/Opins connected to the SCL and SDA pinsIf this a 0 is written tot his bit, the TWI is switched off and all TWI

transmissions are terminated, regardless of any ongoing operation

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TWIE:TWI Interrupt EnableWhen a one is written to this bit, and the I-bit in SREG (GlobalInterrupt enable) is set, interrupts are enabled for the TWI

Whenever the TWINT flag is high, a TWI interrupt request is generated

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TWI Status Register

TWSR:TWS (7-3): TWI StatusThese 5 bits reflect the status of the TWI logic and the Two-WireSerial BusThe TWSR contains both the 5-bit status value and the 2-bit prescalervalue

The application designer should mask the prescaler bits to zero when checking theStatus bitsThis makes status checking independent of prescaler setting

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TWI Status Register

TWS:TWPS (1-0): TWI Prescaler BitsThese bits can be read and writtenThey control the bit rate prescaler (see slide 29)

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TWI Data Register

TWDR:In Transmit mode, TWDR contains the next byte to be transmittedIn receive mode, the TWDR contains the last byte receivedIt is not writable when the TWI interrupt flag (TWINT) is setThis occurs while the TWI is in the process of shifting a byte

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TWI Address Register (slave)

TWAR:The TWAR should be loaded with the 7-bit slave address (in the sevenmost significant bits of TWAR) to which the TWI will respond whenprogrammed as a slave transmitter or receiver , and not needed in themaster modesThe LSB of TWAR is used to enable recognition of the general calladdress ($00)

There is an associated address comparator that looks for the slave address (or generalcall address if enabled) in the received serial addressIf a match is found, an interrupt request is generated.

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Using the TWI

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ldi r16,(1

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Using the TWI

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wait1:in r16,TWCRsbrs r16,TWINTrjmp wait1

while (!(TWCR & (1

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Using the TWI

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in r16,TWSRandi r16, 0xF8cpi r16, STARTbrne ERROR

if ((TWSR & 0xF8) != START) ERROR();Step 3a:

Checks the value of TWI Status Register and masks theprescaler bits. If status is different from the START conditiongo to ERROR

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Using the TWI

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ldi r16, SLA_Wout TWDR, r16ldi r16, (1

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Using the TWI

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wait2:in r16,TWCRsbrs r16,TWINTrjmp wai t2

while (!(TWCR & (1

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Using the TWI

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in r16,TWSRandi r16, 0xF8cpi r16, MT_SLA_ACKbrne ERROR

if ((TWSR & 0xF8) != MT_SLA_ACK)ERROR();

Step 5a:

Checks the value of TWI Status Register and masks theprescaler bits. If the status is different from MT_SLA_ACK goto ERROR

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Using the TWI

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ldi r16, DATAout TWDR, r16ldi r16, (1

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Using the TWI

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wait3:in r16,TWCRsbrs r16,TWINTrjmp wai t3

while (!(TWCR & (1

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Using the TWI

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in r16,TWSRandi r16, 0xF8cpi r16, MT_DATA_ACKbrne ERROR

if ((TWSR & 0xF8) != MT_DATA_ACK)ERROR();Step 7a:

Checks the value of TWI Status Register and masks theprescaler bits. If the status is different from MT_DATA_ACKgo to ERROR

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Using the TWI

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ldi r16,(1

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SummaryWe discussed:

The basics of the I 2C busThe format of a serial transmission betweenI2C devicesHow AVR devices implement the I 2C bus

We looked in detail atTWI: Two Wire Interface on the ATmega128

topic 18-2 i2c

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