tomi report- 3rd

8/14/2019 Tomi Report- 3rd

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68000 Interrupt Structure

The 68000 Interrupt Structure has eight interruptpriority levels

The priority at which the processor is running at anygiven time is encoded in three bits of the processorstatus word with level 0 being the lowest priority

A request is accepted only if its priority is higher thanthat of the processor except for level 7 requests.


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Two Types Internal Interrupt

External Interrupt


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Internal Interrupt

The internal interrupt is a SoftwareInterrupt.

Generated when the 68000 executesa software interruption called TRAPor by some undesirable event.


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External Interrupts

has seven level of externalinterrupt [1-7]

Level 0 indicates no interruptservice is requested

Levels 1 to 6 are level-sensitive

Level 7 is edge trigerred


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The 68000 checks for and

accepts requests forinterrupts only betweeninstructions

Level 7 are non maskable

interrupt.Always acknowledged

Has the highest priority


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The processor automatically savesthe contents of the program counter

and the processor status word at thetime of the interruption.

Trace Bit (T) Enables a special type of interrupt called a

trace exception

Supervisor bit (S) Determines whether the processor is

running in the Supervisor mode (S=1) or

User mode (S=0)


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RTE (Return-from-exception)

At the end of the exceptionprocessing, this instructionrestores the 68000 to USER

mode

The 68000 can also providean autovector facility as analternative


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Pentium Interrupt Structure

Interrupts Nonmaskable Interrupt (NMI)

Maskable Interrupt

Enabled

Disabled


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Occurences of someinterrupt and exception

events causes the processorto branch to an interruptservice routine

Advanced ProgrammableInterrupt Controller (APIC)

EFLAGS processor statusregister (INTEL)


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Interrupt Enable Flag (IF)

Trap Flag (TF)

I/O Privilege Level (IOPL)


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Pentium processor has 4 levels ofprivilege (0-3).

Where Level 0 is the most highlyprivileged level

Switching from one level to anotherinvolves a number of checksimplemented in a mechanism calleda gate


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The processor takes the following actions:

1. Push processor SR, CS, and EIPonto stack pointed by ESP

2. If exception resulting from anabnormal execution condition, itpushes code on the stack

3. Clears the IF

4. Fetches the starting addressfrom Interrupt Descriptor Table


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After servicing the IRQ, the interrupt-service routine returns to theinterrupted program.

IRET pops EIP,CS and the processorSR from the stack into thecorresponding registers, thusrestoring the processor state


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Direct Memory Access

The capability provided by somecomputer bus architectures thatallows data to be sent directly from

an attached device (such as a diskdrive) to the memory on thecomputer's motherboard.


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DMA controller controlcircuit

To initiate transfer, the

processor sends the startingaddress, quantity, destination.

When the entire block istransferred, the controllerinforms the processor byraising an interrupt signal.


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OS is also responsible for suspendingthe execution of one program and

starting another

The program is in blocked state if

the transfer involves DMA


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R/W bit determines the direction of the transfer

IRQ, the controller sets the IRQ bit to 1 when it

has requested an interrupt IE, when this flag is set to 1, it causes the

controller to raise an interrupt after it hascompleted transferring a block of data

When the controller has completed transferring ablock of data and is ready to receive anothercommand, the Done flag is set to 1.


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DMAC options for datatransfer

CYCLE STEAL

BLOCK or BURSTmode


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Bus Arbitration

The process by which the next deviceto become the bus master is selectedand bus mastership is transferred to

it

Two Approaches

Centralized

Distributed


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Centralized Arbitration Bus Request Line

This is a wired-OR line: thecontroller only knows that arequest has been made by a

device, but doesn't knowwhich device made therequest.

Bus-Grant

This line is propagatedthrough all of the devices.


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Distributed Arbitration

The Distributed arbitration meansthat all devices waiting to use thebus have equal responsibility in

carrying out the arbitration process,without using a central arbiter


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tomi report- 3rd

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