today’s lab

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Start working with Xilinx [pronounced: Zy-links] ISE design suite Create new project Enter code Synthesize code Simulate code JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

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Today’s Lab. Start working with Xilinx [pronounced: Zy-links] ISE design suite Create new project Enter code Synthesize code Simulate code. Half Adder. AND to arrive at Carry XOR to arrive at Sum. Half Adder Verilog Code. module half_adder (A, B, Sum, C_out); input A, B; - PowerPoint PPT Presentation

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Page 1: Today’s Lab

Start working with Xilinx [pronounced: Zy-links] ISE design suite◦Create new project◦Enter code◦Synthesize code◦Simulate code

JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Page 2: Today’s Lab

AND to arrive at Carry XOR to arrive at Sum

Inputs Outputs

A B S C0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Page 3: Today’s Lab

module half_adder (A, B, Sum, C_out); 

input A, B;output Sum, C_out;

 xor (Sum, A, B);and (C_out, A, B);

 endmodule

JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Page 4: Today’s Lab

JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Page 5: Today’s Lab

JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Page 6: Today’s Lab

JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Page 7: Today’s Lab

JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Page 8: Today’s Lab

JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Page 9: Today’s Lab

JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012