to be submitted, vol. 99, no. 9, june 2016 1...

TO BE SUBMITTED, VOL. 99, NO. 9, JUNE 2016 1

Design and Analysis of Energy RecyclableBidirectional Converter with Digital Controller for

Multichannel MicrostimulatorsPaul Jung-Ho Lee, Student Member, IEEE, Man Kay Law, Member, IEEE, and Amine Bermak, Fellow, IEEE

Abstract—The power supply modulated microstimulator sys-tem can drive an expandable electrode array with reducedheat generation across the current drivers and high stimulationefficiency. Although plenty of research efforts have been pourinto demonstrating various applications of the power supplymodulated microstimulators, a comprehensive analytical mod-elling of the system to investigate internal and external energyflow during biphasic stimulation pulses spanning over varyingloading configurations (e.g. number of electrodes, and stimulationcurrent amplitude) is still lacking. This paper fills the researchgap by presenting the systematic tools for attaining insights ofa stimulator system featuring a bidirectional DC-DC converterwith an algorithmic digital controller. The models employed hereare based on traditional analytical methods such as transferfunctions and state-space dynamic models incorporating variousenergy loss circuit elements. With the models, the behaviour andpower efficiency under a wide range of parameters associatedwith stimulator is attained. Numerical assessment reveals thatthe digital controller can track the output supply voltage at thephase transition boundaries just in tens of switching cycles. Thesystem was also studied on a verification platform, where theinternal signals of the digital controller were carefully examined.Measurement results show that the system behavior well matchedto the simulation results, demonstrating the effectiveness of theanalytical system model for obtaining key insights for genericlarge-scale micro-stimulator designs.

Index Terms—Electrical Stimulator, power supply modulation,energy recycling DC-DC converter.

I. INTRODUCTION

MULTI-channel microstimulator is the main apparatus

for strenuous efforts for establishing a link between

an artificial sensor and a high-density nerve array such as

the retina and the cortex [1]. A stimulator innervates neurons

by artificially modulating excitatory postsynaptic potential, by

sourcing and sinking charge packets into and from the axon

hillock region of neurons [2]. Recently, electrical stimulation

of high-density electrode array (> 1, 000) emerges as an

important engineering interest, engendered by technological

advances appeared in nanofabrication of electrode array [3]

and deep-submicron high-density current driver circuits [4].On the one hand, the primary design concern of multi-

channel microstimulators is to suppress the worst-case tem-

perature rise under 1 ∼ 4.5◦C [5] with high stimulation

Paul Jung-Ho Lee and Amine Bermak are with the Smart Sensory IntegratedSystems (S2IS) Lab, the Department of Electrical and Computer Engineering,Hong Kong University of Science and Technology, Clear Water Bay, HongKong, China (e-mail: [email protected], [email protected]).

Man Kay Law is with the State Key Laboratory of Analog and Mixed-Signal VLSI, Macau University, Macau, China (e-mail: [email protected]).

Manuscript received April 19, 2005; revised December 27, 2012.

efficiency. To reduce the heat generation from the conduction

paths across the current drivers, power supply voltages should

be adaptively adjusted according to instantaneous electrode

voltage. On the other hand, for the connection with multi-

channel electrode array, the modulated power supply and

the electrode current drivers should be decoupled, because a

dedicated voltage waveform generation circuits allocated for

each stimulation channel is superfluous. The decoupling is

also essential for the stimulation of many therapeutic target

sites such as vagus nerve [6] and subthalamic nucleus [7],

considering they are served with intermittent stimulations

at the instances of abnormal events. Hence, in the generic

multi-channel stimulator system, a separate energy storage is

dedicated for storing energy harvested from various power

sources (e.g. [8]), and then the energy stored in the storage

is utilized for stimulations. For this reason, the direct voltage

forming based topologies [9]–[12], in which the instantaneous

voltage required for sourcing or sinking a specific amount of

the current into or out of electrodes is directly applied to the

electrodes, are not feasible for the multi-channel stimulator

applications. Thus, a power supply serving for a generic multi-

channel stimulators should modulate the voltage at an inter-

mediate energy storage capacitor (IESC) instead of directly

delivering charge into the electrodes.

A generic stimulator in which the stimulation current drivers

are decoupled and connected to a power supply modulating

DC-DC converter is demonstrated in [13]. The power supply

incorporated in [13] takes advantages of two main stimulator-

application-specific features to achieve a fast tracking speed

(< 10μs) at low switching frequency (< 1MHz). Taking

those application-specific features into account, some of the

important performance measures for traditional power supply

controllers can be traded off for a compact, low-power, digital

controller. Conventional performance requirements that can be

alleviated in the proposed controller include fast adaptation to

load transient with regulated output voltage dipping, smooth

step response without excessive oscillatory output behaviour,

and fast reference tracking speed without output voltage peak-

ing. Two important features of the stimulation waveform make

this alleviation possible.

The first feature to be exploited is found during the

initialization step at the beginning of the phase transition

boundaries, when the output voltage exhibits abrupt ramp-

up or -down. At the phase transition boundaries, the current

drivers start to conduct current into the electrodes only after

the power supply voltage reaches a predefined voltage that

This is the Pre-Published Version


can operate the current controlling transistors in the saturation

mode. Therefore, the short-term output voltage peaking can be

tolerated during the initialization of a new phase, because the

current drivers are ensured to be inactivated at the moment.

The second useful feature is that the time rate of the target

voltage change is slow at less than tens of mV/μs without

load transient, once the power supply voltage crosses the initial

target voltage level required for current drivers. After reaching

an initial operable voltage, a stimulator slowly changes its

state variables such as duty ratio and pulse skipping frequency,

adapting to an operating condition determined by the number

of simultaneously driven electrodes and current amplitude at

a stimulation phase.

In this paper, an in-depth evaluation effort of the proposed

multichannel microstimulator system is provided, comple-

menting the key concepts and silicon prototype demonstrated

in [13]. The comprehensive analysis and simulation assess-

ments for the proposed stimulator achieve following aims:

• To set up a design guideline for reducing the wasted

energy, the flow of energy from the power source to the

electrodes with corresponding energy loss sources during

biphasic stimulations is identified.

• To get insights on the influence of the individual sub-

system on the system performance, the transfer functions

corresponding to the system blocks are derived using the

linearization techniques.

• To observe the time-domain behavior of the system with

varying system and component parameters, a state-space

model is provided.

• To ensure the stability of the system, simulations covering

a wide range of the system configurations were performed

and some phase-portraits at the parameter corners are

provided.

• To observe real-time trajectories of the internal states

during a biphasic stimulus, an experimental system was

built and demonstrated.

The rest of the paper is organized as follows. Section II

describes the operation of the proposed system from various

aspects including a biphasic stimulation scenario, a single

switching cycle, and algorithm. Then, the dissection of power

consuming elements in the system and analytic system models

are presented in Section III. Section IV assesses the reliability

of the system from corner simulations and proof-of-concept

system emulations. Section V concludes the paper.

II. SYSTEM DESCRIPTION

The overall block diagram is shown in Fig. 1. Here, an

electrode was approximated by a resistor (Ra) in series with

a capacitor (Cdl), assuming that the irreversible chemical

reactions at the electrode is negligible. Ra is the access

resistance which models the resistance of hydrolyte at the

tissue-electrode interface. Cdl is the double layer capacitance

representing the charge-transfer contributed by ionic redox

reaction in the Helmholtz layer, which is adjacent to the

metallic surface of the electrode [14]. Similar to [10], the

proposed stimulator system employs an switching mode power

supply (SMPS) operating in forward buck and reverse boost

Ielec,src

Ielec,sink

– Vsg

P +

VDD

VSS

...

VSUP

Velec

S1 16

16+ VgsN –

VgC1

C2

L1D1IL

D2

Voffset

S2MN1

MP1Vx

ElectrodeArray

Velec

VSUPVDD

VSS

...

S5

S3

S4

Cdl

Ra

Vmid

DPWM 2-ch ADC CurrentDAC

ElectrodeArray

Controller

D-PS-PWM-QPIDController

16

64

64

P1

P2

P3

P4

Fig. 1. The generic high-density micro-stimulator system with power-supplymodulation and energy recycling.

modes during anodic and cathodic stimulation phases, respec-

tively. However, the proposed system doesn’t require a current

sensor that increases circuits complexity causing extra power

consumption per channel.

The micro-stimulator system shown in Fig. 1 maneuvers

the SMPS, which is tethered to an array of current drivers

to efficiently generate biphasic stimuli to the electrode ar-

ray. In the cathodic stimulation phase, the modulated power

supply (VSUP ) tracks a reference voltage, which is set to

Velec − Voffset. The offset voltage have to be larger than

the voltage headroom of the current control transistors (con-

ducting Ielec,src, Ielec,sink), and vice versa in the anodic

stimulation phase. In the anodic stimulation phase, on the

other hand, VSUP follows the reference voltage which is set to

Velec − Voffset. The system comprises the power source Vg ,

the input filtering capacitor C1, an array of complementary

power switches (MP1, MN1), 2 diodes (D1, D2), an inductor

(L1), an array of the intermediate energy storage capacitors

(C2), a current DAC, a 2-ch ADC, and a digital controller

(D-PS-PWM-QPID) for giving instructions to a digital pulse

width modulation (DPWM) block that turns on and off the

power switches. The load-adaptive power transistor scaling

(APTS) and intermediate capacitor scaling (AICS) schemes

are employed for attaining a reasonable power conversion

efficiency (PCE) of the SMPS regardless of loading conditions,

by reducing the switching loss incurred by charging and

discharging of the gate capacitance of the power transistors

(PT) and the intermediate energy storage capacitor (IESC).

These schemes are popular techniques that used when the

loading dynamic range is large and the voltage conversion ratio

(VCR) coverage is wide [15]–[18]. For maintaining reasonable

PCE (∼80%), the effective switching frequency is adjusted to

a lower level by means of ‘pulse skipping’ when driving small

load power, as is employed in [19]–[21].

A. Time Domain Description

The proposed system uses the buck converter for forward

energy transmission from the power source to the double



0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2x 10

02468

1012

Time

Volta

ge (V

)

Adaptive Supply VoltageElectrode Voltage

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2x 10

10.5

00.5

11.5

2

Time

Indu

ctor

Cur

rent

(A)

(a)

(b)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2x 10

0

5

10

15

Time

Duty

Lev

el (0

~ 15

)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2x 10

0.04

0.02

0

0.02

0.04

Time

Elec

trode

Cur

rent

(A)

(c)

(d)

Fig. 2. Waveforms of the proposed stimulation system during a set ofcathodic-first bi-phasic stimulation pulses: waveforms of (a) the voltage at thepower supply rail (VSUP ) and the voltage at the electrode interface (Velec).(b) the current flowing through the inductor (L1). (c) the duty cycle command.(d) the total current amplitude flowing through the electrodes array.

layer capacitance (Cdl), and boost converter for backward

energy transmission from Cdl back to the power source.

Fig. 2(a) portrays a waveform of the voltage at the supply

voltage node (red line, VSUP in Fig. 1) and the voltage at

the electrode interface (green line, Velec in Fig. 1), when

driving 64 electrodes with a pair of cathodic-first biphasic

pulses having attributes of 1ms pulse width and ±600μAcurrent amplitude. The target voltage headroom across the

current controlling transistors (Voffset) was set to 1V . All

the simulations in this paper were performed using the design

parameters shown in TABLE I, if not otherwise specified.

At the onset of a stimulation cycle, both VSUP and Velec

are initialized at the bulk tissue potential (Vmid), which is

defined by a reference electrode exhibiting very fast kinetics

to effectively work as a voltage regulator [22]. Then, the

stimulator drives VSUP to a voltage level defined as Vref,rev ,

where Vref,rev = Velec − Voffset − IDAC ×Ra, IDAC is the

driving current controlled by the current DAC, and Ra is the

electrode access resistance. Voffset should be large enough

to operate the current controlling transistors into saturation

region. The regulated drain-source voltages (Voffset) ensures

a reasonably high output resistance of the current drivers,

which, in turn, attenuates the voltage ripple at the power supply

(VSUP ). Thus the current flowing through the electrode is

kept consistent. To reach the target reference voltage (Vref )

as fast as possible, the controller quickly increases the 4-bit

(b)(a)

Vx

IL

Vx

IL

tswftswf Vx

IL

Vx

IL

tswrtswr

VgsN

Vx

IL

VSUP

Ts

T1 T2 T3

Vx

VsgP

IL

VF

VSUP

tswrVx

IL

trrbVx

IL

tVFttswr trrbt

Ts

T1 T2 T3

IL

tswrVx Vx

IL

trrbtttswr trrb

time time

Vx

VgsN

IL

VSUP

Ts

T1 T2 T1

Vx

VsgP

IL

VSUP

Ts

T1 T2 T1

ttt tt

(d)(c)

time time

VDD

Ielec,sink

Ielec,src

VF

VF VF

VF

VF VF

VF

VDD

VDD VDD

Fig. 3. Key waveforms during a cycle of the forward-buck conversion phaseand the reverse-boost conversion phase. Timing diagram for (a) the DCMforward-buck operation, (b) the DCM reverse-boost operation, (c) the CCMforward-buck operation, and (d) the CCM reverse-boost operation.

duty number, as shown in the Fig. 2(c). The rule for duty

update is detailed in Sec. II-D. Once VSUP reaches Vref , the

controller turns on the switches between the electrode and

the current driving transistors (S4 in Fig. 1). Then, cathodic

current starts to flow from the electrode to the C2, discharging

the double layer capacitor (Cdl), resulting in a downward slope

voltage waveform. At the moment that the current starts to flow

through the electrode, Velec drops further by IDAC ×Ra. The

charges collected on C2 are relayed into the power source

through the reverse boost converter operation which will be

explained in Sec. II-B. At 1ms, the cathodic phase ends, and

the anodic phase starts. At this boundary, SMPS should swiftly

escalate the output voltage from Vref,rev to Vref,fwd, where

Vrev,fwd = Velec + Voffset + IDAC × Ra. In the simulation

shown in Fig. 2(a), where IDAC = 600μA, the required

quantum leap of the output voltage is 5.6V , or 28% of the

rail-to-rail voltage. Responding to the fast transient of Velec at

the phase transition boundary, the proposed nonlinear digital

controller rapidly ramps up the duty number to accelerate

the speed of charge delivery from the power source to C2,

as shown inside the green oval line of Fig. 2(c). At this

boundary, the converter operates in continuous conduction

mode (CCM) as shown in the inset of Fig. 2(b), while the



0 10 20 30 40 50 60

0

50

100

Number of electrodes

Perc

enta

ge (%

)Energy Saving Percentage vs. Number of Electrodes (IDAC = 100 uA, Voffset = 1 V)

4 levels8 levels16 levels32 levels64 levels

0 10 20 30 40 50 60

0

50

100


Perc

enta

ge (%

)

Energy Saving Percentage vs. Number of Electrodes (IDAC = 300 uA, Voffset = 1 V)


0 10 20 30 40 50 60

0

50

100


Perc

enta

ge (%

)

Energy Saving Percentage vs. Number of Electrodes (IDAC = 600 uA, Voffset = 1 V)


(a)

(b)

(c)

Fig. 4. Wasted energy saving percentage vs. number of stimulating electrodesfor various PT and IESC scaling levels, when (a) IDAC = 100μA , (b)IDAC = 300μA , and (c) IDAC = 600μA.

converter operates in discontinuous conduction mode (DCM)

during current stimulation. In the simulation shown in Fig. 2,

it takes 8 switching cycles (16μs) to cross over the target

voltage, which is set to Vref,fwd. As a result of the rapid inrush

current incurred by the increase in duty cycle, there is a voltage

overshoot across C2 at the beginning of the anodic stimulation.

The overshoot causes no harmful ramification on tissue such as

over-current into the electrode because the current controlling

transistors serve as barriers between the power supply and

the electrodes. When VSUP crosses over Vref,fwd, current

starts to flow from C2 to the electrode array, for the rest of

the 1ms anodic pulse duration. At the inter-phase boundary,

Velec rises by an amount of IDAC × Ra. During the anodic

stimulation phase, charges are transferred from the power

source to the electrode via C2, and are accumulated on Cdl

resulting in an upward slope waveform of Velec. At the end

of a complete stimulation cycle (2ms), the electrode voltage

returns to its original value. The above discussion assumes that

all the electrochemical processes taking place on the electrode

surface induce only reversible hydrogen plating and capacitive

redistribution, devoid of irreversible hydrogen evolution or

toxic dissolution of noble metals, such as Ir or Pt [22].

B. Single-Cycle Operation of the Bidirectional Converter

In this section single-cycle operations of the forward-buck

and the reverse-boost DC-DC converters are described for

further analysis on the energy usage of the system. The

primary role of the DC-DC converter is to modulate the VSUP

by charging and discharging C2 in Fig. 1. It operates in

Retrieve Vsup[n] and Velec[n]

START

Verr[n] = |Vsup ref[n]|;err[n] = Verr[n] - Verr[n-1];

Verr[n] > Vthres1

Verr[n] > 0

Verr[n] > Vthres2

cont_pulse_cnt[n] > Cont_Pulse_Cnt_Max

no_pulse_cnt[n] > No_Pulse_Cnt_Max

duty[n] = duty[n-1] + 1

duty[n] = duty[n-1] + 1

duty[n] = duty[n-1] + 1;cont_pulse_cnt[n] = 0;

duty[n] = duty[n-1] 1;no_pulse_cnt[n] = 0;

END

Vref[n] = Velec[n] + VRa + Vcompl

cont_pulse_cnt[n] =cont_pulse_cnt[n-1] + 1;no_pulse_cnt[n] = 0;Apply one pulse;

no_pulse_cnt[n] =no_pulse_cnt[n-1] + 1;cont_pulse_cnt[n] = 0;

Yes

No

Yes

Yes

Yes

Yes

No

No

No

No

Fig. 5. Flowchart of the Digital Pulse-Skipping PWM Controller with Quasi-PID Duty Update. (Adopted from [13])

the forward-buck or reverse-boost mode to ramp up or down

VSUP , respectively.

Fig. 3(a) illustrate DCM operations for the reverse-boost

case. During the time period annotated with T1, the controller

turns on the NMOSFET switch (MN1), by raising VgsN to

“high”. In this period, the current (Ielec,sink) starts to flow

from C2 to VSS . Ielec,sink linearly increases with a slope ofVSUP−VSS

L . In the beginning of the period, MN1 discharges the

Vx node to VSS . After that, during the time period annotated

with T2, the controller turns off MN1, pulling down VgsN to

“low”. In this period, energy stored in L1 forces the current

(IL) back into the power source, gradually decreasing its

magnitude with the slope of −VDD+VF−VSUP

L , where VF is

the diode forward drop voltage of D1. In the beginning of

the period, energy stored in L1 sets the voltage at Vx to

VDD + VF , closing the conduction path through D1. When

all the energy stored in L1 is released, L1 acts as a DC short

circuit connecting VSUP and Vx. This period is annotated with

T3, where IL returns to zero after delivering a short period of

the diode reverse recovery current.

Fig. 3(c) illustrates the CCM operation for a switching

cycle. The system starts to operate in CCM, when the in-

cremental inductor current during a switching cycle – ΔIL =VSUP−VSS

L DTs – is greater than the current flowing into C2

(Itransition), where D is the duty ratio and Ts is the switching

period. The converter operates in CCM at the phase transition

boundary, when the stimulation mode changes from cathodic

to anodic or vice versa. The average current required for charg-

ing the ascending VSUP during the cathodic-to-anodic phase

transition period is Itransition =C2·(2·Voffset+2·IDAC ·Ra)

ΔTtransition,



where ΔTtransition is the time to take for the output voltage

transition [13]. Thus, the SMPS is more likely to operate in

a deeper CCM region, when Ra, Voffset, and C2 are greater,

and the fact tells us that, when the number of simultaneously

driving electrodes increasingly, C2 should also be up-scaled

accordingly, as is done by AICS scheme.

VSUP decreases when the magnitude of IL is greater than

the total sinking current through the electrodes array, Ielec,sink(shown in 3(a) as a dashed pink line), and increases when the

magnitude of IL is smaller than Ielec,sink. In the forward buck

converter operations, illustrated in Fig. 3(b),(d), the energy

flow direction is the opposite of that during the reverse boost

operation. In the anodic stimulation phase, Ielec,src flows

from C2 to the electrodes. The energy consumed from C2

is recharged from Vg by the forward buck operation of the

SMPS.

C. Existing Controllers Considered for the PSM Stimulator

To understand why an yet another controller design is

necessary for the bi-directional converter employed for the

PSM stimulator, we first consider basic requirements that a

controller for the SMPS used in the power supply modulated

stimulator has to fulfill. The controller has to:

• operate robustly notwithstanding the varying power-stage

transfer function, which is induced by adaptive scaling of

the power transistor and output capacitance.

• be able to accommodate a wide dynamic range of output

load, since the stimulation current amplitude and the

number of simultaneously driving electrodes ceaselessly

changes.

• swiftly track the discontinuity of the reference voltage

appearing at the inter-phase boundary.

• be simple enough to avoid the usage of the power- and

area- hungry solutions such as a high-frequency-clocked

DSP.

Although there have been a tremendous amount of the efforts

to tackle some of those challenges listed above, to our best

knowledge, they could only satisfies part of the requirements

among them. Conventional full-fledged DC-DC converters are

designed to robustly exhibit a nimble output response with

a suppressed output voltage ripple and ringing [23], [24].

However, in the DC-DC converter for stimulator application,

some degree of output voltage peaking and ripple is accept-

able, only if the output supply voltage can put the current

controlling transistors in saturation mode; the influence of the

ripple voltage on the current amplitude is attenuated due to

high output resistance of the current controlling transistors.

In the proposed D-PS-QPID-PWM controller, we took the

advantages coming from the relatively loose ends, to meet all

those above mentioned requirements of the stimulator appli-

cation. There are two classes of the solutions to decouple the

DC-DC converter design and the varying power-stage function

while maintaining broad output load dynamics coverage: 1)

nonlinear controllers such as hysteretic or sliding mode (SM)

controllers, and 2) autotuning pulse width modulation (PWM)

controllers. Both controller types can drive the load having

wide dynamic ranges of impedance and voltage, because the

nonlinear controllers always reach the stable operating point

in phase plane, and the autotuning PWM controllers namely

“tune” the controller parameters according to the obtained

frequency characteristics of the power-stage.

Among these, the simplest option we can consider is the

hysteretic controller, which only checks the output voltage

with two comparators, and determines the on and off trip

points of the controlling switch [25]. However, it has feasible

operating regions only in the buck converter with resistive

load [26], and is therefore not suitable in our application

that also requires boost mode operation. The autotuning PWM

controllers, which also can be considered for applying to the

stimulation system, dynamically adjusts the parameters of the

compensation controller based on observing the perturbed test

signal [27], [28] or the time-domain characteristics of the com-

pensated error signal [29]. However, achieving a fast transient

response at large-signal time-varying reference voltage with

linear PWM controllers is a very daunting task [30]–[32], since

they are optimized for a specific small-signal operating point.

Moreover, the implementation of autotuning compensator and

observer circuitry is imposes a challenging problem.

The most viable candidate for the PSM stimulator applica-

tions is the SM controllers. The SM controllers continuously

monitor all the time-varying state variables such as the output

voltage error, its derivative and integral, and the inductor

current. The controller commands the power switches to direct

the trajectory of the state variables to follow a sliding surface

toward a stable operating condition. The sliding surface dic-

tates built-in desirable dynamical characteristics that a control

law want to enforce the system to abide by [33]. Thus, when

we let the system to stay on the sliding surface, the system is

unconditional stable and robust, regardless of the fluctuation

of line voltage and load condition and the system parameters,

such as inductor value and switching frequency. However, de-

sign and implementation of the strict SM controllers incur high

cost, since the electronic circuitry involving the switching-

inputs should be meticulously designed to satisfy the hitting,

existence, and stability conditions [34]–[37].

Despite the sophisticated SM controllers making them un-

suitable to be directly applied in an implant system, the princi-

ple of the SM control serve as a conceptual foundation in the

design of the proposed digital pulse-skipping PWM controller

with quasi-PID duty update (D-PS-PWM-QPID), as in the

majority of nonlinear controllers [37]. Indeed, the proposed

controller can be described in terms of the SM controllers [33],

where the switching manifold is a hyperplane defining the

error between VSUP and the target voltage diminishes to zero.

In the reaching phase, VSUP will be driven to a target voltage

to prepare for the DAC to steer current trough the transistors,

and in the sliding-mode phase, VSUP is induced into the

switching manifold.

D. Operation of the D-PS-PWM-QPID Controller

. Shown in the first decision branch of Fig. 5, the D-PS-

PWM-QPID controller judges whether it needs to move an

electric charge from CIESC , and skips a pulse at the consecu-

tive switching cycle, similar to the pulse skipping modulators



demonstrated in [19]–[21]. At an initial boundary state when a

new phase starts, VRef is set to Velec+Voffset+ IDAC ×Ra.

Here, the values of IDAC ×Ra for the possible set of discrete

values of IDAC are tabulated and stored in a read only memory

(ROM) to avoid unnecessary multiplication. The controller

updates the duty in a manner that is similar to the traditional

proportion-integral-differential (PID) controller. The duty is

encoded into 4-bit digital codes, thus providing 16 levels of

time division of the switching cycle for the digital pulse width

modulation (DPWM). The effective resolution of the DPWM

is calculated as RDPWM = log2(2NDPWM /Dmax

), where

Dmax is the maximum duty cycle, NDPWM is the bit-length

of the duty value. Here, we can tune RDPWM by adjusting

Dmax, so that the SMPS can adopt to the asymmetric output

voltage range depending on the phase. For instance, when

the SMPS need to drive the cathodic-first bi-phasic stimuli,

as shown in Fig. 2, VSUP spans a range between 2V and

12V when Vg = 20V . Hence, we adjusted Dmax of the

forward buck operation (Dmax ≈ 0.7, RDPWM ≈ 4.51) to

be less than that of the reverse boost operation (Dmax ≈ 0.3,

RDPWM ≈ 5.74), to balance the IL slope by compensating

the difference between Vg − VSUP and VSUP .

When the controller determines to turn on the power switch,

which shorts the conduction path between the power source

(Vg) and the IESC (C2), it increases the cont pulse cntcounter value, which stores the history of the number of

the consecutive switching cycles without pulse skipping, and

resets the no pulse cnt counter value, which stores the

history of the number of the dormant cycles with pulse

skipping. When the controller decides to skip a switching

cycle, in contrast, it increases the no pulse cnt, and reset the

cont pulse cnt. The two counter values convey ‘time integral’

information to the controller; when cont pulse cnt is larger

Cont Pulse Cnt Max, the controller routine judges that the

duty is higher than a desired level and increase the duty by one;

while no pulse cnt is larger than No Pulse Cnt Max, the

controller judges that the duty is lower than the desired level

and decrease the duty by one. In effect, Cont Pulse Cnt Maxdictates the maximum consecutive active switching cycles,

while No Pulse Cnt Max puts a lid on the maximum pulse

skipping cycles. The ‘proportional and derivative’ parts of the

duty update are quite straight forward; the duty increases by

one when Verrror is greater than V thres1, and decreases by

one when the differential error, ΔVerror[n] = Verror[n] −Verror[n− 1], is greater than V thres2. The duty update logic

can be embodied with four 8-bits digital comparators (2 for

integral, 1 for proportional, and 1 for derivative control) and

one duty counter.

III. SYSTEM ANALYSIS

An ideal adiabatic electrical stimulator system transfers the

energy from the source directly into the electrodes array, and

then recollects the energy on the double layer capacitance

of the electrodes back into the energy source. Thus, without

considering energy losses, net total energy consumption of

the bidirectional DC-DC converter-powered stimulator during

a biphasic pulse cycle is zero. However, the energy loss during

0 10 20 30 40 50 6050

55

60

65

70

75

80

85

90

95

100


Perc

enta

ge (%

)

SMPS Power Conversion Efficiency (%) vs. Number of Electrodes(Voffset = 1 V, Nlv,max = 16)

forward buck PCE (IDAC = 100 uA)reverse boost PCE (IDAC = 100 uA)forward buck PCE (IDAC = 300 uA)reverse boost PCE (IDAC = 300 uA)forward buck PCE (IDAC = 600 uA)reverse boost PCE (IDAC = 600 uA)

Fig. 6. Simulated power conversion efficiency of the proposed SMPScalculated during a set of the biphasic stimuli, as Nelec increases from 0to 64, when Voffset = 1V .

the charge delivery conducted by the SMPS is inevitable, and

we need to study the energy flow from the power source to the

electrodes to figure out how the energy is consumed during the

transmission. These loss sources are accounted in the simulator

which is based on the state space model, which is also detailed

in this section. Using the simulation parameters of the Table I,

the PCE as a function of Nelec is plotted in Fig. 6, with the

loss equations that will be discussed in this section.

A. Power Consumption

In the proposed system, the energy drawn from the power

source is lost as: 1) heat in the current sources and electrodes,

and 2) the conduction, switching, and core losses in SMPS.

And the remaining energy less the losses is recovered to

the power source. In the cathodic stimulation phase, energy

is drawn from double layer capacitances of the electrode;

then the energy is gradually stored in the inductor as the

inductor current (IL) amplitude rises; and the energy is finally

transferred to the power source as IL amplitude decreases.

In the anodic stimulation phase, electric charge is transferred

from an energy reservoir (Vg), passes through the IESC,

then arrives at the electrodes, ramping up VSUP to track the

time-dependent incremental evolution of Velec. The remaining

portion of the energy drawn from Vg but not recovered to the

source are consumed by the SMPS operations (Ploss,SMPS)

and the current driving operations in the current controlling

transistors and the access resistances (Ra) of the electrodes

array (Ploss,CS). This portion of energy which is irrevocably

lost during the stimulation is expressed as

Eloss,PSM,cyc =

∫ Ts

t=0

Pfrom,src(t)dt−∫ Ts

t=0

Pto,src(t)dt

=

∫ Ts

t=0

Ploss,SMPS(t)dt+

∫ Ts

t=0

Ploss,CCT (t)dt

+

∫ Ts

t=0

Ploss,Ra(t)dt, (1)

where Pfrom,src(t) represents the instantaneous power drawn

from the source at the time t, during the forward buck oper-

ation, Pto,src(t) represents the instantaneous power restored

back to the source at the time t, during the reverse boost



0 10 20 30 40 50 60

10

20

30

40

50

60


Powe

r (m

W)

Composition of power usage vs. Nelec (IDAC = 100 uA, Voffset = 1 V)

Composition of power usage vs. Nelec (IDAC = 600 uA, Voffset = 1 V)

Avg. power drawn from the power sourceAvg. power recovered to the power sourceAvg. SMPS power lossAvg. power loss in current sources and electrodes

0 10 20 30 40 50 60

100

200

300

400


Powe

r (m

W)

Avg. power drawn from the power sourceAvg. power recovered to the power sourceAvg. SMPS power lossAvg. power loss in current sources and electrodes

(b)

(a)

Fig. 7. Average power compositions pertaining to a set of the bi-phasicstimuli, as Nelec increases from 0 to 64, when (a) IDAC = 100μA, and(b) IDAC = 600μA. The power loss in current sources and electrodes is theaverage of Ploss,Ra + Ploss,CCT during a pair of biphasic stimuli.

operation, Ploss,Ra is the conduction loss across the access

resistance of electrode, and Ploss,CCT is the conduction loss

across the current controlling transistors. Both Pfrom,src(t)and Pto,src(t) can also be expressed in relation to the instan-

taneous power used for energizing the inductor (PL,stored) as

Pfrom,src(t) = PL,stored(t) + Ploss,SPMS(t) (2)

Pto,src(t) = PL,stored(t)− Ploss,SMPS(t), (3)

where Ploss,SMPS is the cost that we have to pay to reduce

Ploss,CCT , compared to the current-source-based stimulator

system. The average power composition during a biphasic

stiulation cycle as a function of Nelec is shown in Fig. ??,

in terms of Pfrom,src, Ploss,SMPS , Ploss,Ra, Ploss,CCT , and

Pto,src.

1) Conduction Loss: Conduction loss is caused by the

energy which is dissipated across the resistive components,

mainly as joule heating. The parasitic resistances that con-

tributes the conduction loss are: 1) the turn-on resistance

of power transistors, Ron; 2) the inductor equivalent series

resistance (DCR, RDCR); 3) the capacitor equivalent series

resistance (ESR, RESR); 3) I-R drop via the current control-

ling transistors–current sources Ielec,src and Ielec,elec in Fig. 3;

4) the resistance of bonding wire, denoted as Rbond leading

toward the electrode; and 5) the access resistance of electrodes

formed by both an over-potential at the pad-electrode interface

and the voltage drop in tissue. The conduction losses are

formulated as:

Ploss,cond(t) = Ploss,par(t) + Ploss,d(t)

+ Ploss,CCT (t) + Ploss,Ra(t), (4)

where

Ploss,par(t) = IL2(t) · (Ron +RESR +RDCR +Rbond)

Ploss,d(t) = IL(t) · VF

Ploss,CCT (t) = Nelec · IDAC(t) · (|VSUP (t)− Velec(t)|) .

103 104 105

10

10

10

100

Frequency (Hz)

Gain

(dB)

Gain Response of the Forward Buck Converter

State Space ModelTransfer Function Model

103 104 105

0

Frequency (Hz)

Phas

e (de

g)

Phase Response of the Forward Buck Converter


103 104 10510

10

100

Frequency (Hz)

Gain

(dB)

Gain Reponse of the Reverse Boost Converter


103 104 105

0

Frequency (Hz)

Phas

e (de

g)

Phase Respose the Reverse Boost Converter


(a)

(b)

Fig. 8. Bode plots calculated by state space model and transfer functionanalysis, for (a) forward buck operation, and (b) reverse boost operation.

2) Switching Loss: Switching loss appears at the signal

transient triggered by the switching circuit elements such as

power transistor and diode. The main constituent parts of the

switching loss are: 1) the V-I crossover loss of the power

P/NMOS during turn-off time in DCM mode, and turn-on and

-off time in CCM mode; 2) diode reverse recovery loss; 3) the

charging and discharging of parasitic capacitors of inductor

at the switching node (Vx); and 4) the gate driving loss

for charging and discharging input capacitance of the power

transistors.

Formally putting all the terms comprising the switching loss,

Ploss,sw(t) = Ploss,gate(t) + Ploss,cross(t) + Ploss,rr(t). (5)

The loss induced by driving the gate is given as:

Ploss,gate(t) =1

2· fs · Ciss · VDD

2 · kt, (6)

where kt is the buffer multiplication factor that account for

the loss due to the gate driving buffer changes. The buffer

multiplication factor is given by [38]: kt =km+1−1km·(k−1) , where

m is the number of the cascading inverters in the buffer and

k is the scaling factor.

The V-I crossover loss that occurs during the voltage

transition at the switching node Vx, induced by the switching

of the power transistors, as is depicted in Fig. 3. During the

DCM mode operation, shown in Fig. 3(a),(b), the crossover



loss only appears at the turn-off time of the power transistor,

since IL = 0A at the turn-on instant. In the CCM operation,

as shown in Fig. 3(c),(d), on the contrary, IL does not return

to zero at the turn-on instant, thus the crossover losses occur

at both turn-on and turn-off instant. The V-I overlap during the

switching transition occurs because the magnetic energy stored

in inductor (L1) is used to charge and discharge the parasitic

capacitors associated with the gate terminals of the power

transistors (MP1, MN1). In the turn-off process of the forward

buck operation, for example, the crossover duration starts after

the gate overdrive voltage of MP1 is set to the inductor current

sustaining gate voltage level, Vsg = Vt + IL/gm, where Vt

is the threshold voltage and gm is the transconductance of

MP1. During the time when the gate voltage is stuck at ‘Miller

Plateau’, the displacement current through the reverse transfer

capacitance, Cgd of MP1–Cgd · dVd/dt at the drain terminal

of MP1–gets diverted through the input resistance of MP1.

The crossover loss is formulated as:

Ploss,cross(t) =1

2· fs · |IL| · (VDD + VF ) · tsw (7)

In addition to the V-I crossover loss, we have to add the

loss for charging and discharging of parasitic capacitance at

the switching node (Vx). The parasitic capacitance is given by

Cx = Coss + CL, where Coss is the output capacitance of

the power transistor between drain and source, and CL is the

parasitic capacitance associated with the inductor (L1). The

effect of the parasitic capacitance is not included in the V-I

overlap loss, since it is not connected to the gate, of which

voltage dominate the duration of the V-I overlap period. The

capacitive loss is described as:

Ploss,cx(t) =1

2· fs · Cx · VDD

2 (8)

The last component of the switching loss is the diode reverse

recovery loss, which is illustrated in Fig. 3. During ta, the

reverse diode current discharges the minority carriers inside

the p-n junction and forms the concentration gradient in a

direction that the forward active current of the diode slides

through [39]. The reverse voltage across the diode (D1) in

reverse boost operation is VDD − VSUP , thus the power loss

is

Ploss,rr,rev(t) =1

6· (VDD − VSUP ) · |IRRM | · trrb · fs (9)

where IRRM is the peak reverse current of the diode. The re-

verse voltage across the diode (D2) in forward buck operation

is VDD − VSUP , thus the power loss is

Ploss,rr,fwd(t) =1

6· VSUP · |IRRM | IRRM · trrb · fs, (10)

3) Core Loss: The core loss is a magnetic loss which is

especially significant in DCM operation, in which the pro-

posed system works except the phase boundaries. This loss is

induced by the changing magnetic energy in the core during a

switching cycle; the magnetic energy drawn into the core when

the inductor is getting energized is larger than the magnetic

energy recovered from the core when the inductor is releasing

the stored energy [40]. The difference between the supplied

and returned energy is caused by the nonlinear response of

TABLE IDESIGN PARAMETERS USED FOR SIMULATIONS

Item Value Item Value Item Value

Vg 20V fs 500kHz R∗on 1.6Ω

CP∗iss 1000pF CP∗

oss 500pF CN∗iss 500pF

CN∗oss 250pF IRRM 10mA trrb 10ns

Rbond 200mΩ RESR 50mΩ RDCR 50mΩC∗

2 2.2μF L 7.2μH Ra 3kΩCdl 100nF Nelec 32 NADC 8NDPWM 4 Nno 5 Ncont 5Voffset 1V Vthres1 0.5V Vthres2 0.25VAe 7.2mm2 le 23.1 mm μe 1120Nturn 4 Kfe 16W/m3 α 1.26β 1.46 CL 3.9fF tsw[rf ] 5ns

* indicates the maximum value, when the AICS and the APTS connect thesystem to full load.The superscript ‘P’ indicates parameters of MP1, and the superscript ‘N’indicates the parameters of MN1.Nno indicates No Pulse Cnt Max, Ncont indicates Cont Pulse Cnt Max.

the magnetic field density (B(t)) versus the magnetic field

strength (H(t)). Because H(t) = N · ΔIL(t), where N is

the number of winding turns around the inductor core, and

ΔIL(t) is larger in DCM than CCM, DCM mode is prone to

have a larger core loss. The calculation of the core losses is not

trivial, and a perfect computational algorithm has not yet been

found [41]. In this work, we chose a widely accepted method

referred as the ‘improved generalized Steinmetz equation’

(iGSE), formulated based on the parameters of the Steinmetz

equation [42], [43]. The iGSE is given as

Ploss,core =1

Ts

∫ 2π

0

ki

∣∣∣∣dBdt∣∣∣∣α

(ΔB)β−α

dt, (11)

where ΔB is peak-to-peak flux density, α, β are Steinmetz

parameters, and ki = k(2π)α−1 ∫2π

0 |cos θ|α2β−αdθ. The equa-

tion (11) tells that the average power loss per unit volume,

Ploss,core, depends on the time history of the domain wall

motion (dB/dt) and the peak-to-peak flux density (ΔB).

4) Figure of Merit: The conduction loss across Ra is a

distinctive source of the loss, in that it is not a loss pertaining

to an innate feature of the stimulator circuits itself. Thus, we

defined the figure of merit (FOM) excluding Ra-associated

conduction loss as measuring sticks for stimulator system:

ηwaste = 1− Ewaste,PSM

Ewaste,CS

= 1−∫ Ts

t=0Ploss,SMPS(t)dt+

∫ Ts

t=0Ploss,CCT (t)dt∫ Ts/2

t=0Ploss,CS,cat(t)dt+

∫ Ts

t=Ts/2Ploss,CS,an(t)dt

,

(12)

where

Ploss,CS,an(t) = Nelec · IDAC(t) · (|VDD(t)− Velec(t)|)Ploss,CS,cat(t) = Nelec · IDAC(t) · (|Velec(t)|) .

B. System Modelling

Building simulator to observe the system behaviour and

power efficiencies over various system parameters involves



with the development of the system models describing the

SMPS. The SMPS can be expressed in terms of the state space

models and transfer functions.

1) Transfer Function: A closed loop system can be written

as Gclosed(s) =Gfwd(s)

1+Gfwd(s)·Gfb(s), where Gfwd(s) is the

forward gain transfer functions (TF), Gfb(s) is the feedback

network TF. In the system under analysis, the forward gain TF

is composed of the three cascaded TF, Gctl(s) · Gdpwm(s) ·Gvd(s), where Gctl(s) is the TF of the D-PS-PWM-QPID

controller, which is described in Section II-D, Gdpwm(s) is

the continuous time model of the DPWM, which is given

as Gdpwm(s) =(

1

2Ndpwm−1

)· e−sTdpwm , where Npwm is

the DPWM resolution and Tdpwm is the delay caused by

the DPWM circuit. Gvd(s) the continuous time model of

SMPS of which the input is Verr(t) and the output d(t).The feedback part consists of H(s) and the Gadc(s). H(s)represents the output voltage sensor gain which is given as

H(s) =Vref (s)Vo(s)

, and Gadc(s) is the continuous time model of

the ADC which is given as Gadc(s) =(

2Nadc−1Vmax,adc

)· e−sTadc ,

where Vmax,adc is the maximum voltage of ADC input, Nadc

is the ADC resolution, and TADC is the conversion delay. The

TF of the D-PS-PWM-QPID controller can be calculated from

the input-output relationship, Gctl(s) = L (d(t)) /L (Verr(t)),where L(·) denotes the laplace transform of a continuous time

function. The duty function d(t) is given as a function of f+(t)and f−(t), where f+(t) indicates the increment of the duty by

1, and f−(t) is the decrement of the duty by 1.

d

dtd(t) =

f+(t)− f−(t)Ts

(13)

We can express f+(t) and f−(t) based on the flowchart

depicted in Fig. 5 as below:

f+(t) = H

(H

(Ncont−1∑

i=0

Verr (t− iTs)−Ncont

)

+H (Verr(t)− Vthres1)

+H (Verr(t)− Verr(t− Ts)− Vthres2)) (14)

f−(t) = H

(Nno−1∑i=0

Verr (t− iTs)−Nno

), (15)

where H(·) is the Heavyside step function, Ncont and Nno

are the Cont Pulse Cnt Max and the No Pulse Cnt Maxparameters of the D-PS-PWM-QPID controller, respectively.

The continuous time model of the reverse boost and the

forward buck converters can be described as an one pole TF:

Gvd,[rev,fwd](s) =Gd0,[rev,fwd]

1 + sωp,[rev,fwd]/2π

(16)

The charge delivered from the energy source Vg into C2

in the forward boost case, and the charge delivered from C2

into the energy source Vg are formulated as Qdelivered =0.5 · ((D1 +D2) · Ts) · Ipk, where D1 is the duty ratio of

energizing period, D2 is the duty ratio of the period when

the energy stored in the inductor is released, and Ipk is

the peak current flowing through the inductor. Peak inductor

current in the reverse boost and the forward buck operation

are formulated as Ipk,rev = D1 · Ts · Vsup/L, and Ipk,fwd =D1 · Ts · (Vg − Vsup) /L, respectively. We can relate D2 with

D1 as D2,rev = (Vsup/ (Vg − Vsup))D1,rev for the reverse

boost operation, and D2,fwd = ((Vg − Vsup) /Vsup)D1,fwd,

for the forward buck operation. From the average output

current flowing into C2, the effective resistances across the

power source network are expressed as:

Reff,rev(D1) =106 · L · Vg

2

D1 · Vsup2 ·

(D1 +

D1·Vsup

Vg−Vsup

) (17)

Reff,fwd(D1) =106 · L · Vg

D12 (Vg − Vsup)

, (18)

where Reff,rev(D1) and Reff,fwd(D1) are the effective re-

sistances in the reverse boost operation, and the forward buck

operation, respectively. Now, we can use the small signal

linearization technique for deriving the duty to voltage transfer

function (Gvd,[rev,fwd](s)).

The resulting gain and the pole frequency in the reverse

boost operation can be written as:

Gd0,rev =−2 ·Drev ·MrevR · VSUP

106 · L(1−Mrev)−Drev2 ·Mrev ·R

(19)

ωp,rev =L(1−Mrev)− 10−6Drev

2 ·Mrev ·RR · L · C(1−Mrev)

, (20)

where the duty (Drev) and the conversion ratio (Mrev) are

given as:

Drev =1.414

√−Ielec · L+ Ielec · L ·M√Ts · Vg

(21)

Mrev = 1 +0.5 ·Drev

2Ts · Vg

Ielec · L (22)

Similarly, the gain and the pole frequency in the forward

buck operation can be written as:

Gd0,fwd =Dfwd (−2 + 2Mbuck)R · VSUP

−106 · L ·Mfwd2 +Dfwd

2 ·R (−1 + 1Mfwd)(23)

ωp,fwd =L ·Mfwd

2 +Dfwd2 ·R (

10−6 − 10−6Mfwd

)R · L · C ·Mfwd

2 ,

(24)

where the duty (Dfwd) and the conversion ratio (Mfwd) are

given as:

Dfwd =1.414

√Ielec · L ·M√

Ts · Vg −Mbuck · Ts · Vg

(25)

Mfwd =Dfwd

2 · Ts · Vg

2 · IelecL+Dfwd2TsV g

(26)

2) State Space Model : We can express the proposed system

with a set of linear, finite state, dynamic equations. We have

three state variables of interest: inductor current (IL), the

voltage on C2 (VC), and the voltage on the electrode interface



(Velec). The equations that express the dynamic evolutions of

VC , Velec, and VSUP are as follows:

dVC,rev

dt=

(1

αRDCRC2

)VC +

(1

αC2

)IL (27)

+

(1

αC2

)Ielec,sink

dVC,fwd

dt=

(1

αRDCRC2

)VC (28)

+

(1

αC2

)IL +

(− 1

αC2

)Ielec,src

dVelec,rev

dt= −Ielec,sink

Cdl(29)

dVelec,fwd

dt=

Ielec,srcCdl

(30)

VSUP,rev =

(1

α

)VC +

(RESR

α

)IL +

(RESR

α

)Ielec,sink

(31)

VSUP,fwd =

(1

α

)VC +

(RESR

α

)IL −

(RESR

α

)Ielec,src

(32)

where the subscript ‘rev’ marks for the variables in the reverse

boost operation and the subscript ‘fwd’ marks for the variables

in the forward buck operation, and α = 1 + RESR

RDCR.

And the equations that express the dynamic evolutions of

IL in the period marked as T1 in Fig. 3 are as follows:

dIL,rev

dt=

(− 1

αL

)VC +

(−RESR

αL

)Ielec,sink

+

(−RESR − α (Ron,MP1 +RDCR)

αL

)IL (33)

dIL,fwd

dt=

(− 1

αL

)VC +

(RESR

αL

)Ielec,src +

(1

L

)VDD

+

(−RESR − α (Ron,MN1 +RDCR)

αL

)IL (34)

The equations for IL in the period marked as T2 are as follows:

dIL,rev

dt=

(− 1

αL

)VC +

(−RESR − αRDCR

αL

)IL

+

(−RESR

αL

)Ielec,sink +

(1

L

)VDD − VF

L(35)

dIL,fwd

dt=

(− 1

αL

)VC +

(−RESR − αRDCR

αL

)IL

+

(RESR

αL

)Ielec,src − VF

L(36)

The equation for IL in the period marked as T3 isdIL,[rev,fwd]

dt = 0.

3) Limit Cycle Oscillation: Digital controllers can incur the

limit cycle oscillation problem, if the resolution of DPWM is

not high enough to provide stead-state output that they are

controlled by a traditional linear controller [44]. However,

in the D-PS-PWM-QPID controller, the resolution of DPWM

resolution no longer restricts the resolution of the quantized

output voltage at which a power system is allowed to settle on;

the controller modulates the amount of the energy to transfer

into the load, delivering the energy necessary for the reference

tracking. In effect, the pulse skipping logic dithers the average

amount of the transferred energy to the load throughout the

long time frame, by preventing VSUP to periodically fluctuate.

C. Discussion

Now, we are ready to answer to the question of how many

scaling levels we need to achieve a reasonable amount of

power saving over a wide operating range, while paying the

smallest possible implementation cost for additional control

and switching circuitry. To answer the question, we performed

simulations calculating the energy saving percentage, sweep-

ing Nelec from 0 to 64, for IDAC = 100, 300, 600μA, of

which results are shown in Fig. 4. The energy saving percent-

age is an indicator of performance, that evinces how much

wasted energy is reduced in the proposed system compared to

the current source stimulator, given that both have the same

power source. In mathematical term, the energy saving per-

centage is found as ηwaste = 1−Ewaste,PM

Ewaste,CS, where Ewaste,PM

is the wasted energy in the proposed stimulator, and Ewaste,CS

is the wasted energy in the conventional current-source-based

stimulator without power supply modulation. The energy

saving percentage approaches to 50% in all three cases of

IDAC = 100, 300, 600μA, as the number of the electrode

approaches to 64. As is predicted from the theory, as the

loading gets lighter ηwaste gets smaller, and even reaches

to −100%, which means that twice more energy is burnt

in the proposed one, compared to the current-source-based

stimulator. This is because the DC-DC converter overhead

dominates the energy waste when driving a light load; thus

APTS and AICS play more significant roles when the load

is light. From the results shown in Fig. 4, we judged that

Nlv,max = 16 could be chosen as a possible spot that

can have reasonably high ηwaste values throughout all the

loading conditions, with a tractable number of the control lines

connected to MP1, MN1, and C2.

To confirm that the system dynamics described by the state

space model and the transfer functions coincide each other,

we will analyze the system under a typical operating point

driving the load of Nelec = 32 and IDAC = 600μA. In this

case, the TF of the D-PS-PWM-QPID controller Gctl(s) is

calculated to be a constant (≈ 9.2), with the duty function

that is updated at the beginning of the switching cycle. Here,

we need to take care of the input sinusoidal injection function

(Verr(t) = sin(ωt)), of which the frequency is less the

switching frequency (fs).

The system parameters involved to calculate the TF (Gvd)

from the duty ratio to VSUP are VSUP = 10V , C2 = 1.1μF ,

Mrev = 2, Drev = 0.083, Gd0,rev = 92.17, ωp,rev = 278,

Mfwd = 0.5, Dfwd = 0.083, Gd0,fwd = 92.17, and

ωp,fwd = 278. The DPWM block typically has a negligible

delay compared to the switching frequency, which leads to

NDPWM = 4.58, TDPWM = 0, thus GDPWM = 1/24.

As for the ADC block which lies on the feedback path, the

conversion time can be assumed to be negligible compared

to a switching period, which leads to the assumptions that

Tadc = 0 and Hs = 1. Finally, we have all the TF components,



42

00

200

0400

5

10

15

20

42

00

200

0400

5

10

15

20

6040

2000

200400

0600

5

10

15

20

6040

2000

200400

0600

5

10

15

20

Ncon

v-re

v

Ncon

v-fw

d

Ncon

v-re

v

Ncon

v-fw

d

Pout (mW)

IDAC ( A)

Pout (mW)

NelecIDAC ( A) Nelec

Ra (k )Ra (k )

(a) (b)

(c) (d)

Fig. 9. Convergence speed of the bidirectional SMPS for microstimulatorwhen driving a biphasic pulse. (Upper row) Number of switching cycles(Nconv) taken for Vsup to reach the switching manifold over various loadresistances (Ra) and output power (Pout) (a) in the reverse boost mode, and(b) in the forward buck mode. (Lower row) Nconv taken for Vsup to reachthe switching manifold over various stimulation current amplitudes (IDAC )and number of electrodes (Nelec) (c) in the reverse boost mode, and (d) inthe forward buck mode.

which are necessary for depicting the TF of the closed-loop

reference input tracking system of interest, thus we are ready

to analyze the frequency response of the closed loop reference

input tracking using the equation below:

Gclosed(s) =Gctl(s) ·Gdpwm(s) ·Gvd(s)

1 +Gctl(s) ·Gdpwm(s) ·Gvd(s) ·Gadc(s) ·H(s)(37)

The resulting bode plot is shown in Fig. 8, from which we

can compare the spectral performances calculated from the

state space model simulations and from the transfer function

analysis.

IV. EXPERIMENTAL RESULTS

In this section, we assess the stability and performance

of the PSM stimulator system using the simulator described

in the previous section. Then, the proposed topology with

the D-PS-PWM-QPID controller is shown to be feasible for

realization on a verification platform, which consists of off-

the-shelf components and a FPGA board communicating with

PC using an USB interface.

A. Numerical Assessment

We first undertook extensive validation of the PSM stimula-

tor system over a wide range of loading configurations using

a simulation code based on the state-space model with power

losses being accounted. Here, we evaluate whether or not

the D-PS-QPID-PWM controller can stably drive the power

supply by quickly converging into the switching manifold at

the phase transition boundaries.

TABLE IICONVERGING SPEED AT THE DISCONTINUOUS BOUNDARY OF THE PHASE

TRANSITIONS

Ref. [10]ˆ [45] [46] [47]ThisWork

Topology

Bidirect-ionalBuck-Boost

Buck-Boost

Buck-Boost

Buck

Bidirect-ionalBuck-Boost

Control SchemeCurrentMode

Hyst-eresis

CurrentMode

VoltageMode

DigitalVoltageMode

SwitchingFrequency (MHz)

0.25 10 5 10 0.5

Up-tracking time(μs/V )

208 93 20 1.7 5

Down-trackingtime (μs/V )

208 27 15 4.4 6.4

Up-trackingNconv*

292 5208 560 93 14

Down-trackingNconv*

292 1512 420 248 18

* The values are normalized for a voltage transition of 5.6V , which wasderived in the time-domain scenario shown in Fig. 2.ˆ Estimated from the corresponding literature.

To measure converging performance of the SMPS, the

number of switching cycles for the stimulator to settle on

the switching manifold from initial phase changing event

(Nconv) was used. Nconv is extracted from the time-domain

simulation waveform at the beginning of the cathodic pulse,

and at the cathodic-to-anodic inter-phasic boundary. Fig. 9

reveals that Nconv is bounded less than 18 switching cycles

(∼ 36μs or 3.6% of a pulse duration) for wide range of the

loading configurations spanning over IDAC = 0 ∼ 600μA,

Pout = 0 ∼ 400mW , and Nelec = 0 ∼ 64. Table II

compares the converging speed of the D-PS-PWM-QPID

controlled bidirectional converter with some state-of-the-art

converters designed for DVS power supply. In absolute time

scale, converters in some works [17], [47] exhibit steady-

state operating points faster than this work. However, after

normalizing the converging speed in terms of the number of

switching cycles required to settle at initial target operating

point (Nconv), the proposed SMPS consumes significantly

less cycles than others, including a bidirectional converter

employed for a PSM stimulator [10]. The price of the eco-

nomic convergence property includes chattering and peaking at

the phase transition boundaries shown in Fig. 12, considering

that they are acceptable shortcomings in the PSM stimulator

applications.

Next, we also confirmed that the SMPS with the D-PS-

PWM-QPID controller is stable for over the wide range of the

loading configurations of concern. The phase plot, displayed

in Fig. 10, validates that the system error function (Verr) and

its derivative vanish toward the origin; thus the stability of the

system can be ensured over a wide range of the loading.

B. Verification Platform

Fig. 11 shows the block diagram of the system. A PC

running Mathworks MATLAB, through the USB interface



-2 0 2 4-1

-0.5

0

0.5

1

-2 0 2 4-1

-0.5

0

0.5

1

-2 0 2 4-1

-0.5

0

0.5

1

-2 0 2 4-1

-0.5

0

0.5

1

Verr(t) (V)

dVer

r(t)/d

t (V/

s)

Verr(t) (V)

dVer

r(t)/d

t (V/

s)

Verr(t) (V)

dVer

r(t)/d

t (V/

s)

Verr(t) (V)

dVer

r(t)/d

t (V/

s)

(a) (b)

(c) (d)

Fig. 10. Phase portrait plot of the bidirectional SMPS for microstimulatorwhen driving cathodic-first biphasic pulses of (a) IDAC = 100μA to anelectrode during the reverse boost phase, and (b) during the forward buckphase, and when driving (c) IDAC = 600μA to 64 electrodes during thereverse boost phase, and during the forward buck phase.

provided by Opal Kelly Xem3001, sets a 4 bits current DAC

data word in the current DAC I/F block for it to feed a I2C

command waveform to the current DAC (Maxim DS4412).

The PC also fetches a start flag in the pulse generator, which

forges a stimulating current pathway by maneuvering the

switches (TI CD4066B) connecting the current source and sink

(the 10x terminals of the current mirrors) with a electrode array

model output (Velec). The the pulse generator also controls

the switches connecting the emitters of the 1:10 PNP current

mirror and the collectors of the 1:10 NPN current mirror, to

the output of the LC filter (VSUP ). In the cathodic stimulation

phase, ACT CAT signal turns on the switches connecting

Velec to the current sink (the 10x terminal of the NPN current

mirror), steering current from the Velec node to the IESC of

the LC filter. In an anodic stimulation phase, ACT AN signal

turns on the switches connecting Velec to the current source

(the 10x terminal of the PNP current mirror) steering current

from the IESC of the LC filter to the model electrode. The

amount of the current flowing between the IESC and electrode

array model is defined by the current scaled and copied from

the current DAC through the current mirrors (Infineon BCV61

for NPN, BCV62 for PNP). The D-PS-PWM-QPID controller

is programmed in the FPGA, according to the flowchart of

Fig. 5; it retrieves the ADC output values of Velec and VSUP ,

and determines a 4-bit duty level and the Pulse Enable signal

which indicates whether to apply a set of pulses or not for

the upcoming switching cycle. for DPWM block. The DPWM

block drives the gates of the power switches. The DPWM

block modulates the duration of the gate driving pulses for

MP1 and MN1 that close the conduction path between VDD(or VSS) and the inductor (L1) of the LC filter. The body

DPWM PowerSwitches

LCFilter

PC / MATLAB

8-Bit2-Channel

ADC

PulseGenerator

ElectrodeArray Model

Current DACI2C I/F

FIFO DAQI/F

D-PS-PWM-QPID

Controller

3.3 VVSUP

Velec

VSUP

VSUP

PNP

5

88

CurrentDAC

1 : 1Current Mirror

1 : 1Current Mirror

Current Mirror

1 : 1

1 : 10Current Mirror

Current Mirror

1 : 10

FPGA

GND

GND

3.3 V

3.3 V

10 V10 V

GND

NPN

Fig. 11. The verification platform for the proposed power supply modulatedstimulator topology.

diodes of the power switches are used as a pair of anti-parallel

diodes of Fig. 1, when both power switches are open, and the

inductor has the energy to be released on to the IESC. At the

end of a pair of stimuli, the FIFO DAQ I/F report the voltage

waveforms during the stimulation to the PC, and the D-PS-

PWM-QPID controller report the dynamics of Pulse Enablesignal and duty level signal during the preceding pair of

stimuli to the PC. Note that the signals generated from FPGA–

the outputs of the DPWM, ACT AN, and ACT CAT–were

translated from the 3.3V low voltage domain, to the 10V high

voltage domain, through the MC14504B level shifter.

C. Measurement Results

We performed measurements with a loading configurations

made up of Nelec = 16 and IDAC = 300μA. There are 3 com-

ponents values that are dependent on the switching frequency:

the inductor (L1), the IESC, and the capacitance of the model

electrode. All of those frequency domain values proportionally

scaled up as the switching frequency is scaled down to a level

that can be easily operated on the verification platform. Fig. 12

shows the voltage waveforms of the verification platform,

captured by an oscilloscope at the LC-filter output node and

the electrode node. Fig. 12(a) shows a voltage waveform where

Voffset = 1V , IDAC = 300μA, and Nelec = 16. In this case,

the power supply voltage (yellow line) is the smoothest out

of the 4 cases (Fig. 12(a-d)) where Voffset = 1V ; because

the load current (16 × 300μA = 4.8mA) is high enough to

make the short pulse skipping periods to be short. At the inter-

phase boundary, we can notice that the D-PS-PWM-QPID

promptly charges the IESC to a new reference voltage level

in the subsequent phase, by driving up the duty level more

abruptly than in the normal tracking state. Fig. 12(d) shows

a voltage waveform, where Voffset = 1V , IDAC = 100μA,

and Nelec = 2. This means the load current of the stimulator

is light at 2×100μA = 0.2mA, which leads to more frequent

pulse skipping. Long pulse skipping periods in the reverse

boost operation make VSUP look like a sawtooth waveform;

VSUP drops abruptly only when a pulse is applied, and then

slowly approach to the reference voltage to track, as the



(a) (b)

(c) (d)

(e) (f)

VSUP

VelecVSUP

Velec

VSUP

Velec

VSUP

Velec

VSUP

Velec

VSUP

Velec

2 V 2 V

2 V2 V

2 V 2 V

Fig. 12. Voltage waveforms of the power supply modulated stimulator duringa set of cathodic-first stimulus, when (a) Voffset = 1V , IDAC = 300μA,and Nelec = 16; (b) Voffset = 1V , IDAC = 100μA, and Nelec = 16;(c) Voffset = 1V , IDAC = 300μA, and Nelec = 2; (d) Voffset = 1V ,IDAC = 300μA, and Nelec = 2; (e) Voffset = 2V , IDAC = 300μA,and Nelec = 16; (f) Voffset = 2V , IDAC = 200μA, and Nelec = 16.In all the waveforms, the channel 1 (yellow color) is connected to Vsup, andthe ‘channel 2 (green color) is connected to Velec.

charges to be recovered to the power source are accumulated

on the IESC transferred from the electrode model. In the

anodic phase, however, the sawtooth waveform is not evident

compared to the cathodic phase, because VSUP moves closer

to VDD (10V ); as VSUP approaches closer to VDD, the energy

delivered per pulse gets smaller, given that the duty levels are

the same.

D. Observation

The dynamics of the internal state variables of the blocks

programmed on the FPGA can be stored and transferred to

the PC, so that we can observe how the blocks under test

behave, according to the block attributes. Fig. 13 shows the

timing diagrams of the important internal signals of the D-PS-

PWM-QPID controller, when Voffset = 1V , IDAC = 300μA,

and Nelec = 16. Fig. 13(a) shows the input signals of the

D-PS-PWM-QPID, which are the 8-bit ADC codes of the

voltages at the model electrode and the modulated power

Fig. 13. Measured duty level dynamics pertaining to variousCont Pulse Cnt Max and No Pulse Cnt Max values, whenVoffset = 1V , IDAC = 300μA, and Nelec = 16. (a) Velec andVsup voltage waveforms during a set of biphasic stimulus. (b) Pulseenable signal. (c) Duty level when Cnt (= Cont Pulse Cnt Max =No Pulse Cnt Max ) = 5. (d) Duty level when Cnt = 1. (e) Duty levelwhen Cnt = 10.

supply. Fig. 13(b) shows the Pulse Enable signal which

indicates whether an energy packet is processed during the

time slot, or not. The Cont Pulse Cnt Max attribute de-

termines the maximum number of consecutive pulses, while

the No Pulse Cnt Max attribute determines the maximum

number of cycles that are skipped without a pulse. These

two attributes, together, set boundaries where duty level is

adjusted for adapting the load power. We performed exper-

iments under the conditions that Cont Pulse Cnt Max =

No Pulse Cnt Max = Cnt = 5, for the timing diagrams

shown in Fig. 13(a-c); Cnt = 10, for the result shown in

Fig. 13(d); and Cnt = 1, for the result shown in Fig. 13(e).

The number of consecutive pulses, Cont Pulse Cnt, which

is indicated by the duration that the Pulse Enable signal is

raised, is the number of switching cycles taken for VSUP to

cross over the target reference voltage to track. The number of

switching cycles without a pulse, No Pulse Cnt, is an indica-

tor that VSUP needs to be adjusted to track the target reference

voltage. If Cnt is set to be too small, as shown in Fig. 13(e),

the duty level responds too sensitively to the transient SMPS



output voltage, resulting in oscillatory behavior. On the other

hand, if Cnt is set to be too large, as shown in Fig. 13(e),

the duty level is too inertly adjusted, resulting in long time

periods of the consecutive pulses or idle state.

V. CONCLUSION

The PSM stimulator with the-D-PS-PWM-QPID controller

can accommodate a broad dynamic range of the output loading

conditions, while supporting fast transient tracking capabil-

ity with robustness notwithstanding the power stage transfer

function. Spots of energy losses are identified in the light of

energy flow of the stimulator, traversing from the source power

reservoir, via SMPS converter and current drivers connected to

electrodes, and back to the source power reservoir. Analysis on

the scaling PT and IESC for preventing the power consumption

overhead for the power supply modulation from increasing

beyond the amount of power saving from the power supply

modulation is given. A set of state-space model is derived

for behavior simulation of the stimulator design. And transfer

functions describing the frequency response of the design are

derived for understanding reference tracking capability of the

design in spectral domain. The converging speed and stability

of the system were assessed using the simulations which

implements the state-space model incorporating the energy

losses. Finally, a proof-of-concept experimental platform was

presented. From the platform, we could carve out a possible

embodiment that the power supply modulated stimulator could

be realized. We also observed internal state dynamics of

the D-PS-PWM-QPID controller with varying values of the

attributes.

ACKNOWLEDGMENT

This work was supported in part by an RGC research

Grant from Hong Kong University of Science and Technology,

Grant Reference: 610412, and the Research Committee of the

University of Macau (MYRG115-FST12-LMK).

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