tl5001

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TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS

SLVS084F APRIL 1994 REVISED JANUARY 2002

1POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Complete PWM Power Control

3.6-V to 40-V Operation

Internal Undervoltage-Lockout Circuit

Internal Short-Circuit Protection

Oscillator Frequency . . . 20 kHz to 500 kHz

Variable Dead Time Provides Control OverTotal Range

3% Tolerance on Reference Voltage(TL5001A)

Available in Q-Temp AutomotiveHighRel Automotive ApplicationsConfiguration Control / Print SupportQualification to Automotive Standards

description

The TL5001 and TL5001A incorporate on a single

monolithic chip all the functions required for apulse-width-modulation (PWM) control circuit. De-signed primarily for power-supply control, the

TL5001/A contains an error amplifier, a regulator, anoscillator, a PWM comparator with a dead-time-con-trol input, undervoltage lockout(UVLO), short-circuit protection (SCP), and an open-collector output transistor. The TL5001A has a typicalreference voltage tolerance of 3% compared to 5% for the TL5001.

The error-amplifier common-mode voltage ranges from 0 V to 1.5 V. The noninverting input of the error amplifieris connected to a 1-V reference. Dead-time control (DTC) can be set to provide 0% to 100% dead time by connectingan external resistor between DTC and GND. The oscillator frequency is set by terminating RT with an externalresistor to GND. During low VCCconditions, the UVLO circuit turns the output off until VCCrecovers to its normaloperating range.

The TL5001C and TL5001AC are characterized for operation from 20C to 85C. The TL5001I and TL5001AI arecharacterized for operation from 40C to 85C. The TL5001Q and TL5001AQ are characterized for operation from

40C to 125C. The TL5001M and TL5001AM are characterized for operation from 55C to 125C.AVAILABLE OPTIONS

PACKAGED DEVICES

TA SMALL OUTLINE

(D)

PLASTIC DIP

(P)

CERAMIC DIP

(JG)

CHIP CARRIER

(FK)

TL5001CD TL5001CP

TL5001ACD TL5001ACP

TL5001ID TL5001IP

TL5001AID TL5001AIP

TL5001QD TL5001AQD

TL5001MJG TL5001MFK

TL5001AMJG TL5001AMFK

The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL5001CDR).

Copyright 2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

8

7

6

5

OUT

VCCCOMP

FB

GND

RT

DTC

SCP

D, JG OR P PACKAGE

(TOP VIEW)

192013 2

17

18

16

15

14

1312119 10

5

4

6

7

8

NC

RT

NC

DTC

NC

NC

VCC

NC

COMP

NC

NC

OUT

NC

GND

NC

FB

NC

SCP

NC

NC

FK PACKAGE

(TOP VIEW)

On products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.

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SLVS084FAPRIL 1994REVISED JANUARY 2002

2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

schematic for typical application

TL5001/A

FB

COMP

VO

DTC

RT

VI

+

SCP

VCC

+

TPS1101

GND

8

7

6

5

2

1

3

4

VO

functional block diagram

GND8

OUT

SCP

COMP

FB

5

3

4

+

DTCRT

67

Comparator 2SCP

PWM/DTCComparator

OSC

Comparator 1SCP

AmplifierError

UVLO

VCC2 1

1 V

1.5 V 1 VReference

Voltage

IDT

2.5 V

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detailed description

voltage reference

A 2.5-V regulator operating from VCCis used to power the internal circuitry of the TL5001 and TL5001A and as a

reference for the error amplifier and SCP circuits. A resistive divider provides a 1-V reference for the error amplifiernoninverting input which typically is within 2% of nominal over the operating temperature range.

error amplifier

The error amplifier compares a sample of the dc-to-dc converter output voltage to the 1-V reference and generatesan error signal for the PWM comparator. The dc-to-dc converter output voltage is set by selecting the error-amplifiergain (see Figure 1), using the following expression:

VO= (1 + R1/R2) (1 V)

To PWM

Comparator

Vref= 1 V

4VI(FB)

3

+

R2

R1

COMP

FB

Compensation

Network

TL5001/A

GND8

Figure 1. Error-Amplifier Gain Setting

The error-amplifier output is brought out as COMP for use in compensating the dc-to-dc converter control loop for

stability. Because the amplifier can only source 45 A, the total dc load resistance should be 100 kor more.

oscillator/PWM

The oscillator frequency (fosc) can be set between 20 kHz and 500 kHz by connecting a resistor between RT and

GND. Acceptable resistor values range from 15 kto 250 k. The oscillator frequency can be determined by usingthe graph shown in Figure 5.

The oscillator output is a triangular wave with a minimum value of approximately 0.7 V and a maximum value ofapproximately 1.3 V. The PWM comparator compares the error-amplifier output voltage and the DTC input voltageto the triangular wave and turns the output transistor off whenever the triangular wave is greater than the lesser ofthe two inputs.

dead-time control (DTC)

DTC provides a means of limiting the output-switch duty cycle to a value less than 100%, which is critical for boostand flyback converters. A current source generates a reference current (IDT) at DTC that is nominally equal to thecurrent at the oscillator timing terminal, RT. Connecting a resistor between DTC and GND generates a dead-time

reference voltage (VDT), which the PWM/DTC comparator compares to the oscillator triangle wave as described

in the previous section. Nominally, the maximum duty cycle is 0% when VDTis 0.7 V or less and 100% when VDTis 1.3 V or greater. Because the triangle wave amplitude is a function of frequency and the source impedance ofRT is relatively high (1250 ), choosing RDTfor a specific maximum duty cycle, D, is accomplished using thefollowing equation and the voltage limits for the frequency in question as found in Figure 11 (Voscmax and Voscminare the maximum and minimum oscillator levels):

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dead-time control (DTC) (continued)

RDT

Rt 1250

D Voscmax Voscmin

Voscmin

Where

RDTand Rtare in ohms, D in decimal

Soft start can be implemented by paralleling the DTC resistor with a capacitor (CDT) as shown in Figure 2. Duringsoft start, the voltage at DTC is derived by the following equation:

VDT

IDT

RDT

1et R

DTC

DT

TL5001/ADTC

CDT RDT

6

Figure 2. Soft-Start Circuit

If the dc-to-dc converter must be in regulation within a specified period of time, the time constant, RDTCDT, shouldbe t0/3 to t0/5. The TL5001/A remains off until VDT0.7 V, the minimum ramp value. CDTis discharged every timeUVLO or SCP becomes active.

undervoltage-lockout (UVLO) protection

The undervoltage-lockout circuit turns the output transistor off and resets the SCP latch whenever the supply voltage

drops too low (approximately 3 V at 25C) for proper operation. A hysteresis voltage of 200 mV eliminates falsetriggering on noise and chattering.

short-circuit protection (SCP)

The TL5001/A includes short-circuit protection (see Figure 3), which turns the power switch off to prevent damagewhen the converter output is shorted. When activated, the SCP prevents the switch from being turned on until theinternal latching circuit is reset. The circuit is reset by reducing the input voltage until UVLO becomes active or untilthe SCP terminal is pulled to ground externally.

When a short circuit occurs, the error-amplifier output at COMP rises to increase the power-switch duty cycle in an

attempt to maintain the output voltage. SCP comparator 1 starts an RC timing circuit when COMP exceeds 1.5 V.If the short is removed and the error-amplifier output drops below 1.5 V before time out, normal converter operationcontinues. If the fault is still present at the end of the time-out period, the timer sets the latching circuit and turnsoff the TL5001/A output transistor.

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short-circuit protection (SCP) (continued)

Q1

12 k

185 kRSCP

Q2

SCP

Comparator 2

Vref= 1 VSCP

Comparator 11.5 V

From Error

Amp

CSCP

To Output

Drive Logic

SCP

5

2.5 V

Figure 3. SCP Circuit

The timer operates by charging an external capacitor (CSCP), connected between the SCP terminal and ground,towards 2.5 V through a 185-kresistor (RSCP). The circuit begins charging from an initial voltage of approximately185 mV and times out when the capacitor voltage reaches 1 V. The output of SCP comparator 2 then goes high,turns on Q2, and latches the timer circuit. The expression for setting the SCP time period is derived from the following

equation:

VSCP

(2.5 0.185) 1 et 0.185

Where

= RSCPCSCP

The end of the time-out period, tSCP, occurs when VSCP= 1 V. Solving for CSCPyields:

CSCP 12.46 tSCP

Where

t is in seconds, C in F.

tSCPmust be much longer (generally 10 to 15 times) than the converter start-up period or the converter will not start.

output transistor

The output of the TL5001/A is an open-collector transistor with a maximum collector current rating of 21 mA anda voltage rating of 51 V. The output is turned on under the following conditions: the oscillator triangle wave is lowerthan both the DTC voltage and the error-amplifier output voltage, the UVLO circuit is inactive, and the short-circuitprotection circuit is inactive.

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC(see Note 1) 41 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Amplifier input voltage, VI(FB) 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage, VO, OUT 51 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Output current, IO, OUT 21 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output peak current, IO(peak), OUT 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Operating ambient temperature range, TA: TL5001C, TL5001AC 20C to 85C. . . . . . . . . . . . . . . . . . . . . .

TL5001I, TL5001AI 40C to 85C. . . . . . . . . . . . . . . . . . . . . . . .TL5001Q, TL5001AQ 40C to 125C. . . . . . . . . . . . . . . . . . . . .TL5001M, TL5001AM 55C to 125C. . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg 65C to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to network ground terminal.

DISSIPATION RATING TABLE

PACKAGETA25C

POWER RATING

DERATING FACTOR

ABOVE TA= 25C

TA= 70C

POWER RATING

TA= 85C

POWER RATING

TA= 125C

POWER RATING

D 725 mW 5.8 mW/ C 464 mW 377 mW 145 mW

FK 1375 mW 11.0 mW/ C 880 mW 715 mW 275 mW

JG 1050 mW 8.4 mW/ C 672 mW 546 mW 210 mW

P 1000 mW 8.0 mW/ C 640 mW 520 mW 200 mW

recommended operating conditions

MIN MAX UNIT

Supply voltage, VCC 3.6 40 V

Amplifier input voltage, VI(FB) 0 1.5 V

Output voltage, VO, OUT 50 V

Output current, IO, OUT 20 mA

COMP source current 45 A

COMP dc load resistance 100 k

Oscillator timing resistor, Rt 15 250 k

Oscillator frequency, fosc 20 500 kHz

TL5001C, TL5001AC 20 85

p pTL5001I, TL5001AI 40 85

, ATL5001Q, TL5001AQ 40 125

TL5001M, TL5001AM 55 125

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electrical characteristics over recommended operating free-air temperature range, VCC= 6 V,fosc= 100 kHz (unless otherwise noted)

reference

TL5001C, TL5001I TL5001AC, TL5001AI

MIN TYP MAX MIN TYP MAX

Output voltage COMP connected to FB 0.95 1 1.05 0.97 1 1.03 V

Input regulation VCC= 3.6 V to 40 V 2 12.5 2 12.5 mV

TA=20C to 25C (C suffix) 10 1 10 10 1 10

Output voltage change with temperature TA=40C to 25C (I suffix) 10 1 10 10 1 10 mV/V

TA= 25C to 85C 10 2 10 10 2 10

All typical values are at TA= 25C.

undervoltage lockout



Upper threshold voltage TA= 25C 3 3 V

Lower threshold voltage TA= 25C 2.8 2.8 V

Hysteresis TA= 25C 100 200 100 200 mV

Reset threshold voltage TA= 25C 2.1 2.55 2.1 2.55 V


short-circuit protection



SCP threshold voltage TA= 25C 0.95 1.00 1.05 0.97 1.00 1.03 V

SCP voltage, latched No pullup 140 185 230 140 185 230 mV

SCP voltage, UVLO standby No pullup 60 120 60 120 mV

Input source current TA= 25C 10 15 20 10 15 20 A

SCP comparator 1 threshold voltage 1.5 1.5 V


oscillator



Frequency Rt= 100 k 100 100 kHz

Standard deviation of frequency 15 15 kHz

Frequency change with voltage VCC= 3.6 V to 40 V 1 1 kHz

TA=40C to 25C 4 0.4 4 4 0.4 4 kHz

Frequency change with temperature TA=20C to 25C 4 0.4 4 4 0.4 4 kHz

TA= 25C to 85C 4 0.2 4 4 0.2 4 kHz

Voltage at RT 1 1 V


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electrical characteristics over recommended operating free-air temperature range, VCC= 6 V,fosc= 100 kHz (unless otherwise noted) (continued)

dead-time control



pTL5001C V(DT)= 1.5 V 0.9 IRT 1.1 IRT 0.9 IRT 1.1 IRT

TL5001I V(DT)= 1.5 V 0.9 IRT

1.2 IRT 0.9 IRT 1.2 IRT

pDuty cycle = 0% 0.5 0.7 0.5 0.7

Duty cycle = 100% 1.3 1.5 1.3 1.5

All typical values are at TA= 25C. Output source current at RT

error amplifier



Input voltage VCC= 3.6 V to 40 V 0 1.5 0 1.5 V

Input bias current 160 500 160 500 nA

p Positive 1.5 2.3 1.5 2.3 VNegative 0.3 0.4 0.3 0.4 V

Open-loop voltage amplification 80 80 dB

Unity-gain bandwidth 1.5 1.5 MHz

Output (sink) current VI(FB)= 1.2 V, COMP = 1 V 100 600 100 600 A

Output (source) current VI(FB)= 0.8 V, COMP = 1 V 45 70 45 70 A


output



Output saturation voltage IO= 10 mA 1.5 2 1.5 2 V

VO= 50 V, VCC= 0 10 10-VO= 50 V 10 10

Short-circuit output current VO= 6 V 40 40 mA


total device



Standby supply current Off state 1 1.5 1 1.5 mA

Average supply current Rt= 100 k 1.4 2.1 1.4 2.1 mA


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electrical characteristics over recommended operating free-air temperature range, VCC= 6 V,fosc= 100 kHz (unless otherwise noted)

reference

PARAMETER TEST CONDITIONS

TL5001Q,

TL5001M

TL5001AQ,

TL5001AM UNIT


pTA= 25C 0.95 1.00 1.05 0.97 1.00 1.03

TA= MIN to MAX

0.93 0.98 1.07 0.94 0.98 1.06

Input regulation TA= MIN to MAX VCC= 3.6 V to 40 V 2 12.5 2 12.5 mV

Output voltage change with temper-

atureTA= MIN to MAX *6 2 *6 *6 2 *6 %


*Not production tested.

undervoltage lockout


TL5001Q,TL5001M

TL5001AQ,TL5001AM UNIT


ppTA= MIN, 25C 3.00 3.00

TA= MAX 2.55 2.55

TA= MIN, 25C 2.8 2.8

TA= MAX 2.0 2.0

Hysteresis TA= MIN to MAX 100 200 100 200 mV

TA= MIN, 25C 2.10 2.55 2.10 2.55

TA= MAX 0.35 0.63 0.35 0.63


short-circuit protection


TL5001Q,

TL5001M

TL5001AQ,

TL5001AM UNIT


TA= MIN, 25C 0.95 1.00 1.05 0.97 1.00 1.03

TA= MAX 0.93 0.98 1.07 0.94 0.98 1.06

SCP voltage, latched TA= MIN to MAX No pullup 140 185 230 140 185 230 mV

SCP voltage, UVLO standby TA= MIN to MAX No pullup 60 120 60 120 mV

Equivalent timing resistance TA= MIN to MAX 185 185 k

SCP comparator 1 threshold voltage TA= MIN to MAX 1.5 1.5 V


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oscillator


TL5001Q,

TL5001M

TL5001AQ,

TL5001AM UNIT


Frequency TA= MIN to MAX Rt= 100 k 100 100 kHz

Standard deviation of frequency TA= MIN to MAX 2 2 kHz

Frequency change with voltage TA= MIN to MAX VCC= 3.6 V to 40 V 1 1 kHz

Fre uenc chan e with Q suffix *6 3 *6 *6 3 *6temperature A

=M suffix *9 5 *9 *9 5 *9

Voltage at RT TA= MIN to MAX 1 1 V


*Not production tested.

dead-time control

TL5001Q, TL5001M TL5001AQ, TL5001AM

MIN TYP

MAX MIN TYP

MAXOutput (source)current TA= MIN to MAX V(DT)= 1.5 V 0.9 IRT

1.1 IRT 0.9 IRT 1.1 IRT A

Duty cycle = 0% 0.5 0.7 0.5 0.7

Input thresholdA=

Duty cycle = 100% 1.3 1.5 1.3 1.5

voltage Duty cycle = 0% 0.4 0.7 0.4 0.7A=

Duty cycle = 100% 1.3 1.7 1.3 1.7

All typical values are at TA= 25C. Output source current at RT

error amplifier


TL5001Q,TL5001M


MIN TYP

MAX MIN TYP

MAXInput bias current TA= MIN to MAX 160 500 160 500 nA

Output volta e Positive 1.5 2.3 1.5 2.3 Vswing Negative

A=0.3 0.4 0.3 0.4 V

Open-loop voltageamplification TA= MIN to MAX 80 80 dB

Unity-gain bandwidth TA= MIN to MAX 1.5 1.5 MHz

Output (sink) current TA= MIN to MAX VI(FB)= 1.2 V, COMP = 1 V 100 600 100 600 A

pTA= MIN, 25C 45 70 45 70

TA= MAX

I(FB)= . , =30 45 30 45


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output


TL5001Q,

TL5001M

TL5001AQ,

TL5001AM UNIT


Output saturation voltage TA= MIN to MAX IO= 10 mA 1.5 2 1.5 2 V

VO= 50 V, VCC= 0 10 10- A=

VO= 50 V 10 10

Short-circuit output current TA= MIN to MAX VO= 6 V 40 40 mA


total device


TL5001Q,TL5001M



Standby supply current Off state TA= MIN to MAX 1 1.5 1 1.5 mA

Average supply current TA

= MIN to MAX Rt= 100 k 1.4 2.1 1.4 2.1 mA


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PARAMETER MEASUREMENT INFORMATION

2.3 V

SCP Timing Period

3 V

DTC

OSC

COMP

1 V

0 V

PWM/DTCComparator

OUT

SCPComparator 1

SCP

SCPComparator 2

VCC

1.5 V

NOTE A: The waveforms show timing characteristics for an intermittent short circuit and a longer short circuit that is sufficient to activate SCP.

Figure 4. PWM Timing Diagram

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TYPICAL CHARACTERISTICS

Figure 9

1

0.5

0

2

1.5

0 10 20 30 40

AverageSupplyCurrent

mA

VCCPower-Supply VoltageV

Rt= 100 k

TA= 25 C

AVERAGE SUPPLY CURRENT

vs

POWER-SUPPLY VOLTAGE

IC

C

Figure 10

1

0.9

0.8

050 25 0

AverageSupplyCurrent

mA

1.1

1.2

1.3

25 50 75 100

TAAmbient TemperatureC

VCC= 6 V

Rt= 100 k

DT Resistance = 100 k

ICC

AVERAGE SUPPLY CURRENT

vs

AMBIENT TEMPERATURE

Figure 11

1.5

1.2

0.6

0.3

0

1.8

0.9

10 k 100 k 1 M 10 M

PW

MTriangleWaveAmplitudeVoltageV

foscOscillator FrequencyHz

Voscmin (zero duty cycle)

VCC= 6 VTA= 25 C

PWM TRIANGLE WAVE AMPLITUDE VOLTAGE

vs

OSCILLATOR FREQUENCY

Voscmax (100% duty cycle)

Figure 12

ERROR AMPLIFIER OUTPUT VOLTAGE

vs

OUTPUT (SINK) CURRENT

ErrorAmplifierOutputVoltage

V

VO

IOOutput (Sink) CurrentmA

1.5

1

0.5

00 0.2 0.4

2

2.5

3

0.6

VCC

= 6 V

VI(FB)= 1.2 V

TA=25C

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Figure 13

1.5

1

0.5

00 20 40


V

2

2.5

3

60 80 100 120

VO

IOOutput (Source) CurrentA

VCC= 6 VVI(FB)= 0.8 V

TA= 25 C


vs

OUTPUT (SOURCE) CURRENT

Figure 14

2.43

2.42

2.41

2.4050 25 0


V

2.44

2.45

2.46

25 50 75 100

VO



No Load


vs

AMBIENT TEMPERATURE

Figure 15

180

160

140

12050 25 0


mV

200

220

240

25 50 75 100

VO



No Load


vs

AMBIENT TEMPERATURE

Figure 16

30

20

0

10

20

40

10

10 k 100 k 1 M 10 M

ErrorAmplifierOpen-LoopGain

dB

f FrequencyHz

VCC= 6 VTA= 25 C

AV

Er

rorAmplifierOpen-LoopPhaseShift

AV

ERROR AMPLIFIER OPEN-LOOP GAIN AND

PHASE SHIFT

vs

FREQUENCY

180

210

240

270

300

330

360

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Figure 17

60

40

20

00 0.5 1

80

100

120

1.5 2

DTC VoltageV

OUTPUT DUTY CYCLE

vs

DTC VOLTAGE

OutputDutyCycle

%

VCC= 6 VRt= 100 k

TA= 25 C

Figure 18

6

4

2

00 20 40

SCPTime-OutPeriod

ms

8

10

12

60 80 100 120

VCC= 6 VRt= 100 k

DT Resistance = 200 k

TA= 25 C

CSCPSCP CapacitancenF

t

SCP

SCP TIME-OUT PERIOD

vs

SCP CAPACITANCE

Figure 19

30

20

10

00 10 20

DTCOutputCurrent

40

50

60

30 40 50 60

DT Voltage = 1.3 V

TA= 25 C

IORT Output CurrentA

A

IO(DT)

DTC OUTPUT CURRENT

vs

RT OUTPUT CURRENT

Figure 20

1

0.5

0

2

1.5

0 5 10 15 20

OutputSaturationVoltage

V

IOOutput (Sink) CurrentmA

VCE

VCC= 6 V

TA= 25 C

OUTPUT SATURATION VOLTAGE

vs

OUTPUT (SINK) CURRENT

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APPLICATION INFORMATION

U1TL5001/A

FB

COMP

VO

DTC

RT

GND

C1100 F

10 V

VI5 V

+ R1470

SCP

VCC

L120 H

C2100 F

10 V

3.3 V

GND

+

CR1MBRS140T3

Q1TPS1101

C60.012 F

R45.1 k

R57.50 k1%

R256 k

R343 k

R63.24 k1%

C50.1 F

C41 F

C30.1 F

GND

8

7

6

5

2

1

3

4

Partial Bill of Materials:U1 TL5001/A Texas InstrumentsQ1 TPS1101 Texas InstrumentsLI CTX20-1 or Coiltronics

23 turns of #28 wire onMicrometals No. T50-26B core

C1 TPSD107M010R0100 AVXC2 TPSD107M010R0100 AVXCR1 MBRS140T3 Motorola

R7

2.0 k

C70.0047 F

+

NOTES: A. Frequency = 200 kHz

B. Duty cycle = 90% max

C. Soft-start time constant (TC) = 5.6 ms

D. SCP TC = 70 msA

Figure 21. Step-Down Converter

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MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047/ D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189(4,80)

(5,00)0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394(10,00)

0.386

0.004 (0,10)

M0.010 (0,25)

0.050 (1,27)

08

NOTES: B. All linear dimensions are in inches (millimeters).

C. This drawing is subject to change without notice.

D. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

E. Falls within JEDEC MS-012

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MECHANICAL DATA

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

4040140/ C 11/95

28 TERMINALS SHOWN

B

0.358

(9,09)

MAX

(11,63)

0.560

(14,22)

0.560

0.458

0.858

(21,8)

1.063

(27,0)

(14,22)

ANO. OF

MINMAX

0.358

0.660

0.761

0.458

0.342

(8,69)

MIN

(11,23)

(16,26)

0.640

0.740

0.442

(9,09)

(11,63)

(16,76)

0.962

1.165

(23,83)

0.938

(28,99)

1.141

(24,43)

(29,59)

(19,32)(18,78)

**

20

28

52

44

68

84

0.020 (0,51)

TERMINALS

0.080 (2,03)

0.064 (1,63)

(7,80)

0.307

(10,31)

0.406

(12,58)

0.495

(12,58)

0.495

(21,6)

0.850

(26,6)

1.047

0.045 (1,14)

0.045 (1,14)

0.035 (0,89)

0.035 (0,89)

0.010 (0,25)

121314151618 17

11

10

8

9

7

5

432

0.020 (0,51)

0.010 (0,25)

6

12826 27

19

21B SQ

A SQ

22

23

24

25

20

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold-plated.

E. Falls within JEDEC MS-004

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PACKAGE OPTION ADDENDUM

www.ti.com 17-Dec-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (C) Device Marking

(4/5)

5962-9958301QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9958301QPA

TL5001M

5962-9958302Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

9958302Q2A

TL5001

AMFKB5962-9958302QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9958302QPA

TL5001AM

TL5001ACD ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -20 to 85 5001AC

TL5001ACDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)


TL5001ACDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)


TL5001ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)


TL5001AID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 5001AI

TL5001AIDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)


TL5001AIDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)


TL5001AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)


TL5001AIP ACTIVE PDIP P 8 50 Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TL5001AIP

TL5001AIPE4 ACTIVE PDIP P 8 50 Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TL5001AIP

TL5001AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

9958302Q2A

TL5001

AMFKB

TL5001AMJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9958302QPA

TL5001AM

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Addendum-Page 2


(1)


Pins PackageQty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)


(4/5)

TL5001AQD ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 5001AQ

TL5001AQDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 5001AQ

TL5001AQDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 5001AQ

TL5001AQDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 5001AQ

TL5001CD ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -25 to 85 5001C

TL5001CDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)


TL5001CDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)


TL5001CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)


TL5001CP ACTIVE PDIP P 8 50 Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type -25 to 85 TL5001CP

TL5001CP-P ACTIVE PDIP P 8 50 Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type TL5001CP

TL5001CPE4 ACTIVE PDIP P 8 50 Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type -25 to 85 TL5001CP

TL5001CPS ACTIVE SO PS 8 80 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM T5001

TL5001CPSLE OBSOLETE SO PS 8 TBD Call TI Call TI

TL5001CPSR ACTIVE SO PS 8 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -25 to 85 T5001

TL5001CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -25 to 85 T5001

TL5001ID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 5001I

TL5001IDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)


TL5001IDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)


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Addendum-Page 3


(1)


Pins PackageQty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)


(4/5)

TL5001IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)


TL5001IP ACTIVE PDIP P 8 50 Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TL5001IP

TL5001IPE4 ACTIVE PDIP P 8 50 Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TL5001IP

TL5001IPSR ACTIVE SO PS 8 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM Z5001

TL5001MJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 TL5001MJG

TL5001MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9958301QPA

TL5001M

TL5001QD ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 5001Q

TL5001QDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 5001Q

TL5001QDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 5001Q

TL5001QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 5001Q

(1)

The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND:Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE:TI has discontinued the production of the device.(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
http://www.ti.com/productcontent

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Addendum-Page 4

(3)MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TL5001, TL5001A, TL5001AM, TL5001M :

Catalog: TL5001A,TL5001

Automotive: TL5001A-Q1, TL5001A-Q1

Military: TL5001M, TL5001AM

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Military - QML certified for Military and Defense Applications
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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TL5001ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL5001AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL5001AQDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL5001AQDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL5001CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL5001CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

TL5001IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL5001IPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

TL5001QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL5001QDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Mar-2013

Pack Materials-Page 1

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*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL5001ACDR SOIC D 8 2500 340.5 338.1 20.6

TL5001AIDR SOIC D 8 2500 340.5 338.1 20.6

TL5001AQDR SOIC D 8 2500 367.0 367.0 35.0

TL5001AQDRG4 SOIC D 8 2500 367.0 367.0 35.0

TL5001CDR SOIC D 8 2500 340.5 338.1 20.6

TL5001CPSR SO PS 8 2000 367.0 367.0 38.0

TL5001IDR SOIC D 8 2500 340.5 338.1 20.6

TL5001IPSR SO PS 8 2000 367.0 367.0 38.0

TL5001QDR SOIC D 8 2500 367.0 367.0 35.0

TL5001QDRG4 SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Mar-2013

Pack Materials-Page 2

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MECHANICAL DATA

MCER001A JANUARY 1995 REVISED JANUARY 1997

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.310 (7,87)

0.290 (7,37)

0.014 (0,36)

0.008 (0,20)

Seating Plane

4040107/C 08/96

5

4

0.065 (1,65)

0.045 (1,14)

8

1

0.020 (0,51) MIN

0.400 (10,16)

0.355 (9,00)

0.015 (0,38)

0.023 (0,58)

0.063 (1,60)

0.015 (0,38)

0.200 (5,08) MAX

0.130 (3,30) MIN

0.245 (6,22)

0.280 (7,11)

0.100 (2,54)

015

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

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IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherchanges to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latestissue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of salesupplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs termsand conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessaryto support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarilyperformed.

TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provideadequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI components or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty orendorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alterationand is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altereddocumentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or servicevoids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirementsconcerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or supportthat may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards whichanticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might causeharm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the useof any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TIs goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed a special agreement specifically governing such use.

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which have n ot been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal andregulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright 2015, Texas Instruments Incorporated
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