tiva c series tm4c1294nczad microcontroller data sheet (rev. b)€¦ · 5.2.4 powercontrol.....230...

Tiva™ TM4C1294NCZAD Microcontroller

DATA SHEET

Copyr ight © 2007-2014Texas Instruments Incorporated

DS-TM4C1294NCZAD-15863.2743SPMS434B

TEXAS INSTRUMENTS-PRODUCTION DATA

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June 18, 20142Texas Instruments-Production Data

http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 45About This Document .................................................................................................................... 48Audience .............................................................................................................................................. 48About This Manual ................................................................................................................................ 48Related Documents ............................................................................................................................... 48Documentation Conventions .................................................................................................................. 49

1 Architectural Overview .......................................................................................... 511.1 Tiva™ C Series Overview .............................................................................................. 511.2 TM4C1294NCZAD Microcontroller Overview .................................................................. 521.3 TM4C1294NCZAD Microcontroller Features ................................................................... 551.3.1 ARM Cortex-M4F Processor Core .................................................................................. 551.3.2 On-Chip Memory ........................................................................................................... 571.3.3 External Peripheral Interface ......................................................................................... 591.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 611.3.5 Serial Communications Peripherals ................................................................................ 611.3.6 System Integration ........................................................................................................ 671.3.7 Advanced Motion Control ............................................................................................... 741.3.8 Analog .......................................................................................................................... 761.3.9 JTAG and ARM Serial Wire Debug ................................................................................ 781.3.10 Packaging and Temperature .......................................................................................... 781.4 TM4C1294NCZAD Microcontroller Hardware Details ....................................................... 791.5 Kits .............................................................................................................................. 791.6 Support Information ....................................................................................................... 79

2 The Cortex-M4F Processor ................................................................................... 802.1 Block Diagram .............................................................................................................. 812.2 Overview ...................................................................................................................... 822.2.1 System-Level Interface .................................................................................................. 822.2.2 Integrated Configurable Debug ...................................................................................... 822.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 832.2.4 Cortex-M4F System Component Details ......................................................................... 832.3 Programming Model ...................................................................................................... 842.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 842.3.2 Stacks .......................................................................................................................... 852.3.3 Register Map ................................................................................................................ 852.3.4 Register Descriptions .................................................................................................... 872.3.5 Exceptions and Interrupts ............................................................................................ 1032.3.6 Data Types ................................................................................................................. 1032.4 Memory Model ............................................................................................................ 1032.4.1 Memory Regions, Types and Attributes ......................................................................... 1062.4.2 Memory System Ordering of Memory Accesses ............................................................ 1072.4.3 Behavior of Memory Accesses ..................................................................................... 1072.4.4 Software Ordering of Memory Accesses ....................................................................... 1082.4.5 Bit-Banding ................................................................................................................. 1092.4.6 Data Storage .............................................................................................................. 1112.4.7 Synchronization Primitives ........................................................................................... 112

3June 18, 2014Texas Instruments-Production Data


2.5 Exception Model ......................................................................................................... 1132.5.1 Exception States ......................................................................................................... 1142.5.2 Exception Types .......................................................................................................... 1142.5.3 Exception Handlers ..................................................................................................... 1192.5.4 Vector Table ................................................................................................................ 1192.5.5 Exception Priorities ...................................................................................................... 1202.5.6 Interrupt Priority Grouping ............................................................................................ 1212.5.7 Exception Entry and Return ......................................................................................... 1212.6 Fault Handling ............................................................................................................. 1242.6.1 Fault Types ................................................................................................................. 1252.6.2 Fault Escalation and Hard Faults .................................................................................. 1252.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1262.6.4 Lockup ....................................................................................................................... 1262.7 Power Management .................................................................................................... 1272.7.1 Entering Sleep Modes ................................................................................................. 1272.7.2 Wake Up from Sleep Mode .......................................................................................... 1272.8 Instruction Set Summary .............................................................................................. 128

3 Cortex-M4 Peripherals ......................................................................................... 1353.1 Functional Description ................................................................................................. 1353.1.1 System Timer (SysTick) ............................................................................................... 1363.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1373.1.3 System Control Block (SCB) ........................................................................................ 1383.1.4 Memory Protection Unit (MPU) ..................................................................................... 1383.1.5 Floating-Point Unit (FPU) ............................................................................................. 1433.2 Register Map .............................................................................................................. 1473.3 System Timer (SysTick) Register Descriptions .............................................................. 1503.4 NVIC Register Descriptions .......................................................................................... 1543.5 System Control Block (SCB) Register Descriptions ........................................................ 1643.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 1933.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 202

4 JTAG Interface ...................................................................................................... 2084.1 Block Diagram ............................................................................................................ 2094.2 Signal Description ....................................................................................................... 2094.3 Functional Description ................................................................................................. 2104.3.1 JTAG Interface Pins ..................................................................................................... 2104.3.2 JTAG TAP Controller ................................................................................................... 2124.3.3 Shift Registers ............................................................................................................ 2134.3.4 Operational Considerations .......................................................................................... 2134.4 Initialization and Configuration ..................................................................................... 2164.5 Register Descriptions .................................................................................................. 2164.5.1 Instruction Register (IR) ............................................................................................... 2174.5.2 Data Registers ............................................................................................................ 218

5 System Control ..................................................................................................... 2215.1 Signal Description ....................................................................................................... 2215.2 Functional Description ................................................................................................. 2215.2.1 Device Identification .................................................................................................... 2225.2.2 Reset Control .............................................................................................................. 2225.2.3 Non-Maskable Interrupt ............................................................................................... 229


Table of Contents

5.2.4 Power Control ............................................................................................................. 2305.2.5 Clock Control .............................................................................................................. 2315.2.6 System Control ........................................................................................................... 2405.3 Initialization and Configuration ..................................................................................... 2475.4 Register Map .............................................................................................................. 2485.5 System Control Register Descriptions (System Control Offset) ....................................... 255

6 Processor Support and Exception Module ........................................................ 5276.1 Functional Description ................................................................................................. 5276.2 Register Map .............................................................................................................. 5276.3 Register Descriptions .................................................................................................. 527

7 Hibernation Module .............................................................................................. 5357.1 Block Diagram ............................................................................................................ 5377.2 Signal Description ....................................................................................................... 5377.3 Functional Description ................................................................................................. 5387.3.1 Register Access Timing ............................................................................................... 5397.3.2 Hibernation Clock Source ............................................................................................ 5397.3.3 System Implementation ............................................................................................... 5427.3.4 Battery Management ................................................................................................... 5437.3.5 Real-Time Clock .......................................................................................................... 5437.3.6 Tamper ....................................................................................................................... 5467.3.7 Battery-Backed Memory .............................................................................................. 5497.3.8 Power Control Using HIB ............................................................................................. 5497.3.9 Power Control Using VDD3ON Mode ........................................................................... 5507.3.10 Initiating Hibernate ...................................................................................................... 5507.3.11 Waking from Hibernate ................................................................................................ 5507.3.12 Arbitrary Power Removal ............................................................................................. 5517.3.13 Interrupts and Status ................................................................................................... 5527.4 Initialization and Configuration ..................................................................................... 5527.4.1 Initialization ................................................................................................................. 5527.4.2 RTC Match Functionality (No Hibernation) .................................................................... 5537.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 5537.4.4 External Wake-Up from Hibernation .............................................................................. 5547.4.5 RTC or External Wake-Up from Hibernation .................................................................. 5557.4.6 Tamper Initialization ..................................................................................................... 5557.5 Register Map .............................................................................................................. 5557.6 Register Descriptions .................................................................................................. 557

8 Internal Memory ................................................................................................... 6048.1 Block Diagram ............................................................................................................ 6048.2 Functional Description ................................................................................................. 6068.2.1 SRAM ........................................................................................................................ 6068.2.2 ROM .......................................................................................................................... 6068.2.3 Flash Memory ............................................................................................................. 6088.2.4 EEPROM .................................................................................................................... 6198.2.5 Bus Matrix Memory Accesses ...................................................................................... 6258.3 Register Map .............................................................................................................. 6258.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 6288.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 6548.6 Memory Register Descriptions (System Control Offset) .................................................. 671



9 Micro Direct Memory Access (μDMA) ................................................................ 6829.1 Block Diagram ............................................................................................................ 6839.2 Functional Description ................................................................................................. 6839.2.1 Channel Assignments .................................................................................................. 6849.2.2 Priority ........................................................................................................................ 6859.2.3 Arbitration Size ............................................................................................................ 6869.2.4 Request Types ............................................................................................................ 6869.2.5 Channel Configuration ................................................................................................. 6879.2.6 Transfer Modes ........................................................................................................... 6899.2.7 Transfer Size and Increment ........................................................................................ 6979.2.8 Peripheral Interface ..................................................................................................... 6979.2.9 Software Request ........................................................................................................ 6989.2.10 Interrupts and Errors .................................................................................................... 6989.3 Initialization and Configuration ..................................................................................... 6989.3.1 Module Initialization ..................................................................................................... 6989.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 6999.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 7009.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 7029.3.5 Configuring Channel Assignments ................................................................................ 7059.4 Register Map .............................................................................................................. 7059.5 μDMA Channel Control Structure ................................................................................. 7069.6 μDMA Register Descriptions ........................................................................................ 713

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 74610.1 Signal Description ....................................................................................................... 74710.2 Pad Capabilities .......................................................................................................... 75210.3 Functional Description ................................................................................................. 75210.3.1 Data Control ............................................................................................................... 75410.3.2 Interrupt Control .......................................................................................................... 75610.3.3 Mode Control .............................................................................................................. 75710.3.4 Commit Control ........................................................................................................... 75810.3.5 Pad Control ................................................................................................................. 75810.3.6 Identification ............................................................................................................... 75910.4 Initialization and Configuration ..................................................................................... 75910.5 Register Map .............................................................................................................. 76110.6 Register Descriptions .................................................................................................. 764

11 External Peripheral Interface (EPI) ..................................................................... 82211.1 EPI Block Diagram ...................................................................................................... 82311.2 Signal Description ....................................................................................................... 82411.3 Functional Description ................................................................................................. 82511.3.1 Master Access to EPI .................................................................................................. 82611.3.2 Non-Blocking Reads .................................................................................................... 82611.3.3 DMA Operation ........................................................................................................... 82711.4 Initialization and Configuration ..................................................................................... 82811.4.1 EPI Interface Options .................................................................................................. 82911.4.2 SDRAM Mode ............................................................................................................. 82911.4.3 Host Bus Mode ........................................................................................................... 83311.4.4 General-Purpose Mode ............................................................................................... 85411.5 Register Map .............................................................................................................. 861


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11.6 Register Descriptions .................................................................................................. 863

12 Cyclical Redundancy Check (CRC) .................................................................... 95312.1 Functional Description ................................................................................................. 95312.1.1 CRC Support .............................................................................................................. 95312.2 Initialization and Configuration ..................................................................................... 95512.2.1 CRC Initialization and Configuration ............................................................................. 95512.3 Register Map .............................................................................................................. 95612.4 CRC Module Register Descriptions .............................................................................. 956

13 General-Purpose Timers ...................................................................................... 96213.1 Block Diagram ............................................................................................................ 96313.2 Signal Description ....................................................................................................... 96413.3 Functional Description ................................................................................................. 96513.3.1 GPTM Reset Conditions .............................................................................................. 96613.3.2 Timer Clock Source ..................................................................................................... 96613.3.3 Timer Modes ............................................................................................................... 96713.3.4 Wait-for-Trigger Mode .................................................................................................. 97613.3.5 Synchronizing GP Timer Blocks ................................................................................... 97713.3.6 DMA Operation ........................................................................................................... 97813.3.7 ADC Operation ............................................................................................................ 97813.3.8 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 97813.4 Initialization and Configuration ..................................................................................... 97913.4.1 One-Shot/Periodic Timer Mode .................................................................................... 97913.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 98013.4.3 Input Edge-Count Mode ............................................................................................... 98013.4.4 Input Edge Time Mode ................................................................................................. 98113.4.5 PWM Mode ................................................................................................................. 98113.5 Register Map .............................................................................................................. 98213.6 Register Descriptions .................................................................................................. 983

14 Watchdog Timers ............................................................................................... 103614.1 Block Diagram ........................................................................................................... 103714.2 Functional Description ............................................................................................... 103714.2.1 Register Access Timing ............................................................................................. 103814.3 Initialization and Configuration .................................................................................... 103814.4 Register Map ............................................................................................................ 103814.5 Register Descriptions ................................................................................................. 1039

15 Analog-to-Digital Converter (ADC) ................................................................... 106115.1 Block Diagram ........................................................................................................... 106215.2 Signal Description ..................................................................................................... 106315.3 Functional Description ............................................................................................... 106415.3.1 Sample Sequencers .................................................................................................. 106515.3.2 Module Control .......................................................................................................... 106515.3.3 Hardware Sample Averaging Circuit ........................................................................... 107115.3.4 Analog-to-Digital Converter ........................................................................................ 107115.3.5 Differential Sampling .................................................................................................. 107315.3.6 Internal Temperature Sensor ...................................................................................... 107515.3.7 Digital Comparator Unit .............................................................................................. 107615.4 Initialization and Configuration .................................................................................... 1081



15.4.1 Module Initialization ................................................................................................... 108115.4.2 Sample Sequencer Configuration ............................................................................... 108215.5 Register Map ............................................................................................................ 108215.6 Register Descriptions ................................................................................................. 1085

16 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 117016.1 Block Diagram ........................................................................................................... 117116.2 Signal Description ..................................................................................................... 117116.3 Functional Description ............................................................................................... 117316.3.1 Transmit/Receive Logic .............................................................................................. 117416.3.2 Baud-Rate Generation ............................................................................................... 117416.3.3 Data Transmission ..................................................................................................... 117516.3.4 Serial IR (SIR) ........................................................................................................... 117516.3.5 ISO 7816 Support ...................................................................................................... 117716.3.6 Modem Handshake Support ....................................................................................... 117716.3.7 9-Bit UART Mode ...................................................................................................... 117816.3.8 FIFO Operation ......................................................................................................... 117916.3.9 Interrupts .................................................................................................................. 117916.3.10 Loopback Operation .................................................................................................. 118016.3.11 DMA Operation ......................................................................................................... 118016.4 Initialization and Configuration .................................................................................... 118116.5 Register Map ............................................................................................................ 118216.6 Register Descriptions ................................................................................................. 1184

17 Quad Synchronous Serial Interface (QSSI) ..................................................... 123617.1 Block Diagram ........................................................................................................... 123617.2 Signal Description ..................................................................................................... 123717.3 Functional Description ............................................................................................... 123917.3.1 Bit Rate Generation ................................................................................................... 123917.3.2 FIFO Operation ......................................................................................................... 123917.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 124017.3.4 SSInFSS Function ..................................................................................................... 124117.3.5 High Speed Clock Operation ...................................................................................... 124217.3.6 Interrupts .................................................................................................................. 124217.3.7 Frame Formats ......................................................................................................... 124317.3.8 DMA Operation ......................................................................................................... 125017.4 Initialization and Configuration .................................................................................... 125017.4.1 Enhanced Mode Configuration ................................................................................... 125217.5 Register Map ............................................................................................................ 125317.6 Register Descriptions ................................................................................................. 1254

18 Inter-Integrated Circuit (I2C) Interface .............................................................. 128518.1 Block Diagram ........................................................................................................... 128618.2 Signal Description ..................................................................................................... 128718.3 Functional Description ............................................................................................... 128818.3.1 I2C Bus Functional Overview ...................................................................................... 128818.3.2 Available Speed Modes ............................................................................................. 129418.3.3 Interrupts .................................................................................................................. 129618.3.4 Loopback Operation .................................................................................................. 129718.3.5 FIFO and µDMA Operation ........................................................................................ 129718.3.6 Command Sequence Flow Charts .............................................................................. 1299


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18.4 Initialization and Configuration .................................................................................... 130718.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 130718.4.2 Configure the I2C Master to High Speed Mode ............................................................ 130818.5 Register Map ............................................................................................................ 130918.6 Register Descriptions (I2C Master) .............................................................................. 131118.7 Register Descriptions (I2C Slave) ............................................................................... 134018.8 Register Descriptions (I2C Status and Control) ............................................................ 1357

19 Controller Area Network (CAN) Module ........................................................... 136619.1 Block Diagram ........................................................................................................... 136719.2 Signal Description ..................................................................................................... 136719.3 Functional Description ............................................................................................... 136819.3.1 Initialization ............................................................................................................... 136919.3.2 Operation .................................................................................................................. 136919.3.3 Transmitting Message Objects ................................................................................... 137019.3.4 Configuring a Transmit Message Object ...................................................................... 137119.3.5 Updating a Transmit Message Object ......................................................................... 137219.3.6 Accepting Received Message Objects ........................................................................ 137219.3.7 Receiving a Data Frame ............................................................................................ 137319.3.8 Receiving a Remote Frame ........................................................................................ 137319.3.9 Receive/Transmit Priority ........................................................................................... 137419.3.10 Configuring a Receive Message Object ...................................................................... 137419.3.11 Handling of Received Message Objects ...................................................................... 137519.3.12 Handling of Interrupts ................................................................................................ 137719.3.13 Test Mode ................................................................................................................. 137819.3.14 Bit Timing Configuration Error Considerations ............................................................. 138019.3.15 Bit Time and Bit Rate ................................................................................................. 138019.3.16 Calculating the Bit Timing Parameters ........................................................................ 138219.4 Register Map ............................................................................................................ 138519.5 CAN Register Descriptions ......................................................................................... 1386

20 Ethernet Controller ............................................................................................ 141720.1 Block Diagram ........................................................................................................... 141820.2 Signal Description ..................................................................................................... 141820.3 Functional Description ............................................................................................... 141920.3.1 Ethernet Clock Control ............................................................................................... 141920.3.2 DMA Controller ......................................................................................................... 142020.3.3 TX/RX Controller ....................................................................................................... 144420.3.4 MAC Operation ......................................................................................................... 144820.3.5 IEEE 1588 and Advanced Timestamp Function ........................................................... 145020.3.6 Frame Filtering .......................................................................................................... 145920.3.7 Source Address, VLAN, and CRC Insertion, Replacement or Deletion .......................... 146020.3.8 Checksum Offload Engine .......................................................................................... 146220.3.9 MAC Management Counters ...................................................................................... 146320.3.10 Power Management Module ....................................................................................... 146420.3.11 Serial Management Interface ..................................................................................... 146720.3.12 Interrupt Configuration ............................................................................................... 146720.4 Ethernet PHY ............................................................................................................ 146720.4.1 Integrated PHY Block Diagram ................................................................................... 146720.4.2 Functional Description ............................................................................................... 1468



20.4.3 Interface Configuration ............................................................................................... 147320.5 Initialization and Configuration .................................................................................... 147420.5.1 Ethernet PHY Initialization .......................................................................................... 147520.6 Register Map ............................................................................................................ 147720.7 Ethernet MAC Register Descriptions ........................................................................... 148020.8 Ethernet PHY Register Descriptions ........................................................................... 1599

21 Universal Serial Bus (USB) Controller ............................................................. 165421.1 Block Diagram ........................................................................................................... 165521.2 Signal Description ..................................................................................................... 165521.3 Register Map ............................................................................................................ 1656

22 Analog Comparators .......................................................................................... 166322.1 Block Diagram ........................................................................................................... 166422.2 Signal Description ..................................................................................................... 166422.3 Functional Description ............................................................................................... 166522.3.1 Internal Reference Programming ................................................................................ 166622.4 Initialization and Configuration .................................................................................... 166822.5 Register Map ............................................................................................................ 166922.6 Register Descriptions ................................................................................................. 1669

23 Pulse Width Modulator (PWM) .......................................................................... 167923.1 Block Diagram ........................................................................................................... 168023.2 Signal Description ..................................................................................................... 168223.3 Functional Description ............................................................................................... 168223.3.1 Clock Configuration ................................................................................................... 168223.3.2 PWM Timer ............................................................................................................... 168323.3.3 PWM Comparators .................................................................................................... 168323.3.4 PWM Signal Generator .............................................................................................. 168423.3.5 Dead-Band Generator ............................................................................................... 168523.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 168523.3.7 Synchronization Methods .......................................................................................... 168623.3.8 Fault Conditions ........................................................................................................ 168723.3.9 Output Control Block .................................................................................................. 168823.4 Initialization and Configuration .................................................................................... 168823.5 Register Map ............................................................................................................ 168923.6 Register Descriptions ................................................................................................. 1692

24 Quadrature Encoder Interface (QEI) ................................................................. 175824.1 Block Diagram ........................................................................................................... 175824.2 Signal Description ..................................................................................................... 176024.3 Functional Description ............................................................................................... 176024.4 Initialization and Configuration .................................................................................... 176324.5 Register Map ............................................................................................................ 176324.6 Register Descriptions ................................................................................................. 1764

25 Pin Diagram ........................................................................................................ 178126 Signal Tables ...................................................................................................... 178226.1 Signals by Pin Number .............................................................................................. 178326.2 Signals by Signal Name ............................................................................................. 180026.3 Signals by Function, Except for GPIO ......................................................................... 181626.4 GPIO Pins and Alternate Functions ............................................................................ 1829


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26.5 Possible Pin Assignments for Alternate Functions ....................................................... 183426.6 Connections for Unused Signals ................................................................................. 1840

27 Electrical Characteristics .................................................................................. 184227.1 Maximum Ratings ...................................................................................................... 184227.2 Operating Characteristics ........................................................................................... 184327.3 Recommended Operating Conditions ......................................................................... 184427.3.1 DC Operating Conditions ........................................................................................... 184427.3.2 Recommended GPIO Operating Characteristics .......................................................... 184427.4 Load Conditions ........................................................................................................ 184727.5 JTAG and Boundary Scan .......................................................................................... 184827.6 Power and Brown-Out ............................................................................................... 185027.6.1 VDDA Levels .............................................................................................................. 185027.6.2 VDD Levels ................................................................................................................ 185127.6.3 VDDC Levels .............................................................................................................. 185227.6.4 Response ................................................................................................................. 185327.7 Reset ........................................................................................................................ 185527.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 185827.9 Clocks ...................................................................................................................... 185927.9.1 PLL Specifications ..................................................................................................... 185927.9.2 PIOSC Specifications ................................................................................................ 186127.9.3 Low-Frequency Internal Oscillator Specifications ......................................................... 186127.9.4 Hibernation Clock Source Specifications ..................................................................... 186127.9.5 Main Oscillator Specifications ..................................................................................... 186227.9.6 System Clock Specification with ADC Operation .......................................................... 186627.9.7 System Clock Specification with USB Operation .......................................................... 186627.10 Sleep Modes ............................................................................................................. 186727.11 Hibernation Module ................................................................................................... 186927.12 Flash Memory ........................................................................................................... 187127.13 EEPROM .................................................................................................................. 187227.14 Input/Output Pin Characteristics ................................................................................. 187327.14.1 Types of I/O Pins and ESD Protection ......................................................................... 187527.15 External Peripheral Interface (EPI) .............................................................................. 187727.16 Analog-to-Digital Converter (ADC) .............................................................................. 188527.17 Synchronous Serial Interface (SSI) ............................................................................. 189127.18 Inter-Integrated Circuit (I2C) Interface ......................................................................... 189427.19 Ethernet Controller .................................................................................................... 189527.19.1 DC Characteristics .................................................................................................... 189527.19.2 Clock Characteristics ................................................................................................. 189527.19.3 AC Characteristics ..................................................................................................... 189627.20 Universal Serial Bus (USB) Controller ......................................................................... 189927.21 Analog Comparator ................................................................................................... 190127.22 Pulse-Width Modulator (PWM) ................................................................................... 190327.23 Current Consumption ................................................................................................ 1904

A Package Information .......................................................................................... 1909A.1 Orderable Devices ..................................................................................................... 1909A.2 Device Nomenclature ................................................................................................ 1909A.3 Device Markings ........................................................................................................ 1909A.4 Packaging Diagram ................................................................................................... 1911



List of FiguresFigure 1-1. Tiva™ TM4C1294NCZAD Microcontroller High-Level Block Diagram ....................... 54Figure 2-1. CPU Block Diagram ............................................................................................. 82Figure 2-2. TPIU Block Diagram ............................................................................................ 83Figure 2-3. Cortex-M4F Register Set ...................................................................................... 86Figure 2-4. Bit-Band Mapping .............................................................................................. 111Figure 2-5. Data Storage ..................................................................................................... 112Figure 2-6. Vector Table ...................................................................................................... 120Figure 2-7. Exception Stack Frame ...................................................................................... 123Figure 3-1. SRD Use Example ............................................................................................. 141Figure 3-2. FPU Register Bank ............................................................................................ 144Figure 4-1. JTAG Module Block Diagram .............................................................................. 209Figure 4-2. Test Access Port State Machine ......................................................................... 213Figure 4-3. IDCODE Register Format ................................................................................... 219Figure 4-4. BYPASS Register Format ................................................................................... 219Figure 4-5. Boundary Scan Register Format ......................................................................... 219Figure 5-1. Basic RST Configuration .................................................................................... 225Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 225Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 225Figure 5-4. Power Architecture ............................................................................................ 231Figure 5-5. Main Clock Tree ................................................................................................ 234Figure 5-6. Module Clock Selection ...................................................................................... 243Figure 7-1. Hibernation Module Block Diagram ..................................................................... 537Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 541Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 541Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 542Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 546Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 546Figure 7-7. Tamper Block Diagram ....................................................................................... 546Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 547Figure 8-1. Internal Memory Block Diagram .......................................................................... 605Figure 8-2. Flash Memory Configuration ............................................................................... 609Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 610Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 610Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 611Figure 8-6. Prefetch Fills from Flash ..................................................................................... 612Figure 8-7. Mirror Mode Function ......................................................................................... 613Figure 9-1. μDMA Block Diagram ......................................................................................... 683Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 690Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 692Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 693Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 695Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 696Figure 10-1. Digital I/O Pads ................................................................................................. 753Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 754Figure 10-3. GPIODATA Write Example ................................................................................. 755


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Figure 10-4. GPIODATA Read Example ................................................................................. 755Figure 11-1. EPI Block Diagram ............................................................................................. 824Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 831Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 832Figure 11-4. SDRAM Write Cycle ........................................................................................... 833Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 843Figure 11-6. iRDY Signal Connection ..................................................................................... 843Figure 11-7. PSRAM Burst Read ........................................................................................... 846Figure 11-8. PSRAM Burst Write ........................................................................................... 846Figure 11-9. Read Delay During Refresh Event ...................................................................... 847Figure 11-10. Write Delay During Refresh Event ....................................................................... 848Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 849Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 852Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 852Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 0, RDHIGH = 0 ............................................................................................... 853Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or

Quad CSn ......................................................................................................... 853Figure 11-16. Continuous Read Mode Accesses ...................................................................... 853Figure 11-17. Write Followed by Read to External FIFO ............................................................ 854Figure 11-18. Two-Entry FIFO ................................................................................................. 854Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 857Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 858Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 858Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 859Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 859Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 859Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 859Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 860Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 860Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 860Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 861Figure 13-1. GPTM Module Block Diagram ............................................................................ 963Figure 13-2. Input Edge-Count Mode Example, Counting Down ............................................... 971Figure 13-3. 16-Bit Input Edge-Time Mode Example ............................................................... 973Figure 13-4. 16-Bit PWM Mode Example ................................................................................ 975Figure 13-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 975Figure 13-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 976Figure 13-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 976Figure 13-8. Timer Daisy Chain ............................................................................................. 977Figure 14-1. WDT Module Block Diagram ............................................................................. 1037Figure 15-1. Implementation of Two ADC Blocks .................................................................. 1062Figure 15-2. ADC Module Block Diagram ............................................................................. 1063Figure 15-3. ADC Sample Phases ....................................................................................... 1068Figure 15-4. Doubling the ADC Sample Rate ........................................................................ 1069Figure 15-5. Skewed Sampling ............................................................................................ 1070Figure 15-6. Sample Averaging Example .............................................................................. 1071Figure 15-7. ADC Input Equivalency .................................................................................... 1072



Figure 15-8. ADC Voltage Reference ................................................................................... 1072Figure 15-9. ADC Conversion Result ................................................................................... 1073Figure 15-10. Differential Voltage Representation ................................................................... 1075Figure 15-11. Internal Temperature Sensor Characteristic ....................................................... 1076Figure 15-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1079Figure 15-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1080Figure 15-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1081Figure 16-1. UART Module Block Diagram ........................................................................... 1171Figure 16-2. UART Character Frame .................................................................................... 1174Figure 16-3. IrDA Data Modulation ....................................................................................... 1176Figure 17-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1237Figure 17-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1244Figure 17-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1245Figure 17-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1246Figure 17-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1246Figure 17-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1247Figure 17-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1248Figure 17-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1248Figure 17-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1249Figure 18-1. I2C Block Diagram ........................................................................................... 1286Figure 18-2. I2C Bus Configuration ....................................................................................... 1288Figure 18-3. START and STOP Conditions ........................................................................... 1289Figure 18-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1290Figure 18-5. R/S Bit in First Byte .......................................................................................... 1290Figure 18-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1290Figure 18-7. High-Speed Data Format .................................................................................. 1296Figure 18-8. Master Single TRANSMIT ................................................................................ 1300Figure 18-9. Master Single RECEIVE ................................................................................... 1301Figure 18-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1302Figure 18-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1303Figure 18-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1304Figure 18-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1305Figure 18-14. Standard High Speed Mode Master Transmit ..................................................... 1306Figure 18-15. Slave Command Sequence .............................................................................. 1307Figure 19-1. CAN Controller Block Diagram .......................................................................... 1367Figure 19-2. CAN Data/Remote Frame ................................................................................. 1368Figure 19-3. Message Objects in a FIFO Buffer .................................................................... 1377Figure 19-4. CAN Bit Time ................................................................................................... 1381Figure 20-1. Ethernet MAC with Integrated PHY Interface ..................................................... 1418Figure 20-2. Ethernet MAC and PHY Clock Structure ............................................................ 1420Figure 20-3. Enhanced Transmit Descriptor Structure ........................................................... 1424Figure 20-4. Enhanced Receive Descriptor Structure ............................................................ 1429Figure 20-5. TX DMA Default Operation Using Descriptors .................................................... 1436Figure 20-6. TX DMA OSF Mode Operation Using Descriptors .............................................. 1438Figure 20-7. RX DMA Operation Flow .................................................................................. 1441Figure 20-8. Networked Time Synchronization ...................................................................... 1451Figure 20-9. System Time Update Using Fine Correction Method .......................................... 1453


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Figure 20-10. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer PathCorrection ....................................................................................................... 1456

Figure 20-11. Wake-Up Frame Filter Register Bank ................................................................ 1464Figure 20-12. Integrated PHY Diagram .................................................................................. 1468Figure 20-13. Interface to Ethernet Jack ................................................................................. 1474Figure 21-1. USB Module Block Diagram ............................................................................. 1655Figure 22-1. Analog Comparator Module Block Diagram ....................................................... 1664Figure 22-2. Structure of Comparator Unit ............................................................................ 1665Figure 22-3. Comparator Internal Reference Structure .......................................................... 1666Figure 23-1. PWM Module Diagram ..................................................................................... 1681Figure 23-2. PWM Generator Block Diagram ........................................................................ 1681Figure 23-3. PWM Count-Down Mode .................................................................................. 1684Figure 23-4. PWM Count-Up/Down Mode ............................................................................. 1684Figure 23-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1685Figure 23-6. PWM Dead-Band Generator ............................................................................. 1685Figure 24-1. QEI Block Diagram .......................................................................................... 1759Figure 24-2. QEI Input Signal Logic ...................................................................................... 1760Figure 24-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1762Figure 25-1. 212-Ball BGA Package Pin Diagram (Top View) ................................................. 1781Figure 27-1. Load Conditions ............................................................................................... 1847Figure 27-2. JTAG Test Clock Input Timing ........................................................................... 1849Figure 27-3. JTAG Test Access Port (TAP) Timing ................................................................ 1849Figure 27-4. Power and Brown-Out Assertions vs VDDA Levels .............................................. 1851Figure 27-5. Power and Brown-Out Assertions vs VDD Levels ................................................ 1852Figure 27-6. POK Assertion vs VDDC ................................................................................... 1853Figure 27-7. POR-BOR VDD Glitch Response ....................................................................... 1853Figure 27-8. POR-BOR VDD Droop Response ...................................................................... 1854Figure 27-9. Digital Power-On Reset Timing ......................................................................... 1855Figure 27-10. Brown-Out Reset Timing .................................................................................. 1856Figure 27-11. External Reset Timing (RST) ............................................................................ 1856Figure 27-12. Software Reset Timing ..................................................................................... 1856Figure 27-13. Watchdog Reset Timing ................................................................................... 1856Figure 27-14. MOSC Failure Reset Timing ............................................................................. 1857Figure 27-15. Hibernation Module Timing ............................................................................... 1870Figure 27-16. ESD Protection ................................................................................................ 1875Figure 27-17. ESD Protection for Non-Power Pins (Except WAKE Signal) ................................ 1876Figure 27-18. SDRAM Initialization and Load Mode Register Timing ........................................ 1878Figure 27-19. SDRAM Read Timing ....................................................................................... 1878Figure 27-20. SDRAM Write Timing ....................................................................................... 1879Figure 27-21. Host-Bus 8/16 Asynchronous Mode Read Timing ............................................... 1880Figure 27-22. Host-Bus 8/16 Asynchronous Mode Write Timing ............................................... 1880Figure 27-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing .................................... 1881Figure 27-24. Host-Bus 8/16 Mode Asynchronous Muxed Write Timing .................................... 1881Figure 27-25. General-Purpose Mode Read and Write Timing ................................................. 1882Figure 27-26. PSRAM Single Burst Read ............................................................................... 1883Figure 27-27. PSRAM Single Burst Write ............................................................................... 1884Figure 27-28. ADC External Reference Filtering ..................................................................... 1890Figure 27-29. ADC Input Equivalency .................................................................................... 1890



Figure 27-30. SSI Timing for TI Frame Format (FRF=01), Single Transfer TimingMeasurement .................................................................................................. 1892

Figure 27-31. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1892Figure 27-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1893Figure 27-33. I2C Timing ....................................................................................................... 1894Figure 27-34. MOSC Crystal Characteristics for Ethernet ........................................................ 1895Figure 27-35. Single-Ended MOSC Characteristics for Ethernet .............................................. 1896Figure 27-36. Reset Timing ................................................................................................... 1896Figure 27-37. 100 Base-TX Transmit Timing ........................................................................... 1897Figure 27-38. 10Base-TX Normal Link Pulse Timing ............................................................... 1897Figure 27-39. Auto-Negotiation Fast Link Pulse Timing ........................................................... 1898Figure 27-40. 100Base-TX Signal Detect Timing ..................................................................... 1898Figure 27-41. ULPI Interface Timing Diagram ......................................................................... 1900Figure A-1. Key to Part Numbers ........................................................................................ 1909Figure A-2. TM4C1294NCZAD 212-Ball BGA Package Diagram .......................................... 1911


Table of Contents

List of TablesTable 1. Revision History .................................................................................................. 45Table 2. Documentation Conventions ................................................................................ 49Table 1-1. TM4C1294NCZAD Microcontroller Features .......................................................... 52Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 85Table 2-2. Processor Register Map ....................................................................................... 86Table 2-3. PSR Register Combinations ................................................................................. 92Table 2-4. Memory Map ..................................................................................................... 103Table 2-5. Memory Access Behavior ................................................................................... 107Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 109Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 109Table 2-8. Exception Types ................................................................................................ 115Table 2-9. Interrupts .......................................................................................................... 116Table 2-10. Exception Return Behavior ................................................................................. 124Table 2-11. Faults ............................................................................................................... 125Table 2-12. Fault Status and Fault Address Registers ............................................................ 126Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 128Table 3-1. Core Peripheral Register Regions ....................................................................... 135Table 3-2. Memory Attributes Summary .............................................................................. 139Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 141Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 142Table 3-5. AP Bit Field Encoding ........................................................................................ 142Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 143Table 3-7. QNaN and SNaN Handling ................................................................................. 146Table 3-8. Peripherals Register Map ................................................................................... 147Table 3-9. Interrupt Priority Levels ...................................................................................... 172Table 3-10. Example SIZE Field Values ................................................................................ 200Table 4-1. JTAG_SWD_SWO Signals (212BGA) ................................................................. 209Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 211Table 4-3. JTAG Instruction Register Commands ................................................................. 217Table 5-1. System Control & Clocks Signals (212BGA) ........................................................ 221Table 5-2. Reset Sources ................................................................................................... 222Table 5-3. Clock Source Options ........................................................................................ 232Table 5-4. Clock Source State Following POR ..................................................................... 233Table 5-5. System Clock Frequency ................................................................................... 236Table 5-6. System Divisor Factors for fvco=480 MHz ............................................................ 238Table 5-7. Actual PLL Frequency ........................................................................................ 239Table 5-8. Peripheral Memory Power Control ...................................................................... 244Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 245Table 5-10. MOSC Configurations ........................................................................................ 248Table 5-11. System Control Register Map ............................................................................. 248Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 278Table 5-13. MOSC Configurations ........................................................................................ 282Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 301Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 304Table 5-16. Module Power Control ........................................................................................ 453Table 5-17. Module Power Control ........................................................................................ 455



Table 5-18. Module Power Control ........................................................................................ 458Table 5-19. Module Power Control ........................................................................................ 464Table 5-20. Module Power Control ........................................................................................ 466Table 5-21. Module Power Control ........................................................................................ 468Table 5-22. Module Power Control ........................................................................................ 470Table 5-23. Module Power Control ........................................................................................ 473Table 5-24. Module Power Control ........................................................................................ 475Table 5-25. Module Power Control ........................................................................................ 479Table 5-26. Module Power Control ........................................................................................ 481Table 5-27. Module Power Control ........................................................................................ 483Table 5-28. Module Power Control ........................................................................................ 485Table 5-29. Module Power Control ........................................................................................ 487Table 5-30. Module Power Control ........................................................................................ 489Table 5-31. Module Power Control ........................................................................................ 491Table 5-32. Module Power Control ........................................................................................ 493Table 5-33. Module Power Control ........................................................................................ 495Table 5-34. Module Power Control ........................................................................................ 497Table 6-1. System Exception Register Map ......................................................................... 527Table 7-1. Hibernate Signals (212BGA) ............................................