TINY ENCRYPTION ALGORITHM FOR RFID APPLICATIONS

ABSTRACT

Embedded hardware security has been an increasingly important need for many modern general and specific purposes electronic systems. Minute security algorithms with their expected low-cost and high-speed corresponding hardware realizations are of particular interest to fields such as mobile telecommunications, handheld computing devices, etc. In this paper, we analyze and evaluate the development of a cheap and relatively fast hardware implementation of the tiny encryption algorithm (TEA). The development will start by modeling the system using finite state machines (FSMs) and will use Verilog hardware description language to describe the design. Minimizing the chip area will be our primary target rather than the construction of a multi-way massively parallel implementation with its expected high-speed and large silicon area. Many hardware design tools are used to try reaching the best possible optimized syntheses. The targeted hardware systems are the reconfigurable Xilinx Spartan 3e modern field programmable gate arrays (FPGAs).

The Tiny Encryption Algorithm (TEA) is a suitable lightweight cryptographic algorithm used in medium security systems such as RFID systems. The TEA is a fiestel structure used to satisfy the confusion and the diffusion properties to hide the statistical characteristics of the plaintext.

OBJECTIVES: Program the Tiny Encryption Algorithm (TEA) using verilog HDL (Hardware Description Language) Verifying the functionality of the implementation of the encryption in FPGA Perform simulation for timing analysis and the encryption process on the implementation of Tiny Encryption Algorithm (TEA) in FPGA Experiment and test the project in practice Explore other tools for simulating or verifying designs like Matlab, Labview etc.Implementation using Hardware:Implementation of encryption using hardware by naturally is physically more secure as they are hard to read and view by attacker. Another advantage of hardware implementation is all the data in the encryption process is correlated according to an algorithm which usually perform operation on same data. This will prevent computer technique such as out of order execution and cause hang to the system. Hardware implementation also tend to be more parallel so more orders of magnitudes can be done at certain period of time. Considering the benefits of a hardware implementation of the encryption scheme, we plan to implement TEA on FPGAs.