Time scale matching of dynamically operated devicesusing composite thermal capacitors

Craig E. Green, Andrei G. Fedorov n, Yogendra K. JoshiGeorge W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405, United States

a r t i c l e i n f o

Article history:Received 22 November 2013Received in revised form14 May 2014Accepted 19 May 2014

Keywords:MulticoreHotspotCore migrationThermalPulsed RFComputational sprinting

a b s t r a c t

A new thermal management solution is proposed to maximize the performance of electronics deviceswith dynamically managed power profiles. To mitigate the non-uniformities in chip temperature profilesresulting from the dynamic power maps, solid–liquid phase change materials (PCMs) with an embeddedheat spreader network are strategically positioned near localized hotspots, resulting in a large increase inthe local thermal capacitance in these problematic areas. The resulting device, called composite thermalcapacitor (CTC), can theoretically produce an up-to-twenty-fold increase in the time that a thermallyconstrained high heat flux device can operate before a power gating or core migration event is required.A prototype CTC that monolithically integrates micro heaters, PCMs and a spreader matrix into a Si testchip was fabricated and experimentally tested to validate the efficacy of the concept and to gain aninsight into phase change heat transfer in a spatially-confined environment on the microscale. As themost significant result, an increase in allowable device operating times by over 7� has beenexperimentally demonstrated, while operating a device at heat fluxes approaching 400 W/cm2.

& 2014 Elsevier Ltd. All rights reserved.

1. Introduction

Dynamic operation and control is an essential tool for thethermal management of a number of next generation electronicdevices that suffer from localized hotspots with large heat fluxesthat cannot be dissipated by the baseline cooling system designedfor dissipation of the time-averaged power load. Examples of suchdevices with pulsed or time varying power loads include (i) RFtransmitters, which generate heat in short, periodic, pulses duringthe data transmission process; (ii) power electronics, which useshort modulated voltage pulses to perform tasks such as conversionof power from direct to alternating current; and (iii) many-coremicroprocessors, which use techniques such as thread migration toactively move high power consumption computations from hotter tocooler areas of the die to lower peak temperatures and temperaturegradients.

Due to limited baseline cooling resources, the time that manyhigh heat flux devices can operate before load mitigation appro-aches must be employed is limited. In some cases, such as datatransmitters, the dynamic operation of the device is coupled to itsfunctionality, while in others (e.g. microprocessors) the dynamicarchitecture is driven by thermal limitations. Both types of systemscan benefit from a thermal solution that is specifically geared

towards addressing the dynamic nature of the devices' heatgeneration.

For applications where the duration of the operational pulse isintegral to the device's functionality, it is imperative that thecomponent is able to operate for the entire pulse without exceed-ing temperature limits. Radar systems, for example, transmit andreceive data in high power pulses that can exceed several kW/cm2

[1] and in some cases must operate in thermally challengingenvironments such as outer space or unmanned aerial vehicles[2]. While the transmitters' power consumption during transmis-sion can be large, their duty cycles – the fraction of time when thedevice is actively consuming power – are typically less than about25% [3]. In power electronics, extremely large voltages (sometimeskV) are switched at varying pulse lengths using the pulse widthmodulation technique in order to convert the electrical signal tothe desired output [4]. The heat flux associated with these switch-ing events can also be several kW/cm2 on time scales ranging fromms to hundreds of ms [5,6].

The exponential growth in the number of on chip transistors soreliably predicted by Moore's law has proven to be a powerfuldriver for increases in computing performance over the past40 years, although limitations associated with wire delay [7],power consumption, and heat generation [8] have recently becomesignificant challenges to traditional transistor scaling. The desire tomaintain the historic rate of advancement in the microelectronicsindustry, while avoiding the roadblocks associated with powerconsumption and wire delay have led to the consideration of

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Microelectronics Journal

http://dx.doi.org/10.1016/j.mejo.2014.05.0130026-2692/& 2014 Elsevier Ltd. All rights reserved.

n Corresponding author. Tel.: þ1 404 385 1356.E-mail addresses: AGF@gatech.edu, cgreen8@gatech.edu (A. G. Fedorov).

Microelectronics Journal 45 (2014) 1069–1078

several disruptive design strategies for next generation devices,including many-core processors and 3D vertical integration [9,10].

In a many-core system, the thermal profile across the chip canbe made more uniform by actively migrating computations fromhotter to cooler areas of the chip, reducing the problem oflocalized hotspots that have become a major challenge in modernarchitectures [11]. While this Dynamic Core Migration (DCM)scheme can mitigate hotspots for most cores, serial cores withtheir potentially higher power densities, larger size, and smallernumber may still experience hotspots [12]. To compensate for thehigher power densities the serial cores will either experience morethrottling events during an intra-migration time slice [13], highermigration frequencies, or a dedicated local hotspot cooling solu-tion would be required to handle the additional thermal over-head [14]. In DCM schemes, there is parasitic computational costassociated with each throttling event that can become significantover time when the cycling is too rapid [15]. Furthermore, rapidthermal cycling can lead to reduced lifetime reliability for thechip [16]. To minimize the performance losses associated withthese gating and throttling events, an optimized system should bedesigned that can operate for longer periods without requiring anidle for cool-down, and have as short of an idle time as possible.

2. Proposed cooling method

A commonly used approach to handle hot spots is to bring anembedded liquid cooler to the hotspot, to locally enhance heattransfer. Such dedicated hotspot coolers can significantly increasethe complexity of the overall thermal solution, often requiring addi-tional coolants, piping, or off chip regeneration [17,18]. Furthermore,hotspot coolers are often steady state solutions, as operating a liquidcooler in a dynamic fashion requires the use of valves or other activeflow control measures to synchronize the coolant delivery with theoperation of the electronic device. Recognizing these challenges ofattempting to locally increase a cooler's heat transfer coefficient, theapproach investigated in this work instead seeks to locally increasethe thermal capacitance in thermally troublesome areas of the chip tomaximize the time that a core or device can operate before reachingits thermal threshold.

As shown schematically in Fig. 1, for dynamically operatedelectronics, increasing the thermal capacitance of a device cansignificantly decrease the frequency of core hopping, gating, orthrottling events. This in turn reduces the parasitic computationaloverhead associated with the DCM implementation. Thus, match-ing a device's thermal capacitance to its intrinsic dynamics ofpower dissipation can “homogenize” the thermal time scales ofdevices with very different power dissipation profiles. Further-more, for high power devices with defined pulse lengths such as

RF electronics, a sufficiently large increase in local thermal capaci-tance can ensure that the device can operate for its entire pulsewithout exceeding its temperature limits.

In order to locally alter the thermal capacitance of the devices,a portion of the substrate (Si, SiC, etc.) on the inactive back side ofthe chips can be etched away and a material with a higher thermalcapacitance, for example solid–liquid phase change materials(PCMs), can be placed in the cavity created by removal of substratematerial. An embodiment of this approach is shown schematicallyin Fig. 2, where PCMs have been inserted into the inactive backside of several dies in a 3D chip stack. The PCMs, named because oftheir ability to reversibly melt/solidify during heating/coolingprocesses, can absorb a large amount of thermal energy at arelatively constant temperature. One challenge of utilizing PCMs isthat their typically low thermal conductivities (κ) limit the amountof material that can be melted prior to the device reachingits threshold temperature due to significant temperature non-uniformity. This can be mitigated by using a “composite thermalcapacitor” (CTC), consisting of PCM incorporated into a highthermal conductivity matrix to enhance heat spreading and there-fore improve PCM utilization. The CTC can be manufactured usingstandard batch microfabrication techniques, making the proposedsolution amenable to the level of high volume integration that isneeded for devices in the consumer electronics market.

3. Performance characterization

3.1. Analysis of the impact of spreading on device operating timemodulation

A key feature of the CTC design philosophy is the enhancementof lateral spreading and energy storage into the PCM by improvingthe effective thermophysical properties, specifically the effectivethermal conductivity (κeff) of the composite matrix. It is valuable tofirst examine how κeff, along with the other relevant PCM proper-ties – density (ρ), specific heat (cp), and latent heat of solid toliquid phase change (hsl) – affect the physics of the problem and, inturn, the achievable device operating times. Concentrating on thecontribution of lateral spreading to the achievable enhancementsin device operating times will allow a more informed decision onwhether design of the overall CTC should focus just on the areadirectly above the hotspot, or on using a larger cross-sectional areaaccessible through thermal spreading.

A simple model that can be used to study the impact of lateralspreading on device operating times is an annular region of PCMsurrounding a cylindrical block of Si of radius RSi, and height z, asshown in Fig. 3. At the bottom of the Si region is a heat fluxboundary condition that represents a localized hotspot. Becausethe PCM is confined to the annular region at the periphery of thehotspot, this arrangement highlights what can be gained fromlateral spreading specifically.Fig. 1. Impact of increased thermal capacitance on core hopping frequency.

Fig. 2. Schematic of CTC integration in a 3D chip stack.

C. E. Green et al. / Microelectronics Journal 45 (2014) 1069–10781070

If the domain is thermally thin such that gradients in thevertical direction can be neglected, it can be modeled as 1-D and inthe Si region the transient heat conduction equation with a sourcedue to heat injection at the hot spot can be written in cylindricalcoordinates, along with the appropriate boundary conditions, asfollows:

κSir

∂∂r

r∂T∂r

� �þ _Eg ¼ ρSicSi

∂T∂t

0oroRSi t40 ð1Þ

κSi∂T∂r

¼ 0 ðr¼ 0; tÞ ð2Þ

TðRSi0 tÞ ¼ TRSi ðtÞ ð3ÞHere _Eg represents the equivalent volumetric heat generation fromthe hotspot ð _Eg;Si ¼ q″hs=zÞ and TRSi ðtÞ is the temperature at RSi0 theboundary between the Si and PCM regions.

From inspection one can deduce the limiting scenarios for CTCperformance with respect to the relative loading of the PCM andcontribution of laterally-conducting heat spreader matrix. In thecase of a poorly designed PCM, no energy can be stored in it andthe boundary condition Eq. (3) would be changed to an adiabaticcondition – ∂T=∂rr ¼ RSi ¼ 0. In the best case scenario, the PCMwould require no wall superheat above Tmelt in order to drive themelting process. In this case, the boundary condition Eq. (3) wouldbe changed to a constant temperature boundary condition –

TðRSi; tÞ ¼ Tmelt .In the PCM region, the governing energy conservation equation

and boundary conditions are:

κPCMr

∂∂r

r∂T∂r

� �¼ ρPCMcp;PCM

∂T∂t

RSioroRðtÞ; t40 ð4Þ

�κPCM∂T∂r r ¼ RSi

¼ q″PCM ð5Þ

TðRðtÞ; tÞ ¼ Tmelt ð6Þwith the location of the melt front is determined from thecontinuity of the heat flux at the melting front:

ρPCMhsl∂∂tðRðtÞÞ ¼ �κPCM

∂T∂r r ¼ RðtÞ �

ð7Þ

Rðt ¼ 0Þ ¼RSi ð8ÞHere q″PCM is the heat flux at the Si–PCM interface, which drivesthe melting process and RðtÞ is the location of the melt front.The entire domain, both Si and PCM, are initially at the sametemperature:

Tðr;0Þ ¼ Tmelt ð9ÞThe melting problem described by Eqs. (1)–(9) above fall into

a class of problems called Stefan problems which involve heattransfer or diffusion with a moving boundary [19]. The movingboundary in this problem, the melt front propagating radially

away from the Si–PCM interface, introduces a non-linearity intoEq. (4) that precludes the development of an analytical solution.

In order to simplify the problem and allow an approximateanalytical solution, one may observe that in many problemsinvolving melting, the rate of melt front propagation is muchslower than the diffusion time scale. In these instances theproblem is dominated by this melt front propagation time scaleand as a result a quasi-steady approximation can be justified in thesingle-phase region behind the melt front [20].

The quasi-steady approximation involves dropping the transi-ent term in Eq. (4), which after solving results in a temperaturedistribution in the melt, and melt front position of Ref. [20]

Tðr; tÞ � Tmelt�q″PCMRSi

κPCMln

rRðtÞ

� �RSirroRðtÞ ð10Þ

RðtÞ �ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiR2Siþ

2RSiq″PCMρPCMhsl

sð11Þ

Substituting the expression for RðtÞ into Eq. (10) yields:

TRSi � Tmeltþq″PCMRSi

2κPCMln

2q″PCMtRSiρPCMhsl

þ1� �

ð12Þ

For small values of 2q″PCMt=RSiρPCMhsl, lnð2q″PCMt=RSiρPCMhslÞþ1 can be approximated by �ð2q″PCMt=RSiρPCMhslÞ. This simplifica-tion helps to highlight the inverse relationship of temperaturewith the PCM properties κPCMρPCM hsl.

The quasi stationary approximation neglects the unsteady termin Eq. (4), and thus neglects any energy storage due to sensibleheating, which for the approximation to be valid, should besmall relative to the energy storage due to phase change. TheStefan number St ¼ hsl=cpΔT where ΔT is the wall superheat, e.g.TRSi �Tmelt , compares the relative contributions of latent andsensible heating in the problem. When St is large, the quasistationary approximation is valid. From Eq. (12) the time scalefor melting is τmelt � ðRSiρPCMhsl=q

″PCMÞ; while the diffusion time

scale is τdif f usion �R2Si=ðκ=ρcpÞPCM . Considering the melt front

propagation rate argument that initially motivated the approx-imation, in order for the melt front propagation rate to be muchslower than the diffusion rate, τmeltcτdif f usion. Comparing the twotime scales, τmelt=τdif f usion ¼ κPCMhsl=cpq″PCMRSi, again recovers alarge St requirement where q″PCMRSi=κPCM represents the tempera-ture difference.

A simplified solution to Eq. (1) is desirable in order to elucidatethe qualitative impact of spreading into the melt on the Si (hotspot) temperature. Excepting the early regime (small values ofFo¼ t=τdif f usion), when τdif f usion;Si{τmelt the time dependence of thetemperature in the solid at any point within its interior is the sameas the time dependence of the wall temperature which is definedby Eq. (12) [21]. The temperature distribution within the Si can beestimated from the steady state solution to Eq. (1) with thetemperature boundary condition given by Eq. (12):

TSiðr; tÞ �_Eqsg

4κSiðR2

Si�r2ÞþTRSi ð13Þ

Here, _Eqsg , which determines the slope of the temperature increase

from the Si-PCM interface (TRSi ) to the temperature at the hotspot,is: _E

qsg ¼ 2q″PCM=RSi . The implication of this relationship is that in

the limit of τdif f usion;Si{τmelt , the temperature distribution withinthe solid can be estimated by a quasi-steady state temperaturedistribution governed by the rate of energy storage within the Si,which dramatically simplifies the analysis and thermal designof CTC.

Fig. 3. Schematic of the physical arrangement for cylindrical thermal spreading/melting analysis.

C. E. Green et al. / Microelectronics Journal 45 (2014) 1069–1078 1071

In order to complete the analysis, an estimate must be obtainedfor q″PCM . An energy balance on the Si yields

ρSicSi∂T∂t

¼ q″hsZ �2q″PCM

RSið14Þ

Then ∂T=∂t can be estimated from ∂TRSi=∂t (holding q″PCMconstant) to yield

ρSicSiq″PCM

2 RSi

κPCMð2q″PCMtþRSiρPCMhslÞþ2q″PCM

RSi�q″hs

Z ¼ 0 ð15Þ

which is a quadratic equation in terms of q″PCM that can be solveddirectly

q″PCM ¼RSiκPCMðq″hst�ρPCMhslZÞZðρSicSiRSi

2þ4κPCMtÞþ…

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiR2

SiκPCMðρSicSiR2SiρPCMhslZq″hsþκPCMðq″hstþρPCMhslZÞ2Þ

qZðρSicSiR2

Siþ4κPCMtÞð16Þ

While the simplified analysis described above is useful forhighlighting some of the important relationships governing theimpact of lateral spreading on the device operating times, it onlyprovides an approximate representation of the overall tempera-ture history during the heating/melting cycle. Furthermore, thereare some rather strict assumptions, such as the large St require-ment, that must be satisfied for the analysis to be valid. To providea point of comparison for the results of the simplified analysis, aswell as to study the behavior of materials that fall outside of itsrange of validity, a more detailed numerical model of the processhas been developed to study the CTC behavior under the mostrealistic conditions expected in applications.

A cylindrical computational domain, shown schematically inFig. 3, has been constructed for a numerical study of the influenceof the relevant thermophysical properties of the CTC's PCM–solidmatrix composite on electronic device thermal performance. Thecomputational domain is axisymmetric about the z-axis and the Siblock has dimensions RSi ¼ 500 μm; Z ¼ 150 μm, and D¼ 1:5 mm.It is heated from below by a q″hs ¼ 500 W=cm2 heat flux. Surround-ing the Si block is a donut-shaped region of PCM considered tohave a range of possible values of effective thermophysical proper-ties, ρ, cp, hsl, and κ shown in Table 1.

Except for the hotspot, the remaining external boundaries ofthe system are considered adiabatic, representing for example, adevice embedded in a 3D stack with a large thermal resistancebetween the device and the global heat sink. This completethermal isolation condition (the worst case scenario) will berelaxed later in the analysis, but it serves as an appropriate startingpoint to best illuminate the fundamentals of the local thermalcapacitance enhancement process before the added complexity ofthe packaging and integration related thermal inputs are includedin a more comprehensive analysis.

The entire domain is initially set at the solid liquid-transitiontemperature Tsolidus when the 500 W/cm2 hotspot is activated att¼0. When the maximum allowable (throttling) temperatureTthrottle is reached, the device will be have to be throttledor shut-off to allow it to cool down. The generality of the ana-lysis is achieved by tracking the dimensionless temperature

θ¼ ððT�TsolidusÞ=ðTthrottle�TsolidusÞÞ instead of the dimensional tem-peratures, as the specific values of Tsolidus do not affect thedynamics (time constant) of the heating process. Instead, onlythe temperature budget ðTthrottle�TsolidusÞ – determined by theapplication – is needed. For this analysis, a temperature budgetof 15 1C is assumed.

Melting of the PCM is accounted for by incorporating amodified enthalpy term in the transient heat conduction equation,as described in [22].

∂ðρHÞ∂t

¼∇ðκ∇TÞþ _Eg0 ð17Þ

The modified enthalpy term H, defined as ¼ hþΔH, accountsfor both sensible and latent heating. Here the sensible enthalpy, h,and latent heat ΔH respectively are given by: h¼ href þ

R TTref

cpd T ,and ΔH¼ βhf s. In the preceeding equations, href is the enthalpy atthe reference temperature Tref , cp is the constant pressure specificheat of the material, hf s is the latent heat of solidification and β isthe local liquid fraction, defined as: β¼ T�Tsolidus=Tliquidus�Tsolidus.

For eutectic materials that melt and solidify at a singletemperature, the β term is undefined at the melting temperature,so a “mushy zone” approximation is made to allow for solution ofEq. (17). The mushy zone approximation assumes the meltingprocess occurs over a range as opposed to a single temperature,beginning at Tsolidus and completing at Tliquidus, and vice versa forthe solidification process. For the remainder of this investigation asmall ðTliquidus�TsolidusÞ ¼ 0:1 1C mushy zone is assumed to aid inthe convergence of the numerical simulation.

3.2. Two-dimensional model for CTC performance evaluation

To evaluate the potential effectiveness of creating a compositePCM-high k matrix CTC to maximize both the energy storagecapacity and device operating times, the performance of a CTC thatuses an azimuthal array of diamond shaped loops of either Cu orCVD diamond as a heat spreader matrix (Fig. 4) has been modeled[23]. The voids between the loops are filled with a PCM withproperties of typical of Bi–In–Sn based alloys with an assumed60 1C melting temperature. The properties of the PCM as wellas the Cu and CVD diamond spreaders used in the model are listedin Table 2.

The diamond shaped loop arrangement for the high thermalconductivity material was first studied by Rocha et al., whichshowed that this type of layout is effective at enhancing steadystate heat conduction in a volume containing two solid materialswith differing values of thermal conductivity [24]. The layoutwas biologically inspired by the venation patterns of leavesin nature. While a more involved optimization following for

Table 1Thermophysical properties evaluated for cylindricalspreading investigation.

Property Value range

κ 1–100 W/m Kcp 1 kJ/kg Khsl 1–500 kJ/kgρ 100-10,000 kg/m3

Fig. 4. Schematic of 2D computational domain for CTC performance analysis. (Forinterpretation of the references to color in this figure, the reader is referred to theweb version of this article.)

C. E. Green et al. / Microelectronics Journal 45 (2014) 1069–10781072

example, the constructal theory put forth in [24,25], might includeconsideration of varying numbers of loops or irregularly shapedbranching structures, this geometry consisting of eight diamondshaped loops was chosen as a design constraint, in order to limitthe computational cost associated with the investigation. Eightloops were chosen to align with the inherent symmetry of theproblem.

The size of the regular octagonal computational domain shownin Fig. 4 is set to fit within a circumscribed 3 mm diameter circle.This limitation on the maximum allowable size of the CTC is set toensure that it does not monopolize an impractical amount ofvaluable real estate in the bulk Si, which may also be needed forthrough-layer interconnect routing in 3D chip applications [26].The high thermal conductivity materials are laid out in a rhombusshaped region with 451 and 1351 internal angles as shown in Fig. 4.

To simulate the process of activating a high power electronicdevice and storing the energy in the PCM the energy conservationEq. (17) is solved within a planar (thickness-averaged) CTCcomputational domain with the dimensions shown in Fig. 4. Thesource term _Eg in Eq. (17) that accounts for the heat generation atthe 1 mm�1 mm square hotspot (red region in Fig. 4) is assumedto be uniformly distributed in the vertical (across the CTC layer)direction. In practice, the heat generation only occurs in a thinlayer on the active side of the chip, so this approximation is onlyvalid in the limit of thin PCM layers with high effective thermalconductivity across the plane, such that temperature gradients inthe vertical direction are negligible.

The outer boundaries of the computational domain are consid-ered adiabatic, and the volumetric heat generation in the hotspotdomain is taken as 33 W=mm3 corresponding to a 500 W=cm2

hotspot under a 150 μm thick CTC, in line with projected peak heatfluxes in future devices [14]. For each configuration analyzed, thechips starts at an initially uniform temperature of 59 1C and thesimulations are run until the junction temperature reaches 90 1C.

Because of the simplifying assumptions included in this model,such as complete isolation from any external heat sink, neglectingtemperature gradients in the vertical direction, and large allow-able temperature swings (up to 30 1C), this portion of the analysisprovides an understanding of what best case potential operatingtime enhancements can be achieved with this combined PCM/highκ material CTC design.

3.3. Grid and convergence study

The mathematical models described in the previous sectionswere solved numerically using FLUENT software. In the case ofSi-PCM (i.e., no spreader analysis) shown in Fig. 3, a computationaldomain with 13,799 quadrilateral cells was used as a baseline, andgrid independence of the solution was evaluated by increasing thenumber of cells in the computational domain by a factor of four to55,196 cells. When comparing the refined and unrefined cases,there was o1% difference in the predicted operating times beforereaching the throttle temperature for the two cases considered.A criterion of scaled energy equation residuals o1� 10�10 on

the standard grid size was used to indicate convergence of thenumerical solution. A reduction of the convergence criterion toresiduals o1� 10�11 resulted in a o1% difference in the pre-dicted allowable operating times before reaching the throttletemperature.

For the CTC with the composite high-k matrix/PCM shown inFig. 4, grid size and residual convergence of the numericalsimulations were tested using a PCM fraction of 95%. The baselinegrid size in the test case contained 5998 cells. The grid was thenrefined near all interfaces and boundaries, resulting in a refinedgrid with 8185 cells. A o1% difference in allowable operatingtimes was predicted using the refined and standard grid sizes. Thescaled energy residuals were found to be converged to the valueof 3� 10�8 with temperature deviations of o1% with furtherreduction in residuals.

4. Experimental characterization

4.1. Device fabrication

In order to validate the potential of the CTC concept forenhancing device operating times, several prototype devices havebeen fabricated and tested [27]. Each device featured a mono-lithically integrated thin film platinum heater (used to simulatedlarge heat flux electronic device) and a CTC formed by a siliconmatrix filled with a solder alloy as a PCM (Fig. 5). Monolithicintegration of the CTC device and a heat source with a single Siwafer was essential to eliminate any contact resistances associatedwith bonding of different layers, which would mask an intrinsicbehavior of the CTC device as it would have been implemented inactual applications.

The prototype device was fabricated on a 500 μm thick double-side polished wafer with the simulated hotspot built on one sideatop a thin SiO2 passivation layer. The 1 mm�1 mm square hotspotresistor heater, surrounded by an array of 250 μm�250 μm tem-perature sensors shown in Fig. 6a, were fabricated using a micro-fabrication process similar to that described in [28]. The heater andsensors were made of �250 nm thick Pt films deposited on a�25 nm Ti adhesion layer. Platinumwas chosen because of its linearresistivity vs temperature dependence, allowing the devices to act asresistance temperature detectors (RTDs). The smaller RTDs thatsurrounded the heater shown in Fig. 6a were not used in this study.

To form the cavities for PCM loading, the CTC sidewalls wereetched into the back side of the wafer using an ICP-RIE process.The wafer was then thinned to 300 μm such that the final devicehas a 190 μm deep CTC on top of a 110 μm thick base. The CTCdevices that were fabricated had a diameter of 2 mm and PCMfractions of 50%, 60% and 70%. An additional CTC with 3 mmdiameter and PCM fraction of 50% was tested as well. Opticalmicrographs of a representative sample of each device are shownin Fig. 7.

Table 2Properties used in simulations for CTC design analysis.

Material ρ

kg=m3� � cp

J=kg 1C� � κ

W=m 1C� � hsl

J=kg� � Tliquidus

½1C�Tsolidus

½1C�

Cu 8940 386 400CVD diamond 3500 509 1800PCM 9570 123 40 32500 60 60.1

Fig. 5. Schematic of the experimental setup used for CTC proof-of-conceptdemonstration.

C. E. Green et al. / Microelectronics Journal 45 (2014) 1069–1078 1073

The PCM used in the experiments was alloy – 136, a eutecticalloy of Bi0:49In0:21Pb0:18Sn0:12 with a 58 1C melting temperature.A 1 μm thick layer of Pt was sputtered on the CTC structures toimprove its wetting characteristics. Platinum was chosen for thesidewall coating because it typically does not form or tightlyadhere to surface oxides which lowers the surface energy andreduces wetting. Unlike other noble metals such as Au or Ag, Ptalso has an extremely low dissolution rate in most solderalloys, which is important to the long term stability of the PCM[29,30]. The major CTC fabrication steps are shown schematicallyin Fig. 8.

4.2. Experimental procedure

A typical experimental procedure consisted of the followingsteps. An unaltered Si chip of an equivalent size was usedas a control device for comparison to the CTC performance.The control device was a 300 μm thick Si test chip with heaterson one side and no alterations on the back side. To calibrate theheaters the test chips were heated in an oven and the tempera-tures and corresponding resistances were measured over a broadrange relevant to subsequent experimental conditions. The result-ing temperature vs resistance calibration curves were used todetermine the temperature histories of the test devices duringoperation.

The prototype devices were then preheated in a 51 1C oven tosimulate a steady-state baseline heating due to background heatdissipation. The hotspots were then activated for short pulses,ranging from �300 W/cm2 to �395 W/cm2. To simulate a veryrapid heating during the pulsed operation, the resistor heaters ofthe test structures were connected to the test circuit shown inFig. 9. The power through the circuit was supplied by a DC powersupply. A NPN type transistor was used as a switch to open andclose the circuit downstream of the test device. The base currentproviding the switching operation of the transistor was suppliedby a waveform generator, which sends square pulses of the widthof the activation time to the device. The edges of the square waveswere set at 5 ns ramp time.

The 82 kΩ bypass resistor, R3, shown in the circuit was put inplace to allow the power supply to remain at its target voltage

Fig. 6. Optical micrograph of simulated test chips with integrated CTC: (a) top sideof chip with hotspot heater and resistive temperature sensors and (b) back side ofchip with CTC spreader matrix filled with phase change material.

Fig. 7. Optical micrographs of 2 mm CTC cavities in Si: 50%, 60%, 70% PCM fraction (from left to right).

Fig. 8. Schematic of main process steps for fabricating the CTC in a Si substrate.

C. E. Green et al. / Microelectronics Journal 45 (2014) 1069–10781074

with a small amount of current flowing when the test deviceportion of the circuit is open, thus removing the intrinsic ramptime of the power supply from the temporal response of the maincircuit, which corresponds to the thermal transients. The sensingresistor, R2, was a calibrated 53.5Ω resistor. The voltage dropacross R2 was measured as a function of time using an oscilloscopein order to determine the change in current flow through thecircuit as the test device heats up. This change in current wasrelated to the temperature dependent change in resistance of thePt heater in the test device. The small 1.4Ω resistor R1 simplyprovided a small load for the waveform generator to ensure it didnot exceed its current rating when the transistor circuit wasclosed.

With the current and voltage drop across the device known, theresistance of the test device was determined using Ohm's law,and compared to its calibration curve in order to determine itstemperature history throughout the transient. Because of theinherent noise in the measurement circuit, each data point istaken as the average value measured over 16 identical pulses,executed sequentially with 300 s between each pulse to ensure thedevice has sufficient time to be fully regenerated before activatingthe next pulse.

4.3. Uncertainty analysis

Measurement uncertainty was determined using an errorpropagation analysis [31]. Using the RTD method the measure-ment uncertainty is dependent upon two uncorrelated uncertain-ties: the uncertainty in determining the resistance of the testdevice, and the uncertainty associated with the temperature vsresistance calibration of the test devices.

The test device resistance, Rtest, is dependent upon threemeasurements: the voltage drop across the test device Vtest, thevoltage drop across the sensing resistor Vsense, and the resistance ofR2 (Fig. 9). Vtest was determined from the difference between thevoltage at the positive terminal of the power supply Vtotal and theupstream terminal of R2 (see Fig. 9). With the negative terminal ofthe power supply grounded, the expression for determining Rtestcan be written as follows: Rtest ¼ Vtest=Itest ¼ ðVtotal�VsenseÞ=ðVsense=R2Þ: The total uncertainty can then be computed from

ΔRtest=Rtest ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiðΔVtest=VtestÞ2þðΔItest=ItestÞ2

qwhere the individual

components are

ΔVtest

Vtest¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiΔV2

totalþΔV2sense

qVtotal�Vsense

ð18Þ

and

ΔItestItest

¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiΔR2

R2

� �2

þ ΔVsense

Vsense

� �2s

ð19Þ

In Eq. (19) ðΔR2Þ=R2 is the uncertainty of the sensing resistor,which is calibrated by the manufacturer to be accurate within(71%).ΔVtotal can be determined from the uncertainty of thepower supply ΔVtotal=Vtotal�0.1% [32], and ΔVsense can be deter-mined from the uncertainty of the oscilloscope measurement(ΔVsense=Vsense � 3%) [33].

Nonlinearity was found to be negligible in the temperature vsresistance calibration, with R2 values 40.99. Thus the uncertaintyin the temperature vs resistance calibration curve is dominatedby the 70.5 1C uncertainty of the thermocouple reference usedduring the heater calibration.

5. Results and discussion

5.1. Spreading impact analysis

Fig. 10 compares the two limiting cases determined analyticallyin Section 3.1 (i.e., the adiabatic boundary condition for poorlyperforming PCMs and constant temperature boundary conditionfor ideal PCMs) to the results of numerical simulations. Each of therelevant thermophysical properties of the PCM has some ability tomove the performance of the PCM towards one of the extremes.Recalling that the wall superheat in the expression for St in Section3.1 scales with � q″PCMRSi=κPCM , one sees that if thermal conduc-tivity κ is small relative to the heat flux q″PCM , the PCM behaves asan insulator due to the large temperature gradient needed to drivethe melt front. Similarly if ρ or hsl is small relative to the heat flux,the PCM has little capacity to store heat minimizing the meltingtime scale τmelt �RSiρPCMhsl=q″PCM , again moving the PCM perfor-mance towards the adiabatic limit. At the other extreme, if thedensity or latent heat is infinitely large, the melt front will nevermove from the Si/PCM interface, thus the problem reduces to theheating of the Si block with a constant temperature boundarycondition at its periphery. At somewhat smaller values of ρ or hsl,the device can still operate near the constant temperature limit ifκ-1, because negligible temperature gradient will be required todrive the melt front. In the scenarios considered, an enhancementin operating time through spreading of �2� can be achieved by

Fig. 9. Electric diagram of CTC test device circuit used for rapid pulsed heatingactuation.

Fig. 10. Limits on achievable device operating times through spreading into a PCMalone for hsl¼100 kJ/kg and cp¼1 kJ/kg 1C.

C. E. Green et al. / Microelectronics Journal 45 (2014) 1069–1078 1075

moving from PCMs that operate near the adiabatic limits to PCMcomposites that operate near the constant temperature limit.However, this is dependent on the allowable temperature budget,Tthrottle�Tmelt. At larger allowable gradients the achievable gainswould be significantly larger as the adiabatic and constant tem-perature curves diverge further from one another.

The results of the numerical simulations shown in Fig. 10compare PCMs with intermediate Stefan number St ¼ 20=3 tothese limiting cases. PCMs with small effective ðκρÞ combinationsapproach the adiabatic boundary condition limit, while at κ¼100 W/m 1C, ρ¼10,000 kg/m3, the temperature history is almostidentical to that of the constant interface temperature case for thevalues of Fourier number Fo (dimensionless time) considered. Overlonger times the large ðκρÞ case would diverge from the constantinterface temperature case as the melt front moved further awayfrom the Si/PCM interface. This observed in simulation ðκρÞrelationship (holding hsl constant) follows the predicted trendsapproximated by Eq. (12).

Also shown in Fig. 10 is a comparison of the predictions of thequasi-steady analytical model to the results of the numericalsolution for hsl¼100 kJ/kg and cp¼1 kJ/kg 1C ðSt ¼ 20=3Þ. At thisvalue of St, the quasi-steady (qs) model has reasonable agreementwith the numerical solution in the later part of the transient. In theearly time regime, (Foo�0.2) the solutions converge as thethermal wave propagates across the Si block and the propertiesof the PCM have little impact. However in the regime wherethe quasi-steady model is applicable (i.e. large St, and Fo4�0.2)the reduced order model gives good insight into how the effectiveproperties of the PCM affect the achievable device operating times.

Fig. 11 shows the influence of thermal conductivity κ anddensity ρ on the temperature histories for hsl¼100 kJ/kg andcp¼1 kJ/kg 1C. Improvements in device operating times can beachieved through increases in κ, ρ or both. The strength of theforcing for each parameter is similar for both κ and ρ such thatconfigurations with the same value of product ðκρÞ have similartemperature histories, and associated operating times. Althoughthe time to reach the threshold and dimensionless temperaturetransient are similar regardless whether κ and ρ are increased bythe same amount, there are significant differences in other aspects.That is increasing κ reduces the magnitude of the thermal gradientneeded to drive the melt front a given distance R, whereasincreasing ρ reduces the distance that the melt front travels fora given amount of energy absorbed.

Considering constant values of effective κ, ρ and cp (κ¼10W/m 1C, ρ¼10,000 kg/m3, cp¼1 kJ/kg 1C) Fig. 12 shows the effect of

varying the Stefan number on device performance by changing themagnitude of the latent heat of melting. The device operating timesincrease with increasing hsl, although diminishing returns are ulti-mately observed as hsl becomes sufficiently large. The effect ofmodulating hsl, is analogous to that of density ρ – changing theamount of energy stored in a given volume of PCM – although ρ has alarger forcing due to its impact on both sensible and latent energystorage.

While RSi was not varied parametrically in the numericalanalysis, much larger gains in operating times could be achievedwith smaller hotspot sizes without increasing the allowabletemperature budget Tthrottle�Tmelt. The temperature differencebetween the center of the hotspot where Tthrottle is observed andthe Si/PCM interface scales with R2

Si. Because it is the interfacetemperature that drives the melt front, smaller hotspot sizeswould reduce the excess temperature between Tthrottle and Tinterfaceallowing more energy storage in the PCM before the throttletemperature is reached.

5.2. PCM-spreader composite optimization

As shown in Fig. 13, there is a significant potential for extendingthe device operating time before throttling/hopping is requiredwith the use of CTC. When compared with the baseline case of

Fig. 11. Impact of effective thermal conductivity κ and density (ρ) on temperaturehistories of a CTC device shown in Fig. 3: hsl¼100 kJ/kg and cp¼1 kJ/kg 1C.

Fig. 12. Impact of St on cylindrical spreading temperature histories of a CTC deviceshown in Fig. 3 for κ¼10 W/m 1C, and ρ¼10,000 kg/m3.

Fig. 13. Time before reaching a 90 1C threshold for the CTC device with diamondshaped loop layout of the spreader matrix and different thermal conductivity of thespreader material, as function of the PCM loading fraction.

C. E. Green et al. / Microelectronics Journal 45 (2014) 1069–10781076

pure Si heat spreading through the device stack, which allows theheated device to operate for about 3 ms before reaching thethreshold temperature, an increase in operating time ranging froma factor of 10� for the copper-based matrix up to over 20� forthe diamond-based matrix can be achieved.

The first local maximum occurs in the regime where the PCMfraction is above 90% and the performance is limited by thetradeoff between the increased spreading that is achieved withadding additional high thermal conductivity materials and theassociated decrease in the amount of PCM available for heatstorage. With higher thermal conductivity κ materials such asdiamond, CNTs or graphene, an appreciable increase in spreadingcan be achieved with the addition of a relatively small amount ofthe spreader matrix material, so that the capacitive properties ofthe composite still closely resemble that of the unaltered PCM.However, for more moderate κ spreading materials such as copperor silicon, the increase in spreading at very high PCM loading issmall, eliminating the first peak.

In the second maximum, which occurs at PCM loadings below60%, the performance is limited primarily by the amount of lateralcross sectional area allotted to the CTC. In this regime, additionalspreading could potentially be achieved by adding extra highthermal conductivity materials, but the area that is made availablefor the placement of the CTC is limited to 3 mm in diameter by theelectrical chip design and routing constraints discussed in Section3.2. While the performance of both regimes is governed by thecombination of the energy storage due to phase change at the meltfront and single phase heating of the composite material in theregions where melting has already occurred, in this lower PCMloading regime the single phase portion of the capacitance isstrongly affected by the presence of the higher thermal conduc-tivity material.

5.3. Experimental validation

As shown in Fig. 14, at �395 W/cm2 the 70% PCM fraction CTCprovides an enhancement in achievable operating time of the testdevice of over 7.5� beyond that observed with the unaltered(control) Si test chip. At 50% PCM fraction, an operating timeenhancement of 3.5� was observed.

Increasing the diameter of the CTC to 3 mm improves theperformance at 50% PCM fraction (Fig. 15). The allowable deviceoperating time with a 50% CTC improves from 29 ms for the 2 mm

device to 55 ms with the 3 mm device. This suggests that at 50%PCM fraction, the amount of PCM available for thermal storagemay be less than ideal in the 2 mm CTC. As a result, increasing theCTC diameter to 3 mm while keeping the PCM fraction constantprovides more PCM for thermal storage.

However, the phenomena cannot be explained completely bythe total amount of PCM available for storage. The 2 mm 70% PCMfraction CTC outperforms both the 2 mm and 3 mm 50% CTC, eventhough the 3 mm CTC has more PCM available than the 70%/2 mmdevice (0.67 mm3 vs 0.47 mm3, respectively). Another importantinput is the location of the PCM within the CTC. The 70% PCMfraction device has more PCM available near the center of thedevice, while the 50% PCM fraction devices have most of their PCMlocated near the outer edge of the PCM (Fig. 7). If the melt frontdoes not reach the edge of the CTC before reaching the throttletemperature, the device with more PCM in the region inside of themelt front (here the 70%–2 mm CTC) will perform better.

The notion that the PCM is not fully melted before reaching thethrottle temperature is further supported by the device perfor-mance at 300 W/cm2, shown in Fig. 16. At lower fluxes, the meltfront will be able to travel further before the device reaches its

Fig. 14. Temperature histories of �395 W/cm2 heat flux hotspots with 2 mmdiameter CTCs monolithically integrated as a part of the device under test, bothcompared to an unaltered Si (control) device performance.

Fig. 15. Comparison of temperature histories of �395 W/cm2 heat flux hotspotswith CTCs of 2 mm and 3 mm in diameter and 50% PCM fraction, both mono-lithically integrated as a part of the device under test.

Fig. 16. Temperature histories of �300 W/cm2 heat flux hotspots with CTCsmonolithically integrated as a part of the device under test, compared to a Sibaseline.

C. E. Green et al. / Microelectronics Journal 45 (2014) 1069–1078 1077

throttle temperature, and yet the 3 mm–50% CTC loses its advan-tage over the 2 mm–50% CTC at this lower heat flux. This suggeststhat the available PCM in the 50%–2 mm CTC was not fully meltedprior to reaching its throttle temperature at 395 W/cm2. The meltfront travels further, and yet the performance of the smallerdiameter CTC gains ground on the larger diameter CTC. Instead,it appears that the smaller device is now able to access more of thePCM located at the periphery of the device prior to reaching itsthrottle temperature at this lower heat flux.

The 60% PCM fraction, 2 mm in diameter device provides thelongest observed operating time of 101 ms before reaching Tthrottleat 300 W/cm2. While this is significantly longer that the operatingtimes observed at 395 W/cm2 the relative improvement of the CTCover the plain Si control device decreases to 4.2� at 300 W/cm2.This is because as the heat flux decreases, the average steepnessof the temperature history for the Si alone also decreases. As thethrottle temperature gets closer to the steady state temperature ofthe device at lower heat fluxes, the rate of change of the temper-ature will also decrease in the latter portion of the transient.However, even at this lower heat flux, a 4.2� increase inallowable operating time is still a significant enhancement.

Fundamentally, even larger heat fluxes could potentially beaddressed with the CTC than those used in this study, dependingon the desired operating times and the target high heat fluxdissipated by the device of interest. As discussed above, at higherheat fluxes the relative improvements realized from implementingthe CTC concept (i.e., over a Si baseline) should only be greater.Addressing larger heat fluxes was not attempted in this investiga-tion because without direct indication of temperature duringtesting (voltage is measured directly and converted to temperaturein post processing) it was difficult to ensure that the devices wouldnot be burned or damaged during the tests.

6. Conclusions

We have introduced a new thermal management approachbased on an imbedded composite thermal capacitor (CTC) networkthat is shown to be effective for dynamically operated electronicsdevices experiencing non-uniformities in their power profiles dueto asymmetric architectures or integration of heterogeneousdevices. It has been shown that with careful design this approachcan have a dramatic impact on core hopping and throttlingfrequencies, resulting in devices with greater spatial and temporalsynchronization. Importantly, the gains in performance (i.e., timefor device to stay operating before reaching the temperaturethreshold) are more significant as the dissipated power loadincreases, making this approach especially appealing for the highpower electronics. One of the most important advantages of theapproach is that it is locally passive, requiring no additional fluidicrouting to realize its benefits, and can be implemented usingstandard CMOS-compatible fabrication techniques.

Acknowledgments

The authors acknowledge the support of the Interconnect FocusCenter, one of five research centers funded under the Focus CenterResearch Program, a Semiconductor Research Corporation program.

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