through the looking glass—part 2 of 2pagiamt/kcsmith/trend-tracking-for-isscc2013-partii.pdfdate...

IEEE SOLID-STATE CIRCUITS MAGAZINE spring 20 13 33

ISSCC TrendS

T

Digital Object Identifier 10.1109/MSSC.2013.2254632

Date of publication: 17 June 2013

Through the Looking Glass—Part 2 of 2Trend Tracking for ISSCC 2013

The intent of the second part of this article is to share a sampling of the views held by the diverse group of experts represented by the Interna-tional Solid-State Circuits Confer-ence (ISSCC) 2013 Energy Efficient Digital; High Performance Digital; Technology Directions; Imagers, MEMS, Medical, and Displays (IMMD); and Memory program subcommit-tees. We published the findings of the subcommittees on Analog, Data Converters, RF, Wireline, and Wire-less subcommittees in the Winter 2013 issue of this magazine.

Energy-Efficient DigitalThe energy efficiency of digital circuits becomes increasingly important as larger and larger numbers of transistors are integrated on a single chip. Demand for ubiquitous mobile func-tionality for enhanced productivity, a better social-networking experience, and improved multimedia qual-ity continues to drive tech-nological innovation toward energy- and cost-efficient implementations. While the performance of embedded processors has increased to meet the rising demands of general-purpose computa-tion, dedicated multimedia accelera-tors provide dramatic improvements in performance and energy effi-ciency for specific applications.

Energy harvesting is another area of growing importance, lead-ing to technologies that leverage nonvolatile logic-based systems-on-chips (SoCs) for applications that do not have a constant power source or for handheld devices with very lim-ited battery capacity.

Technology scaling continues to be exploited to deliver designs capable of operating at lower voltages, result-ing in reduced energy per operation, as well as reducing the area required to implement specific functions. Cor-respondingly, at ISSCC 2013, proces-sors unveiled are built on a variety

of technologies, with best-in-class results as measured by integration scale, performance/watt, and inte-gration functionality. These include a few industry-first implementations demonstrated in various technologies ranging from 0.13 µm down to 28 nm bulk and SOI CMOS technologies.

Emerging medical applications require a significant reduction in standby power, compared to state-of-the-art commercial processors. This has driven the exploration of new leakage-reduction techniques in both logic and on-chip memories, target-ing orders-of-magnitude reduction in leakage currents. Fast wake-up time requirements drive the need for rap-idly saving and restoring the proces-sor state.

Figure 5 illustrates the main trends of energy relevant aspects of feature phones and smartphones. In the late 1990s, a GSM phone con-

tained a simple RISC pro-cessor running at 26 MHz, supporting a primitive user interface. After a steady increase in clock frequency to roughly 300 MHz in the early 2000s, there was a sudden spurt toward 1 GHz and beyond. Moreover, fol-lowing trends in laptops and desktops, processor architectures have become much more advanced, and recent smartphones incor-porate dual- and even quad-core processors, running up to 2 GHz. Battery capac-ity, mostly driven by the required form factor, as well as thermal limits, imply a

power budget of roughly 3 W for a smartphone. From this power bud-get, the RF power amplifier (for cel-lular communication) and the display are major drains. Overall, digital power consumption ranges from 2 W (peak) to 1 W (sustained). Thus, energy efficiency has become the

Figure 1: The development of integrated power conversion: Each year, more and more are integrated in standard CMOS technolo-gies, optimizing efficiency versus power density. At ISSCC 2013, these trends are evident in a shift to higher performance, as shown by the arrow directed to the upper right. (Adapted, cour-tesy of ISSCC 2012 Paper 5.4.)

Power Density (mW/mm2)

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Trench Caps.ISSCC 2013

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34 spring 20 13 IEEE SOLID-STATE CIRCUITS MAGAZINE

main challenge in design-ing application processors, graphics processors, media processors (video, image, audio), and modems (cellu-lar, WLAN, GPS, Bluetooth). For video and image pro-cessing, the trend has been toward dedicated optimized hardware solutions. Some new areas where dedicated processors are particularly needed include gesture-based user interfaces and computational imaging. For all digital circuits, the lim-ited power budget leads to the use of more-fine-grained clock gating, various forms of adaptive voltage-frequency scal-ing, a variety of body-bias schemes, and elaborate power-management strategies.

Figure 6 shows the evolution of bit rates for wired and wireless links over time. Interestingly, cel-lular links, wireless LAN, as well as short links, consistently show a 10# increase in bit rate every five years, with no sign of abatement. Thus, with essentially constant power and thermal budgets, energy effi-ciency has become a central theme in designing the digital circuits involved in signal processing. His-torically, CMOS feature sizes have halved every five years. For a brief

period in the 1990s, CMOS scaling (aka Dennard scaling) provided a 23 (a–3) increase in energy efficiency every five years, almost matching the required 10# power reduction. But during the past decade, CMOS scaling offers only a roughly 3# improvement in energy efficiency every five years. The resulting ever-widening gap has led to alternative approaches to improving energy efficiency, namely, new standards, smarter algorithms, more efficient digital signal processors, highly optimized accelerators, smarter hardware-software partitioning, as well as the power-management tech-niques mentioned previously.

Thus, we see a potential for a host of new applica-tions of lower- and lower-power technology created in response to the recognition of the universal importance of efficient local processing of signals in diverse omni-present areas.

High-Performance DigitalThe relentless march of pro-cess technology brings more integration and performance to digital systems each year. At ISSCC 2013, for exam-ple, IBM’s System z proces-sor leads the charge with a 2.75 B transistor chip, oper-

ating at 5.7 GHz. The chip complexity chart in

Figure 7 shows the trend in tran-sistor integration on a single chip over the past two decades. While the 1 billion transistor integration mark was achieved some years ago, we now commonly see processors with beyond 2 B transistors on a single die.

Leveraging sophisticated strate-gies to lower leakage and manage voltage, variability, and aging has bolstered the continuing reduction in total power dissipation. These strate-gies are helping rein in the increase in energy demands from PCs, serv-ers, and similar systems. As power

Figure 2: Power efficiency versus SNDR (highlighting ISSCC 2013 results).

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reduction becomes mandatory in every application, the trend toward maintaining near-constant clock frequencies also con-tinues as shown in the frequency trends plot in Figure 8. This will yield solu-tions with lower cost and lower cooling demands, resulting in greener products for the future.

As well, processor designers are choos-ing to trade off per-formance by lowering supply voltage. The performance loss of reduced voltage and clock frequency is compensated by further increased parallelism. Pro-cessors with more than eight cores are now commonplace. This year, at ISSCC 2013, a 24-core processor was presented as noted in the core-count trend chart in Figure 9.

In addition to the trend toward integrating more cores on a single chip, single packages with multiple die are appearing. At ISSCC 2013, IBM presented a multichip module with six CPUs and two embedded DRAM cache chips. As well, dedicated coprocessing units for graphics and communications are now commonly integrated on these complex systems-in-package (SiP). Design of these SoCs and SiPs requires broad collaboration across multiple disciplines includ-ing circuits, architecture, graphics, process technology, package, sys-tem design, energy efficiency, and software. New performance- and power-efficient computing tech-niques continue to be introduced for targeted critical applications, such as floating point and SIMD.

As technology continues to scale to finer dimensions, large caches are being integrated within micropro-cessor die. Figure 10 shows the gen-eral trend of large cache integration.

Methods for communication within and between die are becoming

increasingly important. These are being driven by two trends: 1) three-dimensional (3-D) integration is increasingly common and 2) intercon-nect delay becomes more dominant as processes scaled down. Designs emphasizing on-die interchip trans-port constitute a recent trend (see also wireline).

At ISSCC 2013, another trend in evidence was the continued emer-gence of all-digital phase-locked loops (PLLS) and delay-locked loops (DLLs) that better exploit nano-meter-feature-size scaling while

reducing power and area costs. Due to the application of highly innova-tive architectural and circuit design techniques, the features of these “all-digital” PLLs and DLLs have improved significantly over the recent past. Figure 11 shows the jit-ter performance versus energy cost for PLLs and MDLLs.

Overall, digital processors con-tinue to grow in complexity, while more circuits are implemented using digital techniques to cope with vari-ability and ease scaling to finer geometries.

Figure 5: Developments in application processors for smartphones.

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3 M 5~8 M 10 M 16 M 20 M DualCamera

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Figure 6: Wireless and wired data rates over time. (Image courtesy of G. Fettweis.)

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IMMDThe common thread that unites the constituents of IMMD is a concern for interfaces with the physical world—both the human body and its environ-ment. Conventionally, we consider this broad area in terms of both tool and task: imagers, MEMS, medical, and displays, as discussed below.

ImagersSince 2010, there has been growth beyond expectations in the adoption of mobile devices, such as smart-phones and tablets, that has induced larger volumes of CMOS image sen-sor chips. Both the resolution and miniaturization races are ongoing, and performance metrics are becom-ing more stringent. In addition to conventional pixel shrinkage, a “more than Moore” trend is increas-ingly evident: Resolution of over 20 Mpixels is commercially available for mobile devices employing enhanced

small-size pixels. As a consequence of innovative readout and ADC archi-tectures embedded at the column and chip levels, data rates approach-ing 50 Gb/s, and a noise floor below single electron have been demon-strated. In addition to conventional applications, ultra-low-power vision sensors, 3-D, high-speed, and multi-spectral imaging, are front-running emerging technologies.

Back-side illumination (BSI) is now the mainstream technology for high-volume, high-performance mobile applications. While 1.12 nm BSI pixels are currently available, the industry is potentially mov-ing toward 0.9 nm pixel pitch and below. Additional innovative tech-nologies outside of traditional scal-ing include advanced 3-D stacking of a specialized image-sensor layer on top of deep-submicron digital CMOS (65 nm 1P7M) using through-silicon vias (TSVs) and microbumps.

The importance of digital signal processing technology in cameras continues to grow to mitigate sen-sor imperfections and noise and to compensate for optical limitations. The level of sensor computation is increasing to thousands of opera-tions per pixel, requiring high-performance and low-power digital signal processing solutions. In par-allel with these efforts is a trend through out the image-sensor indus-try toward higher levels of integra-tion to reduce system costs.

Ultra-low-power vision sensors are being reported in which more programmability and computation is performed at the pixel level to extract scene information, such as object features and motion.

Lightfield/plenoptic commercial cameras, which have been avail-able since 2010, are gaining popu-larity and are being marketed for 3-D imaging and/or all-in-focus

Figure 8: Clock frequency.

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two-dimensional imaging. On-chip stereoscopic vision has been demonstrated through digital micro lenses (DMLs), paving the way to next-generation passive 3-D imaging for mobile and entertainment applications, such as through gesture-control user interfaces.

Significant R&D effort is being spent on active-3-D-imaging time-of-flight (TOF) applications to support requirements from autono-mous driving, gaming, and industrial applications, addressing open challenges, such as background light immunity, higher spatial resolution, and longer dis-tance range. Deep-submicron CMOS single-photon avalanche diodes (SPADs) have been developed by sev-eral groups in various submicron technologies. They are now capable of meeting the requirements for high-resolution and high-timing accuracy by employing highly parallel time-to-digital converters (TDCs) and small pixel pitch with better fill factor.

Ultra-high-speed image sensors for scientific imaging applications having up to 20 Mf/s acquisition speed have been demonstrated.

Multispectral imaging is gain-ing a lot of interest from the image-sensor community: several research groups have demonstrated fully-CMOS room-temperature tera-hertz image sensors, and a hybrid sensor capable of simultaneous vis-ible, IR, and terahertz detection has been reported.

The share of the market for CCDs in machine vision, compact DSCs for security applications, continues to shrink. Only for high-end digital cameras for astronomy and medi-cal imaging do CCDs still maintain a significant market share.

MEMS and SensorsMEMS inertial sensors are finding widespread use in consumer appli-cations to provide enhanced user interfaces, localization, and image

stabilization. Accelerometers and gyroscopes are being combined with 3-D magnetic-field sensors to form nine-degree-of-freedom devices, and pressure sensors will eventually add a tenth degree. The power consumption of such devices is becom-ing sufficiently low for the sensor to operate continuously, enhanc-ing indoor naviga-tion. There have been further advances in heterogeneous integration of MEMS with interface circuits to support increased perfor-mance, larger sensor arrays, reduced noise sensitivity, reduced size, and lower costs.

To address the stringent require-ments of automotive, industrial, mobile, and scientific applica-tions, MEMS inertial sensors, pres-sure sensors, and microphones are becoming more robust against electromagnetic interference (EMI), packaging parasitics, process-voltage-temperature (PVT) varia-tions, humidity, and vibration.

Sensor interfaces achieve increas-ingly high resolution and dynamic range while maintaining or improv-ing power or energy efficiency. This is achieved through techniques such as zooming, nonuniform

quantization, and compen-sation for baseline values.

New calibration approaches, such as voltage calibra-tion, are being adopted for BJT-based temperature sen-sors to reduce cost. In addi-tion to thermal-management applications (prevention of overheating in microproces-sors and SoCs), temperature sensors are also increasingly co-integrated with other sensors (such as humidity, pressure, and current sen-sors) and MEMS resonators for cross-sensitivity compen-sation. Alternative temper-ature-sensing concepts find their way into applications with specific requirements

not easily addressed by BJTs: thermal diffusivity-based sensing for high-temperature applications; thermistor-

based and Q-based concepts for in-situ temperature sensing

of MEMS devices; and for ultra-low-voltage operation.

MEMS oscillators continue to improve. Phase noise is now low

enough for demanding RF applications (12-kHz to

20-MHz integrated jitter is now below 0.5 ps); and frequency accuracy is now better than 0.5 p/m. Consumer applications are adopting such new low-power and low-cost oscillators.

BiomedicalThere have been continuous achieve-ments in the area of ICs for neural and biopotential interfacing tech-nologies. Spatial resolution of neu-ral monitoring devices is being reduced, utilizing the benefits of CMOS technology. IC providers are increasing their component offer-ings toward miniaturization of por-table medical devices.

Telemedicine and remote-monitor-ing applications are expanding with support from IC manufacturing com-panies. Moreover, the applications of such systems are not limited to

Figure 11: PLL and MDLL trends.

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Developments reported at ISSCC 2013 continue to present breakthroughs in the broad domain of solid-state circuits and systems.


services targeted for elderly or chronically ill patients; for example, there are sev-eral technologies developed to enhance the way clinical trials are conducted by moni-toring patient adherence and improving data collection. Low-power WiFi and Blue-tooth low energy is emerg-ing as a standard wireless connection between portable communication services and wearable technology.

Smart biomolecular sensing is another major trend that marries the solid-state and biochemi-cal worlds together with the ultimate goal of enabling a more predictive and preventative medical care. With the help of the accuracy and parallelism enabled by CMOS technology, time, cost, and error rate of DNA sequencing may be significantly improved. Direct electronic readout may relax the need for complex biochemical assays. Similar trends are becom-ing increasingly evident in pro-teomics and sample preparation.

Even for medical imaging, there is a shift from hospital imaging toward point-of-care and portable devices. A key example is in porta-ble high-resolution ultrasounds in which larger scientific imaging set-ups are being integrated onto the sensor through process technolo-gies (such as integrated spectral filters, CMUT). Another example is in molecular imaging. The advent of silicon photo multipli-ers (SiPM), which provide a solid-state alternative to PMTs, enables the realiza-tion of PET scanners com-patible with MRI, opening the way to new frontiers in the field of cancer diagnos-tics. More recently, SiPMs realized within deep-sub-micron CMOS technologies have allowed the integra-tion at pixel- and chip-level extra features, such as mul-tiple timestamp extraction,

allowing a dramatic reduction in system cost.

DisplaysThe desire to put much higher-resolution and higher-definition displays into mobile applications is one of the display-technology trends that is now opening a full HD smartphone era. High-def-inition displays of 440 p/i are expected, even for 5-in display sizes. Low-temperature poly silicon (LTPS) technology seems to have more merit than amorphous-silicon thin-film-transistors (a-Si TFTs) technology. But a-Si TFT and oxide TFT technologies supported by compensating driver systems are beginning to compete with it. Very-large-size LCD TVs over 84 in, with UD (3,840 # 2,160) resolution are

now the leading entertain-ment systems. Also open-ing new opportunities in consumer applications are 55-in AMOLED TVs with full HD resolution.

As touch-screen displays for mobile devices become increasingly thin, capacitive touch sensors move closer to the display. But the resulting in-cell touch displays come with reduced signal levels due to increased parasitics and increased interference from the display and switched-mode chargers. Noise immu-nity is improved by adopting noise filtering and new signal-modulation approaches.

Thus, overall, we see an expansion of diverse techniques evolving in aid the most important role of modern technology—to serve mankind.

MemoryDevelopment in mainstream memory technologies continues unabated. We see progressive sustained scal-ing in embedded SRAM, DRAM, and floating-gate-based Flash for very broad applications. However, due to the major scaling challenges in all mainstream memory technolo-gies, we see a continued increase in the use of smart algorithms and error-correction techniques to com-pensate for increased device vari-ability. In further response to these challenges, we see logic processes adopting FinFET devices along with read- and write-assist circuits in

SRAMs. Meanwhile, emerg-ing memory technologies are making steady progress toward product introduc-tion, including PCRAM and ReRAM, while STT-MRAM is beginning to become a strong candidate for both standalone and embedded applications.

SRAMEmbedded SRAM continues to be a critical technology enabler for a wide range

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Figure 13: Trends in DRAM data rate/pin.


of applications from high-perfor-mance computing to mobile uti-lization. The key challenges for SRAM include VCCmin, leakage and dynamic power reduction while relentlessly following Moore’s law to shrink the area by 2# for every technology generation. As the transistor feature size has marched to under 30 nm, device variation has made it very dif-ficult to shrink the bit-cell size at the 2# rate while maintaining or lowering VCCmin between gen-erations. Starting at 45 nm, the introduction of high-k metal-gate technology reduces the Vt mis-match and further enables device scaling by significantly reducing the equivalent oxide thickness. Starting at 22 nm and beyond, new transistors such as FinFETs and fully depleted SOIs are key to enabling the continuous scal-ing of bit-cell area and low-voltage performance. Design solutions such as read/write-assist circuitry have been used to improve SRAM VCCmin performance starting at 32 nm. New SRAM bit cells with more than six transistors have also been proposed to minimize oper-ating voltage. For example, 8T reg-ister file cells have been reported in recent products requiring low VCCmin. Dual-rail SRAM design emerges as an effective solution to enable dynamic voltage-frequency

scaling (DVFS) by decoupling the logic supply rail from the SRAM array, thus allowing a much wider operating window. It is important for SRAM to reduce both leak-age and dynamic power, keeping products within the same power envelope for succeeding feature-size reductions. Sleep transis-tors, fine-grain clock gating, and clockless SRAM designs have been proposed to reduce leakage and dynamic power. Redundancy and ECC protection are also keys to ensure yield and reliability when

embedded SRAM products go into production. Figure 12 shows the trend in SRAM-bit-cell scaling on the left axis and the trend in SRAM supply-voltage scaling on the right axis, using data from major semi-conductor manufacturers.

High-Speed I/O for DRAMTo reduce the bandwidth gap between main memory and pro-cessor frequencies, external data rates continue to increase as con-ventional high-speed wired inter-face schemes (such as DDRx and

Figure 14: Read- and write-bandwidth comparison of nonvolatile memories.

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GDDRx for DRAM) evolve, as shown in Figure 13. Currently, GDDR5 and DDR4 memory I/Os operate around 7 Gb/s/pin and 3 Gb/s/pin, respectively. To achieve higher data-transfer rates, signal-integrity tech-niques (such as crosstalk, noise, and skew cancellation) and speed enhancement techniques (such as equalizers and pre-emphasis) have been developed. These advanced techniques have pushed I/O speeds toward 10 Gb/s/pin. Lower power consumption for data center and mobile applications has also been pursued. A near-ground signaling method, termination impedance optimization, decision feedback equalization, and clock-feathering

Figure 18: Output power versus frequency for mm-wave and sub-mm-wave sources.

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slew-rate control technologies have been demonstrated to reduce the power dissipation of memory inter-faces significantly, while achieving high bandwidth.

Nonvolatile MemoriesIn the past decade, significant focus has been put on the search for emerging memories to pro-vide a possible alternative to floating-gate nonvolatile memory (NVM). The emerging NVMs, such as phase-change memory (PRAM), ferroelectric RAM (FeRAM), spin-torque-transfer magnetic RAM (STT-MRAM), and resistive memory (ReRAM), are showing the poten-tial to achieve high-cycling capa-bility (operational lifetime) and lower power per bit for both read and write operations. Some com-mercial applications, such as cel-lular phones, have recently begun to use PRAM, demonstrating that reliability and cost competitiveness of emerging memories is becoming a reality. Fast write speed and low read-access time are being achieved in many of these emerging memory schemes. At ISSCC 2013, a 32 Gb ReRAM cross-point array was dem-onstrated in 24-nm technology. Figures 14 and 15 provide a sum-mary of the scaling trends for both bandwidth and density of emerging memories.

NAND Flash MemoryNAND Flash memory continues to advance toward higher den-sity and lower power, resulting in low-cost storage solutions that are enabling the replacement of traditional hard-disk storage with solid-state disks (SSDs). The use of multiple bits per cell has proven to be effective in increasing the den-sity. Figure 16 shows the observed trend in NAND Flash capacities presented at ISSCC over the past 18 years. With scaling, device vari-ability and error rates increase, requiring system designers to develop sophisticated control algo-rithms to compensate. Some of these algorithms are implemented

outside the NAND silicon, in the system memory controller (in particular, the ECC and data man-agement methods), for improved overall reliability. Possible future scenarios include 3-D-stacked NAND vertical gates as a solution to further increase overall NAND-memory density.

Current state-of-the-art results from ISSCC 2013 include:

■ 32 Gb ReRAM test chip developed in 24-nm CMOS

■ the first ever 128 Gb 3 b/cell NAND Flash design in 20-nm pla-nar-cell CMOS

■ a 45 nm, 6 b/cell charge-trapping Flash memory using LDPC-based ECC demonstrates a ten-year error-free operation

■ a highly efficient 6.4-Gb/s near-ground single-ended low-common mode transceiver for memory interface

■ a highly efficient SRAM operating at 0.6 V used statistically gated sense amplifiers.

Technology Directions (TD)The role of the Technology-Direc-tions Subcommittee is to identify and encourage developments of potential importance in the ongoing evolution of ISSCC. Characteristically, a wide variety of topics are covered, some

new and some continuing, with suc-cess achieved by the transference of the emerging technique to one of the evolving mainstream subcommit-tees. This year at ISSCC 2013, two strong emerging trend directions were visible: in flexible electronics and in NVM.

Large-Area Flexible ElectronicsIn the field of flexible large-area electronics fabricated at low tem-peratures, the current focus is now on lowering the cost-per-unit area, rather than on increasing the num-ber of functions-per-unit area that is the focus of crystalline silicon tech-nology, following Moore’s law.

A clear breakthrough in research for large-area electronics in the past decade has been the development of thin-film transistor (TFT) processes with an extremely low temperature budget (1150 °C), enabling manu-facturing on flexible and inexpen-sive substrates such as plastic films and paper.

For some time, the materials used for these developments have been carbon-based organic mole-cules such as pentacene, with prop-erties of p-type semiconductors. More recently, air-stable organic n-type semiconductors and amor-phous metal oxides, which are also

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Figure 21: Data rate for wireless connectivity standards (802.11x).


n-type semiconductors, have emerged. The most popular metal-oxide semi-conductor is amorphous indium gallium zinc oxide (IGZO), but variants exist (zinc oxide, zinc tin oxide, and so on). The mobility of n- and p-type organic semiconductors has reached values exceed-ing 10 cm2/Vs, which is already at par or exceeding the performance of that using amorphous silicon. Amorphous metal-oxide transistors have typical charge carrier mobility of 10–20 cm2/Vs. Moreover, the operational stability of all organic semiconduc-tor materials has greatly improved to a level suffi-cient to enable commercial appli-cations, especially in combination with large-area compatible barrier layers to seal the transistor stack.

In the present state of the art, p-type only, n-type only, and com-plementary technologies are avail-able. For the latter, all-organic implementations are available, but also we see hybrid solutions, featur-ing the integration of p-type organic with n-type oxide TFTs. At present, most TFTs are still manufactured with technologies from display lines, using subtractive methods based on lithography. However, there is a clear emphasis on the development

of additive technologies that could provide higher production through-put, based on different approaches borrowed from the graphic print-ing world, such as screen and ink-jet printing. The feature sizes and spread of characteristics of printed TFT technologies are still larger than those made by lithography, but there is clear progress toward size reduction.

The primary applications for such TFT systems are as backplanes in active-matrix displays, particu-larly flexible ones. Organic TFTs are well suited for electronic-paper-type displays, whereas oxide TFTs are

targeting OLED displays. Fur-thermore, TFTs on foil are well suited for integration with temperature or chemical sensors to create pressure-sensitive foils, photodiode arrays, antennas, sheets capable of distributing RF power to appliances, energy scavenging devices, and so on, in hybrid integrated systems on foil. Early dem-onstrations include smart labels, smart shop shelves, smart medical patches, and so on. These are enabled by continuous progress in the complexity of analog TFT cir-cuits targeting the interface with sensors and actuators, to modulate, to amplify, and to convert analog signals, as well as progress in digital

TFT circuits and NVM for signal pro-cessing and storage.

Nonvolatile Memory in LogicWith continuing technology scal-ing, advances in energy-efficient computation will become even more important. Correspondingly, at ISSCC 2013, a new trend can be seen: It involves the integration of NVM with logic for ultra-fast power-down/power-up while maintaining the state of the computation. Such technologies will impact future mobile platforms and industrial applications, making mobile com-puting truly ubiquitous.

Figure 24: Wireline transceiver power efficiency versus channel loss.

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Figure 22: Per-pin data rate versus year for a variety of common wireline I/O standards.


Thus, we see two examples of the many new directions in which the electronics industry are likely to flow, as continuously uncovered by technology directions at ISSCC.

SummaryDevelopments reported at ISSCC 2013 continue to present break-throughs in the broad domain of solid-state circuits and systems. In this rich environment, presentations at ISSCC characteristically predict ways in which electronics techniques will fulfill the present and future needs of the IEEE Solid-State Circuits Society. In this role, ISSCC continues to present a road map of things to come, both in the immediate future and in the longer term.

AcknowledgmentsThe authors wish to acknowledge the creators of the original material from

which this article has been struc-tured. While this has been largely a team effort by several members of each subcommittee, each has oper-ated under the direction of his or her subcommittee chair, as follows:

■ Energy-Efficient Digital: Stephen Kosonocky, Advanced Micro Devices

■ High-Performance Digital: Stefan Rusu, Intel

■ Technology Directions: Hoi-Jun Yoo, KAIST

■ Imagers, MEMS, Medical, and Dis-plays: Roland Thewes, TU Berlin

■ Memory: Kevin Zhang, Intel ■ Analog: Bill Redman-White,

Southampton University ■ Data Converters: Boris Murmann,

Stanford University ■ Radio Frequency: Andreia Cathe-

lin, STMicroelectronics ■ Wireless: David Su, Atheros

Communications

■ Wireline: Daniel Friedman, IBM Thomas J. Watson Research Center.Our thanks go as well to the

ISSCC technical editors for their ini-tial editing and interaction with sub-committee members:

■ Jason Anderson, University of Toronto

■ Vincent Gaudet, University of Waterloo

■ Glenn Gulak, University of Toronto

■ James Haslett, University of Calgary

■ Kostas Pagiamtzis, Semtech.

—Kenneth C. Smith University of Toronto, Canada

—Alice Wang MediaTek, Texas

—Laura C. Fujino University of Toronto, Canada

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