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אופטיקה -נושאים נבחרים באלקטרו

נוריאל אמיר' דר

Technical Director – KLA-Tencor

האוניברסיטה העברית

2 חומרים ותהליכים במיקרואלקטרוניקה - 82001


מנהל המחקר והפיתוח במיקרון ישראל

המכללה להנדסה

ירושלים

טכנולוגיות במיקרואלקטרוניקה 05124700

סמסטר ב' 2009

2011תהליכי יצור במיקרואלקטרוניקה


מנהל המחקר והפיתוח במיקרון ישראל

אוניברסיטת בן גוריון

5

Process Integration

Dr Nuri Amir & Shaul Halabi

Course Contents:

1. Silicon as a Semiconductor

2. Clean Room & particles / defects

3. Yield and E-test

4. Assembly and Reliability

5. Intro to design and process interaction

6. Future Trends

6

Silicon as a Semiconductor

95% of the Semiconductor industry use Si

Other Semiconductors:

Used for specific, small markets (optoelectronics, RF)

There is no known substituted to Si,

Si/SiO2 interface is the best known

Ge has lower Oxide interface quality

Si-Sio2 interface charge as low as 10E10/cm2

6/8/12” in diameter, ¾ millimeter thickness

The active device located on the top 1µ

Silicon and Other Semiconductors Silicon as a Semiconductor

7

Clean Room - Particles and Yield Impact

Clean room is the physical manufacturing area

No cost limitation to maintain room’s cleanliness

Particles of 0.02micron and up are ‘killers’ - can

“open” a metal line or short two neighbor lines

Particles and Yield Impact Clean Room

8

Clean Room - How Clean is Clean?

“Class 1” Clean Room

One or less, 0.3micron particle, within 1 cubic feet

10,000X Cleaner than a Hospital operating room


9


Human Hair: 75-100 Micron

The smallest particle that the human eye can see: 40 Micron

A 0.5 Micron particle (10X bigger than a killer particle)


10


Human Hair


11

Clean Room - many tool for defects detection


12

Clean Room - many tool for defects detection Using Die to Die Comparison

Reference Die

Inspected Die

Partially Etched Holes


13

Def 2

X-s

ectio

n

Pt decoration

Metal5

ILD5

Si particle

W ILD5

X-s

ectio

n

Pt decoration

Pt decoration

Metal5

ILD

5

Metal5

ILD5

Si particle

Def 11

• Few defects were X-sectioned. In all cases W filled

ILD5 Tearouts were found.

• Imbedded in ILD5 Silicon particles were found as well.

• All images shows thin ILD5 layer under the defect.

It means that defect fall down at the beginning of ILD

deposition.


14

Yield and E-Test

Yield

Basic MOS transistor

Device and E-Test Structures

Yield and E-test

15

Line Yield: Refers to the number of good wafers produced without being

scrapped - effectiveness of material handling and process control.

Die Yield (sort yield): Refers to the number of good dice that pass wafer

probe testing from wafers that reach that part of the process.

Chip can be non functional due to:

Defects

Contamination

Electrical parameter out of range

Process parameter out of range

Wrong process

Sort is the area to check chips functionality

Yield Terminology

InWafers

OutWafersY L _

_

N

dicegoodY P

_

N is the total

Number of dice

printed per Wafer

Yield and E-test

16

00.10.20.30.40.50.60.70.80.9

1 2 3 4 5 6 7 8 9

Die Area

Yie

ldYield reduces as the area increases

YYYY RSLieldxx

(YL) Line Yield = Wafers out / Wafers In

(YS) Systematically Effecting every die

(YR) Caused by particle – Random

eeY AD x

R

0

D0= faults density per cm2

A = die area

= average no. of faults per die

Yield and E-test

17

Smaller chips Higher yield

Yield and E-test

18

Smaller chips Higher yield

Edge

Defects

Yield and E-test

9/13 = 69% yield

Overall 9 good die

81/86 = 94% yield !

Overall 81 good die !!!

see the impact of 4X reduction => 9X number of die:

19

Random & systematic yield issues: Yield and E-test

examples of real wafers with problems

20

Device and E-test (Electrical testing) Structures

Resistors Sheet Rho, Dimension, Contact Chain (CC) and single contacts.

Capacitors Area, Edge,

Transistors Different Types and Dimensions

Isolation and Junction Structures diffusion to diffusion and well to diffusion

Edge and area junctions

Device & E-Test Structure Yield and E-Test

21

Etest measurements

Etest parameters are located in the ”scribe lines”

between the dies, and they are built in the same

time and in the same process as the dies

themselves.

Each of the Etest parameters has upper and lower

control and/or Dispo limits. Wafers which exceed the

Dispo limits are not sent to customers. This is part of

the quality control.

Each parameter is tested on at least 16 sites on the

wafer, and all of them have to meet the control and /

or Dispo parameter, hence we need to control also

the range and STDV of each Etest parameter.

E-Test measurements Device & E-Test Structure Yield and E-Test

22

Resistors

Wide resistor -

Sheet resistance is calculated

from resistance of the wide

structure. The wide structure is

less sensitive to dimension

variation

Narrow resistor –

Dimensions are calculated from

the resistance of the narrow

resistor by using the sheet

resistance of the wide structure

Wide Resistor

Narrow Resistor

Device & E-Test Structure Resistors Yield and E-Test

23

Resistors

rs = Sheet Resistance

R = Resistance

r = Resistively

T = Thickness

L = Length

W = Width

R = r * ( ) L

W * T

rs r

T

R rs * L W

Resistors Device & E-Test Structure Yield and E-Test

24

Chain and Single Contacts/Vias

Large number of contacts

connected in series or single

contact

The overlap of the top layer

and the enclosure to the

bottom layer are considered in

the design rules

The chain resistance is a sum

of the contacts/vias resistance

and the chains resistance

Chain Contact

Single Contact

Chain & Single Contacts Resistors Device & E-Test Structure Yield and E-Test

25

Capacitors

Area Capacitor

Diffusion edge Capacitor

Poly edge Capacitor

Diffusion edge capacitor

Poly Oxide Isolation Diffusion

Diffusion edge capacitor

Poly Oxide Isolation Diffusion

Capacitors Device & E-Test Structure Yield and E-Test

26

Gate Oxide Thickness Measurement

Measurement is done by using the basic concept of

plate capacitor and the measurement is done in well

inversion

There is a significant offset between the electrical

and the physical thickness due to poly depletion and

charge distribution in the channel

Gate OX Capacitors Device & E-Test Structure Yield and E-Test

27

GRD

well

Gate

GRD

1.3volt

1.3 volt

Source Drain

E-test of MOS Transistors

Yield and E-Test Transistors Device & E-Test Structure

28

Transistor Key Parameters Trans-conductance Gm: Indication for how much the drain

current changes in response to the gate voltage (Id/ Vg)

Extrapolated VT : Threshold voltage for the transistor. Is

calculated from the maximum trans-conductance slope

Saturation current Id: Drain to source current in operation mode

Junction breakdown BVJ - The voltage on the junction which

sustains a leakage current of 1 uA.

BV Punch through - Leakage of current between the drain and

the source

Substrate current Isub - Charge carriers which are collected at

the substrate as a result of high electric field in the drain which is

generating electron/holes pairs

Key Parameters Transistors Device & E-Test Structure Yield and E-Test

29

Type of Structures:

N+ to Nwell and

P+ to Pwell Isolation

N+ to N+ and P+ to P+

Isolation

Isolation

N+ Diff

Nwell Pwell

P+ Diff

Diffusion

Metal 1

Contact

Trench

Isolation Device & E-Test Structure Yield and E-Test

30

Junctions

Area Junction

Edge Junction

N+ or P+

Nwell or Pwell

N+ or P+

Junction Device & E-Test Structure Yield and E-Test

31

Assembly Slice the wafers and package the

single chips

Functional test, similar to the Fab sort

post package

Assembly site usually at a different

location than the process Fab

Assembly Assembly and Reliability

32

Failure Mechanism

Infant Mortality Regime

Defect related

May correlate with yield

Circuits may act abnormally

Subject to screening

Wearout Regime

Materials wear out

Design sensitivity (design rule)

Characterize with test structures

Usually does not correlate with yield (may anti correlate)

Random Failure Regime

Random defects

Latchup (induced by random noise spikes)

Single event upset (from alpha particles, cosmic rays)

Failure Mechanism Reliability Assembly and Reliability

Infant Mortality

Wearout

Random

Time

Failu

re R

ate

Life (Bathtub) Curve

33

“Yield” and “Reliability” Defects

Very Small Defect

Small Defect

Medium Defect

Large Defect

Defects Reliability Assembly and Reliability

34

“Yield” and “Reliability” Defects

Very Small Defect

Small Defect

Medium Defect

Large Defect

Defects Reliability Assembly and Reliability

35

Electro Migration (EM)

Accumulation Void DS

DL

e-

Electro Migration Reliability Assembly and Reliability

36

Synthesis

Schema

RTL

Lay Out

Module inv (out,in)

Wire in

…

Vss

Vdd

Place & Rout

Logic

Design

Circuit

Design

Layout

Design

Intro to Design and process interaction - Design Overview

37

The parasitic capacitance is proportional to the transistor’s width

Layout

Cp

Ca Cov

Cross Section

Cjp

Cja Cjg

Transistor parasitic capacitance

Self

capacitance

Layout vs. cross-section transistor Intro to design

38

Example for Inverter's layout

Matal 1 Layout & process Intro to design

B

A

B

p sub.

n well

p sub.

n well

\

n +

p + p + n + n +

p +

B

A

Vcc Vss

Input Output

vcc

vss

in out

40

Symbol l Logic function

IN OUT

0 1

1 0

VCC

VCC

VIN

VOUT

VCC

2

l The transfer function

The ideal inverter

Ideal inverter Inverter Intro to design

41

VCC 0V

VCC

IN OUT

Inverter operation “1” to “0”

Nmos opens in VCC

Operation Inverter Intro to design

42

0V VCC

IN OUT

VCC

Inverter operation “0” to “1

Pmos opens in Zero

Pmos

Nmos

Operation Inverter Intro to design

43

A B A*B

0 0 1

0 1 1

1 0 1

1 1 0

A

B

OUT

A

B

A*B

Logic function example – NAND

Better to pass “1”, need

strong Nmos to pass “0”

Operation NAND Intro to design

44

A B A+B

0 0 1

0 1 0

1 0 0

1 1 0

A OUT

B

A

B

A+B

NOR

Good to pass “0”, need

strong PMOS to pass “1”

Operation NOR Intro to design

45

Which are the functions in the layouts?

VCC

GND

B

A Vout

VCC

GND

B A

Vout

Layouts identification Intro to design

46

Vcc BL BL

WL WL

SRAM layout

Layout SRAM Intro to design

47

VCC VCC

Precharge_l WEN WEN

BIT BIT#

Sense Amp

Out

Ram cell

Ram driver

Address

Decoder

Word line

Data in Control

(Clocks)

SRAM cell schematics

operation SRAM Intro to design

48

WEN = ‘1’ WEN = ‘1’

BIT BIT#

Word line = ‘1’

Data in

VCC VCC

Precharge_l=‘1’

SRAM operation - Write


49

VCC VCC

Precharge_l=‘0’ WEN=‘0’

BIT BIT#

Sense Amp

Out

Ram cell

Ram driver

Address

Decoder

Word line

Data in

WEN=‘0’

SRAM operation - Precharge


50

WEN = ‘0’

BIT BIT#

Sense Amp

Out

Word line = ‘1’

WEN = ‘0’

VCC VCC

Precharge_l=‘1’

SRAM operation - Read

Data in


51

CLK

PRC_L

WEN

WORD_SEL

BIT

Write cycle Read cycle

SRAM timing


52

Example for Inverter's layout


B

A

B

p sub.

n well

p sub.

n well

\

n +

p + p + n + n +

p +

B

A

Vcc Vss

Input Output

vcc

vss

in out

53

l Defines the active and Isolation areas

l Defines the transistor width

B

A

B

p sub.

p sub.

STR drawing layer

B

A

Isolation Layout & process Intro to design

54

l Surrounds PMOS transistors

l P-well mask is complimentary to N-well mask and doesn’t need to be drawn

A

B

N-well drawing layer

p sub.

n well

p sub.

n well

B

A

Wells Layout & process Intro to design

55

l Defines the transistor length

l Defines small lines

B

A

p sub.

n well

intel confidential

Poly drawing layer

B

A p sub.

n well

Poly Layout & process Intro to design

56

p sub.

n well

SiO2

p sub.

n well

SiO2

p +

p + p +

A

B

P+ drawing layer

B

A

l Poly doping is defined by the well doping

P+ Layout & process Intro to design

57

l Poly doping is defined by the well doping

p sub.

n well

SiO2

n well

SiO2

n +

p + p + n + n +

p +

A

B

N+ drawing layer

B

A

N+ Layout & process Intro to design

58

p sub.

n well

SiO2

p sub.

n well

SiO2

n +

p + p + n + n +

p +

B

A

B

Contact drawing layer

B

A

contact Layout & process Intro to design

59

p sub.

n well

p sub.

n well

\

n +

p + p + n + n +

p +

B

A

B

Metal1 drawing layer

B

A


60

All together


B

A

B

p sub.

n well

p sub.

n well

\

n +

p + p + n + n +

p +

B

A

Vcc Vss

Input Output

vcc

vss

in out

Poly Stack sketch example

HM SiN 400A

Poly 700A

Si

APF – 900 A

Si

Resist 1000A

HM Ox 150A

DARC – 150A BARC – 50A

Oxide 1400A

62

Future Trends

Moore’s Law

Modern Technology Features

Technology Challenges

1st Electronic Computer

Eniac vs. Atom

Historical perspective

Future Trends

63

The original Moore’s Law

In 1965, Gordon Moore’s prediction, popularly known as Moore's Law, states that the number of transistors on a chip will double about every two years.

64

Future Trends Moore’s Law

65

Modern Technology Features

300mm wafers (450?)

9+ Layers of Metal

=<32nm line / space

Aspect ratios 6->10!

Tri gate

Strained silicon

Fully panelized

Salicided/metal gate

Speeds > 3 GHz

High K Gate

Low K ILD

Multi Stacked packaging

Modern Technology Features Future Trends

66


67

Advanced transistor features


68


69


70

Technology Challenges

Solutions Challenge

Extreme UV and immersion tools

X-Ray Lithography

Phase shift masks

Stressed & strained silicon

Speed and Size =

Sub Micron Lithography

Low dielectric constant glasses (Low K ILD)

Copper conductors

Super shallow junctions – Low energy implants &

Epi growth on Source-drain

Speed = RC Effects

More selective etches

High pressure depositions

High plasma depositions

High Aspect Ratios

Technology Challenges Future Trends

71

First Electronic Computer

The Eniac , 1946

Historical perspective Future Trends

72

We’ve come a long way...

Eniac

18,000 tubes

200 bytes RAM

5000 additions/sec

MTBF = minutes

30 Ton

2008 laptop (Atom processor)

2,000,000,000 transistors

2 Billion bytes RAM

>50 Billion additions/sec

MTBF = years

3.5 Kg

and remember why …

= 1 X 2,000,000,000 X


73

First integrated circuit 1961


74

אני חושב שיש מקום "

בשוק העולמי

"מחשבים בלבד 5-ל

תומס ווטסון

,IBMר חברת "יו

1943


75

אין סיבה שמישהו "

"ירצה מחשב בביתו

קן אולסון

ר ומייסד חברת "יו, נשיא

Digital Equipment

1977


this is the title - hebrew university of jerusalemaph.huji.ac.il/courses/2014_15/83842/4.pdf ·...

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