thi nghiem vi xu ly va vi dieu khien

8/4/2019 Thi Nghiem Vi Xu Ly Va Vi Dieu Khien

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I HC QUC GIA TP.HCMTRNG I HC BCH KHOAKHOA KHOA HC V K THUT MY TNH

TH NGHIMVI XL - VI IU KHIN

BM K thut My tnh

2011


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Mc LcMc Lc .............................................................................................................................. 1Bi 1 : Gii thiu MPLAB IDE v KIT PIC .................................................................. 1

1.1 Mi trng pht trin MPLAB ................................................................................. 1

1.2 Np file hex vo vi iu khin PIC........................................................................... 61.3 Debug dng MpLab SIM........................................................................................ 101.4 Debug onchip dng Mplab ICD2............................................................................ 121.5 Bi tp ..................................................................................................................... 12

Bi 2 : Kho st cng xut nhp ................................................................................... 132.1 Kin thc lin quan................................................................................................. 13

2.1.1 Cc thanh ghi iu khin cng xut nhp ........................................................ 132.1.2 Kt ni mch .................................................................................................... 13

2.2 Cc bc hin thc yu cu 1 ................................................................................. 142.3 Chng trnh mu yu cu 1................................................................................... 162.4 Cc bc hin thc yu cu 2 ................................................................................. 17

2.5 Chng trnh mu yu cu 2................................................................................... 182.6 Bi tp ..................................................................................................................... 20Bi 3 : Kho st cch ngt qung, giao tip LCD k t ............................................ 21

3.1 Kin thc lin quan................................................................................................. 213.1.1 Tm tt cc thanh ghi iu khin ngt ............................................................. 21

3.2 Cc bc hin thc yu cu 1 ................................................................................. 223.3 Chng trnh mu yu cu 1................................................................................... 243.4 LCD k t 2x16 ...................................................................................................... 26

3.4.1 Hnh dng v ngha cc chn: ....................................................................... 263.4.2 T chc vng nhca LCD............................................................................. 273.4.3 Cc lnh giao tip vi LCD ............................................................................. 30

3.4.4 Khi to LCD................................................................................................... 313.5 Cc bc hin thc yu cu 2 ................................................................................. 323.6 Bi tp ..................................................................................................................... 37

Bi 4 : Kho st bnh thi ........................................................................................ 384.1 Cc bc hin thc yu cu 1 ................................................................................. 384.2 Chng trnh mu ................................................................................................... 404.3 Bi tp ..................................................................................................................... 42

Bi 5 : K thut qut ma trn phm .............................................................................. 435.1 Kt ni mch ma trn phm..................................................................................... 435.2 Cc bc hin thc ................................................................................................. 445.3 Bi tp ..................................................................................................................... 48

Bi 6 : K thut qut LED............................................................................................ 496.1 Cu to LED 7 on v LED ma trn..................................................................... 496.2 Kt ni mch ........................................................................................................... 516.3 Cc thanh ghi lin quan v cch iu khin............................................................ 526.4 Cc bc hin thc. ................................................................................................ 556.5 Bi tp ..................................................................................................................... 58

Bi 7 : Kho st b truyn nhn ni tip ...................................................................... 597.1 Cc bc hin thc. ................................................................................................ 59


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7.2 Chng trnh mu ................................................................................................... 617.3 Bi tp ..................................................................................................................... 63

Bi 8 : Kho st khi chuyn i A-D.......................................................................... 648.1 Cc bc hin thc ................................................................................................. 648.2 Bi tp ..................................................................................................................... 65

Bi 9 : Kho st cc khi chc nng c bit khc ...................................................... 669.1 Cc bc hin thc PWM....................................................................................... 669.2 Chng trnh mu ................................................................................................... 679.3 Bi tp ..................................................................................................................... 68


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Trng H. Bch Khoa TP.HCM Khoa KH & KTMT

Bi 1 : Gii thiu MPLAB IDE v KIT PIC

Ni dung :To project trn MPLAB IDE.

Vit chng trnh ASM.Dch v np chng trnh vo vi iu khin PIC.Chy v gri chng trnh.

1.1 Phn cng th nghim ICD2 v PICDEM 2 PLUS.

B h trlp trnh dng vi my tnh ICD2 (In-Circuit Debugger).

Cng ni tip

ICD2

USB

Ni vi cardPICDEM

Ni vimy tnh

S kt ni ICD2

Kit th nghim PICDEM 2 Plus c cc c im nh hnh sau :

1. cm DIP 18, 28 v 40 chn (c th cm 3 linh kin nhng ch dng 1 mi ln).2. n p +5V dng cho ngun 9V, 100 mA AC/DC hay pin 9V.3. u cm DB-9 theo chun giao tip RS-232.4. u cm qua b lp trnh In-Circuit Debugger (ICD).5. Bin tr5K dng cho tn hiu nhp tng t.6. Ba nt nhn dng to tn hiu kch t bn ngoi v reset.7. LED ngun.8. Bn LED ch th cho PORTB.9. Jumper J6 ngt LED ch th RB0 (khi nhp tn hiu t nt nhn RB0).

B mn K Thut My Tnh 1 Thc hnh Vi x l


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10.B dao ng (OSC) 4 MHz.11.Ni lp thm thch anh dao ng nu cn.12.Thch anh dao ng 32.768 kHz to xung clock cho Timer1.13.Jumper J7 ngt dao ng RC c sn (khong 2 MHz).14.EEPROM ni tip 32K x 8 bit.

15.Mn hnh LCD.16.Kn Piezo.17.Vng lp thm linh kin.18.Cm bin nhit TC74.

1.2 Mi trng pht trin MPLAB

Bc 1. Chy phn mm MPLAB:Start_|All Programs_|Microchip_|MPLAB IDE v8.00_|MPLAB IDE.

Bc 2. Chn Menu :Project_|Project Wirazd

Chn Nextca s Welcome

Bc 3. Chn s hiu PIC cn s dng (PIC18F4520) ri bm Next:

Chn tool Microchip MPASM Toolsuite ti Active Toolsuite.Bc 4.



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Chn MPASM Assembler (mpasmwin.exe) ti Tollsuite Contents.

Click Next qua ca s k.Bc 5. Nhn Browse chn th mc v nh tn project.

Chn th vin thng qua file .INC v .LKR thm vo project



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C:\Program Files\Microchip\MPASM Suite\LKR\18f4520.lkrC:\Program Files\Microchip\MPASM Suite\P18F4520.INC

Click Next s thy nh sau :

ClickFinish. Ta sc mt project nh hnh sau:



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Bc 6. Thm file vo d n theo cc bc sau :Mt project n gin nht phi gm c 2 thnh phn Source files v Hearder Files.

Th mc Source files cha file text *.asm hoc file *.c cha code lp trnh. Th mcHearder Files cha file *.h hoc *.INC: file c sn ca microchip.

Nu bn qun khng thm cc file cn c vo th lm theo hng dn sau :

ADD header file: ( Copy header file vo th mc cha project tin cho vic sdng sau ny).

ca s la chn

Chn header file ph hp vi PICmnh chn. Open.

ADD source file: Click chn Newtrn toolbar:

Ca s hin ln nh sau: TMenu

bar chn File_|Save lu.

Thc hin Save, t tn viui .asm vo th mc cha dn.

Nhp phi vo Source Fileschn Add file >>> chn filechng ta va to xong.

Chng ta hon tt victhm file vo cc th mcSource files v Header files.



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Cng vic tip theo l vit code (trong ca s text editor ca source file).i vi project ln dng nhiu source file v header file, ta lm li qu trnh thm file

vo d n nhiu ln.

1.3 Np file hex vo viiu khin PIC

Sau khi to c mt project, ta tin hnh build n to ra *.hex. C th m t cngvic nh sau:

V d, ta c mt chng trnh cho PIC nh sau:;===================================================

; Name: BaiTN1.asm

; Project: Nhap du lieu tu nut nhan RA4.; Khi nut RA4 duoc nhan thi led don RB0 sang,

; Khi khong nhan RA4 thi led don RB0 tat

; Author: BKIT HARDWARE CLUB; Homepage: http://www.bkit4u.com/forum

; Creation Date: 7 - 31 - 2009

;===================================================

list p=18f4520#include p18f4520.inccode 0goto start

;vung dinh nghia du lieuudata

;vung dinh nghia cac chuong trinh conPRG codestart call init

;chuong trinh chinhmain

btfsc PORTA,RA4 ;cho nhan nut RA4bra mainbsf LATB,RB0 ;Bat LED RB0

swoffbtfss PORTA,RA4 ;cho nhan nut RA4bra swoffbcf LATB,RB0 ;tat LED RB0bra main ;Lap lai cong viec

;chuong trinh khoi dong ban dau

initbcf TRISB,RB0 ;khoi dong RB0 la cong xuatbsf TRISA,RA4 ;khoi dong RA4 la cong nhapreturnend

By gichng ta lu chng trnh va vit thnh BaiTN1.asm vo mt th mc to project pha trn. compile chng trnh ta vo menu Project_|Build All nh hnhbn di.



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Nu vic build tht bi, nhng vic ny th khng mong mun, ta c thy kt qu nhhnh sau:



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Nu thnh cng, ta s thy hnh sau:

Nu vic build thnh cng, chng trnh s dch BaiTN1.asm thnh BaiTN1.hextrong cng th mc chng trnh BaiTN1.asm. Sau khi c c file hex, cng victip theo l lm th no np c file Hex xung board. u tin, chn mch np bngcch vo menu Programmer_|Select Programmer_|Mplab ICD2 nh hnh sau :

Sau khi chn Mplab ICD2 xong th ta s thy giao din nh sau:



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Mt thao tc cn lm gip ta c th dch chng trnh, np v chy tng l vomenu Programmer_|Settings_|Program chn mc Automatically nh hnh sau :

By gita c th dch, np v chy d n vi thao tc menu Project_|Build All (hocnhn Ctrl-F10).

Nu thnh cng th chng trnh sc dch, np ra card PICDEM v chy ngay.



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Nu tht bi, xem thng tin bo li trong ca s Output khc phc v lm li tbc Build All.

Trng hp thnh cng m chng trnh chy khng ng, ta phi s dng cng cDebugger tm li theo mt trong hai cch sau.

1.4 Debug dng MpLab SIM

Bc 1. Chn Debugger bng menuDebugger_|Select Debugger_|Mplab SIM

Bc 2. Tham kho menu Debugger. Xut hin nhiu chc nng h trdebug.

Ty ta c th m phng c chng trnh ca mnh mt cch d dng.

Cc chc nng thng dng :Run (F9): chy chng trnh, chng trnh s chy lin tc n khi no cbreakpoint th dng.Breakpoints (F2): to ra breakpoint ti v tr hin ti ca con tr (cng c th

"double click" vo hng code mnh mong mun t Breakpoint).Step Into (F7): chy tng bc, vo trong chng trnh con (nu gp).Step Over (F8): chy tng bc, gi chng trnh con cng xem nh 1 bc.Reset: trvu chng trnh.



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Bc 3. Khi debug th ta cng cn phi bit gi tr ca cc thanh ghi cng nh b nhca chip nh th no, xem c cc gi tr ny th chng ta qua menu View.

xem c gi tr ca cc thanh ghi trong PIC ta chn menu View_|File registerss xut hin ca s nh hnh sau:

xem c gi tr ca cc thanh ghi SFR th ta chn View_|Special FunctionRegisters s xut hin ca s nh hnh sau:

Hay xem mt v thanh ghi m ta quan tm th c th dng Watch xem bngcch vo menu View_|Watch th hnh sau s xut hin:

Mun xem thanh ghi no, ta ch vic chn thanh ghi tng ng trong combobox bntrn, sau nhn Add SFR.



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1.5 Debug onchip dng Mplab ICD2.

Cng ging nh debug trn Mplab SIM, Mplab ICD2 cng c nhng tnh nng tngt, nhng khi s dng Mplab ICD2 th cn phi c mch debug, v cc hin tng xy raging nh khi chy thc t.

1.6 Bi tpCi tin chng trnh BaiTN1.asm khi nhn RA4 s thy 4 LED t RB3 n RB0sng nhu ra mt bm 4 bit nh phn tng dn (mi ln nhn tng 1).



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Bi 2 : Kho st cng xut nhp

Ni dung:Kho st hot ng ca nt nhn, LED.Kho st cc thanh iu khin cng xut nhp.Tnh ton thi gian thc thi lnh, vit chng trnh con lm nhim v delay.Vit chng trnh kim tra nt nhn v hin th kt qu kim tra ra LED.

Yu cu:Vit chng trnh xut d liu ra 4 led n m t 0 -> 15 -> 0. Thi gian gia

cc ln m ln 1 n v l 1s.Nhp d liu t nt nhn RA4. Khi nt RA4 c nhn th led n RB0 sng,

khi khng nhn RA4 th led n RB0 tt.

2.1 Kin thc lin quan

2.1.1 Cc thanh ghi iu khin cng xut nhpMi Port c ba thanh ghi iu khin hot ng chnh:Cc bit trong thanh ghi TRIS: thit lp chn tng ng l ng vo (logic 1) hoc

ng ra (logic 0).Cc bit trong thanh ghi PORT: c mc logic t chn tng ng.Cc bit trong thanh ghi LAT: ghi mc logic ra chn tng ng.

2.1.2 Kt ni mchV tr LED hin th v nt nhn trn board nh hnh di y:



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LED hin th c kt ni nh sau:

Mun cc LED sng, cc chn RBi tng ng phi ln mc 1. Ring LED D2 cnphi ni jumper J6 li mi sng c khi RB0=1.

L do c jumper JP6 l do chn RB0 cn c dng lm ng nhp nt nhn RB0.

Nh vy, lc no mun dng chn RB0 l ng xut LED th ng jumper JP6 li.Ngc li, hJP6 s dng RB0 lm ng nhp nt nhn.Cc nt nhn c kt ni nh sau:

Nt nhn RA4, RB0 khi c nhn s lm cho chn tng ng mc logic 0.Cn thit lp cc chn RA4 v RB0 l ng vo.

B dao ng chnh l b dao ng ngoi tn s 4 MHz c kt ni nh sau:

Trn kit th nghim, thch anh Y2 c s dng cho tt c cc bi th nghim.

2.2 Cc bc hin thc yu cu 1Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Led_don,

to file led_don.asm v chn chip 18f4520. Ta c hnh sau:



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Bc 2. Include file p18f4520.inc vo file led_don.asm.Bc 3.

Bc 4.

Khi to PORTB l cng xut cc bit RB0-RB3.init clrf PORTB ;

bcf TRISB,RB0 ; RB0 xutbcf TRISB,RB1 ; RB1 xutbcf TRISB,RB2 ; RB2 xutbcf TRISB,RB3 ; RB3 xutreturn

Bc 5.

To hm delay1ms c s dng bin delay (nh ngha trong udata) nh sau :udata

delay res 1 ; nh ngha bin delay. . .

delay1ms ; Gn ng 1 ms vi xung clock 4 MHzclrf delay ; xa bin delay (vng lp 256 ln)

dl_1 nop

decfsz delaybra dl_1return

Ty ta c th to ra c hm delay1s bng cch gi hm delay1ms 1000 lndelay1s movlw .4

movwf delay_1sadl_2 movlw .250 ; bt u vng lp ngoi



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movwf delay_1sbdl_3 call delay1ms ; bt u vng lp trong

decfsz delay_1sbbra dl_3 ; kt thc vng lp trong (250 lan)decfsz delay_1sa

bra dl_2 ; kt thc vng lp ngoi (4 ln)return

Bc 6. Vit chng trnh cho hm begin thc hin cc yu cu ca bi :begin incf LATB

call delay1sbra begin ; lp li sau mi giy

2.3 Chng trnh mu yu cu 1;=====================================;; Name: led_don.asm

; Project: Xut d liu ra 4 led n m t 0

15

0.; Thi gian gia cc ln m ln 1 n v l 1s.; Author: BKIT HARDWARE CLUB; Homepage: http://www.bkit4u.com/forum; Creation Date: 7 - 31 - 2009;======================================;


; Vung du lieuudata

delay res 1delay_1sa res 1delay_1sb res 1; Vung bat dau codePRG codestart call init; chuong trinh chinhbegin incf LATB

call delay1sbra begin ; lap lai sau moi giay

; Ham khoi dong ban dauinit clrf PORTB ;

bcf TRISB,RB0 ; cau hinh RB0 xuatbcf TRISB,RB1 ; cau hinh RB1 xuatbcf TRISB,RB2 ; cau hinh RB2 xuatbcf TRISB,RB3 ; cau hinh RB3 xuatreturn



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; Ham lam tre 1ms voi tan so dao dong 4MHzdelay1ms ; Gan dung voi xung clock 4 MHz

clrf delay ; xoa bien delay (vong lap 256 lan)dl_1 nop

decfsz delay

bra dl_1return; Ham lam tre 1s = 1000 x 1msdelay1s movlw .4

movwf delay_1sadl_2 movlw .250 ; bat dau vong lap ngoai (4 lan)

movwf delay_1sbdl_3 call delay1ms ; bat dau vong lap trong (250 lan)

decfsz delay_1sbbra dl_3 ; ket thuc vong lap trongdecfsz delay_1sa

bra dl_2 ; ket thuc vong lap ngoaireturnend

Sau khi c chng trnh mu ta thc hin vic compile chng trnh v np xungmch chy chng trnh nh hng dn chng 1.

2.4 Cc bc hin thc yu cu 2Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Nut_nhan

v chn chip 18f4520. Ta c hnh sau:



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Include filep18f4520.inc vo file nut_nhan.asm.Bc 2.Bc 3.

Bc 4.

Khi to PORTB bit RB0 l cng xut (jumper JP6 ng) v PORTA bit RA4l cng nhp.

init clrf PORTBbcf TRISB,RB0 ; RB0 xut

bsf TRISA,RA4 ; RA4 nhpreturnVit chng trnh cho hm main thc hin yu cu ca bi

main btfsc PORTA,RA4 ; chn khi RA4 c nhnbra mainbsf LATB,RB0 ; bt sng LED RB0

swoff btfss PORTA,RA4 ; chn khi RA4 c nhbra swoffbcf LATB,RB0 ; tt LED RB0bra main ; lp li qu trnh

2.5 Chng trnh mu yu cu 2;=====================================;

; Name: nut_nhan.asm

; Project: Nhp dliu tnt nhn RA4.; Khi nt RA4 c nhn th ledn RB0 sng,; Khi khng nhn RA4 th ledn RB0 tt; Author: BKIT HARDWARE CLUB; Homepage: http://www.bkit4u.com/forum


;======================================;


; Vung du lieuudata

; Chuong trinh nay khong su dung bien; Vung bat dau codePRG codestart call init; chuong trinh chinhmain btfsc PORTA,RA4 ; cho den khi RA4 duoc nhan

bra main

bcf LATB,RB0 ; bat sang LED RB0swoff btfss PORTA,RA4 ; cho den khi RA4 duoc nha

bra swoffbcf PORTB,RB0 ; tat LED RB0goto main ; lap lai qua trinh

; Ham khoi dong ban dauinit clrf PORTB

bcf TRISB,RB0 ; RB0 xuat



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bsf TRISA,RA4 ; RA4 nhapreturnend




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2.6 Bi tpa) Vit chng trnh khi nhn RA4 th cc led s sng m ln, mi ln nhn m

ln 1 n v.b) Vit chng trnh sao cho mi ln nhn RA4 th 2 led tri v 2 led phi thay nhau

sng.c) To hiu ng light river trn 4 led ca board mch starter kit. Nhn RA4 thay

i chiu ca light river.



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Bi 3 : Kho st c ch ngt qung, giao tip LCD k t

Ni dung:

Kho st cc nguyn nhn gy ngt qung, cch x l ngt qung, tnh u tingia cc ngt ca vi iu khin PIC 18F4520.Kho st ngt ngoi ca vi iu khin PIC 18F4520.iu khin LCD k t 2 x 16.

Yu cu:1. Vit chng trnh khi to 2 ngt:

Ngt ngoi INT0 (nhn ngt qua nt nhn RB0, Jumper JP6 h) vi u tincao. Ngt timer 0 vi u tin thp.

Trong chng trnh ngt ngoi INT0 bt 3 led n RB1, RB2, RB3 sng cng lc.Trong chng trnh timer 0 sau 1s khi 3 led c bt trong ngt ngoi th tt 3

led n RB1, RB2, RB3 cng lc.2. Vit chng trnh hin th k t ln LCD.

3.1 Kin thc lin quan3.1.1 Tm tt cc thanh ghi iu khin ngtThanh ghi INTCON:

Thanh ghi PIE1:

Thanh ghi PIE2:

Thanh ghi PIR1:

Thanh ghi PIR2:



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Siu khin ngt:

3.2 Cc bc hin thc yu cu 1Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Interrupt,

to file interrupt.asm v chn chip 18f4520. Ta c hnh sau:

Bc 2. Include file p18f4520.inc vo file interrupt.asmBc 3. Khi to PortB l output s dng cc lnh clrf, bcf

init clrf LATB ; RB1-RB3 la cong xuatbcf TRISB,RB1



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bcf TRISB,RB2bcf TRISB,RB3movlw .10 ; khoi dong bien delay=10movwf delayreturn

Bc 4.

Bc 5.

Khi to timer 0 to ngt 100 ms (vi xung clock 4 MHz, chn prescaler 2:1, sm 50000), cho ngt timer 0 c u tin thp.init_timer0

bsf RCON,IPEN ; cho phep uu tien ngat.bcf INTCON2,TMR0IP ; timer0 uu tien thapbcf INTCON,TMR0IF ; xoa co ngat timer0bsf INTCON,TMR0IE ; cho phep ngat timer0bsf INTCON,GIEH ; cho phep ngat uu tien caobsf INTCON,GIEL ; cho phep ngat uu tien thapclrf T0CON ; prescaler 2:1movlw HIGH (-50000) ; nap so dem 50000 cho timer0

movwf TMR0Hmovlw LOW (-50000)movwf TMR0Lbsf T0CON,TMR0ON ; cho phep timer0 demreturn

Bc 6.

Khi to ngt ngoi 0 tch cc cnh xung.i vi ngt ngoi INT1 v INT2, u tin ph thuc vo 2 bit INT1IP v INT2IP

trong thanh ghi INTCON3. Cn vi ngt ngoi INT0 th u tin lun l cao.init_int0

bcf INTCON2,INTEDG0 ; tac dong canh xuongbcf INTCON,INT0IF ; xoa co ngatbsf INTCON,INT0IE ; cho phep ngat ngoai INT0return

Bc 7.

Vit chng trnh cho ngt ngoi 0, bt 3 n led n cng sng v khi to ligi tr cho bin delay 1s sau th ngt timer s tt 3 n .

int0_isrbcf INTCON,INT0IFbsf LATB,RB1bsf LATB,RB2bsf LATB,RB3movlw .10movwf delayreturn

Vit chng trnh cho ngt timer0, sau 1s sau khi led c bt sng th n slm cho led tt.

Thi gian timerm ln 1 n vc tnh bng cng thc :t = (1/(Focs/4))*prescaler = (1/(4Mhz/4))*2) =2s

Nh vy, mun c thi khong 100 ms (100000s), ta cn m 50000 ln.timer0_isr

bcf INTCON,TMR0IF



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decfsz delay,1bra timer0_isr_1bcf LATB,RB1bcf LATB,RB2bcf LATB,RB3

movlw .10movwf delaytimer0_isr_1

bcf T0CON,TMR0ONmovlw HIGH (-50000) ; nap lai so dem 50000 cho timer0movwf TMR0Hmovlw LOW (-50000)movwf TMR0Lbsf T0CON,TMR0ON ; cho phep timer0 dem laireturn

3.3 Chng trnh mu yu cu 1;=====================================;

; Name: led_don.asm

; Project: Vit chng trnh khi to 2 ngt:; -Ngt ngoi 0 vi u tin cao.; -Ngt timer 0 vi u tin thp.; -Ngt INT0 : bt 3 ledn RB1, RB2, RB3 sng cng ;lc; -Ngt timer0 : tt 3 ledn RB1, RB2, RB3 sau 1s; Author: BKIT HARDWARE CLUB

; Homepage: http://www.bkit4u.com/forum

; Creation Date: 7 - 31 - 2009;======================================;

list p = 18f4520#include P18f4520.inccode 0goto mainorg 08Hgoto isr_highorg 18Hgoto isr_low

; Vung du lieuudata

delay res 1; Vung bat dau codePRG codemain

call initcall init_timer0call init_int0goto $



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; Ham khoi dong ban dauinit clrf LATB ; RB1-RB3 la cong xuat

bcf TRISB,RB1bcf TRISB,RB2bcf TRISB,RB3

movlw .10 ; khoi dong bien delay=10movwf delayreturn

; Ham khoi dong timer0init_timer0

bsf RCON,IPEN ; cho phep uu tien ngat.bcf INTCON2,TMR0IP ; timer0 uu tien thapbcf INTCON,TMR0IF ; xoa co ngat timer0bsf INTCON,TMR0IE ; cho phep ngat timer0bsf INTCON,GIEH ; cho phep ngat uu tien caobsf INTCON,GIEL ; cho phep ngat uu tien thap

clrf T0CON ; prescaler 2:1movlw HIGH (-50000) ; nap so dem 50000 cho timer0movwf TMR0Hmovlw LOW (-50000)movwf TMR0Lbsf T0CON,TMR0ON ; cho phep timer0 demreturn

; Ham khoi dong int0init_int0

bcf INTCON2,INTEDG0 ; tac dong canh xuongbcf INTCON,INT0IF ; xoa co ngatbsf INTCON,INT0IE ; cho phep ngat ngoai INT0return

; Ham xu ly ngat timer0timer0_isr

bcf INTCON,TMR0IFdecfsz delay,1bra timer0_isr_1bcf LATB,RB1bcf LATB,RB2bcf LATB,RB3movlw .10movwf delay

timer0_isr_1bcf T0CON,TMR0ONmovlw HIGH (-50000) ; nap lai so dem 50000 cho timer0movwf TMR0Hmovlw LOW (-50000)movwf TMR0Lbsf T0CON,TMR0ON ; cho phep timer0 dem lai



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return; Ham xu ly ngat int0int0_isr

bcf INTCON,INT0IFbsf LATB,RB1

bsf LATB,RB2bsf LATB,RB3movlw .10movwf delayreturn

; Ham xu ly ngat uu tien caoisr_high

call int0_isrretfie

; Ham xu ly ngat uu tien thapisr_low

call timer0_isrretfieend


3.4 LCD k t2x163.4.1 Hnh dng v ngha cc chn:

Tn chn Mc logic M tGND - t (0V)VCC - Ngun (+5V)VEE - Chnh contrast (0 VCC)RS 0

1D0-D7 l gi tr lnh

D0-D7 l gi tr d liuR/W 0

1Ghi gi tr vo LCD

c gi tr ra t LCD



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E 01

T 1 xung 0

Cm truy xut LCDLCD hot ng trao i d liu

D liu/Lnh a vo LCDD0 0/1 Bit 0/LSBD1 0/1 Bit1

D2 0/1 Bit2D3 0/1 Bit3D4 0/1 Bit4D5 0/1 Bit5D6 0/1 Bit6D7 0/1 Bit7/MSBA - Chn Anode ca n nnK - Chn Cathode ca n nn

3.4.2 T chc vng nh ca LCDDisplay Data Ram (DDRAM): lu tr m k t hin th ra mn hnh. M ny ging

vi m ASCII. C tt c 80 nhDDRAM. Vng hin th tng ng vi ca s gm 16 nhhng u tin v 16 nh hng th hai. Chng ta c th to hiu ng dch chbng cch s dng lnh dch (m t sau), khi ca s hin th s dch em li hiu ngdch ch.

Character Generator Ram (CGRAM): lu tr tm mu k t do ngi dng nhngha. Tm mu k t ny tng ng vi cc m k t D7-D0 = 0000*D2D1D0 (* manggi tr ty nh 0 hay 1).



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Character Generator Rom (CGROM): lu tr cng cc mu k t tng ng vi mASCII. Di y l bng nh x gia m k t v mu k t.



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Chng ta mun hin th ch CE gia hng u tin, gi s ca s hin thangbt u t v tr u tin (hng th nht hin th d liu ca nht 0x00 n 0x0f, hng

th hai hin th d liu ca nht 0x40 n 0x4f, y l v tr home). Gi tr ca nh0x07 l 0x43 (k t C), ca nh0x08 l 0x45 (k t E).

Chng ta mun hin th ch gi hng th hai, gi s c s hin thang v trhome. Trong bng mu k t chng ta thy khng c mu . Lc ny chng ta phinh ngha mu 5x8 im, gm c 8 byte, sau lu vo v tr ca mu k tCGRAM th nht. Lc ny gi tr ca nh0x47 l 0x00 hoc 0x08 (v tr ca mu kt CGRAM th nht ).



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3.4.3 Cc lnh giao tip vi LCD

Lnh RS RW D7 D6 D5 D4 D3 D2 D1 D0Thi gianthc thi

Clear display0 0 0 0 0 0 0 0 0 1 1.52ms

Return home0 0 0 0 0 0 0 0 1 * 1.52ms

Entry mode set0 0 0 0 0 0 0 1 I/D SH 37s

Display on/offcontrol

0 0 0 0 0 0 1 D C B 37s

Cursor/Displayshift

0 0 0 0 0 1S/C

R/L

* * 37s

Function set0 0 0 0 1 DL N F * * 37s

Set CGRAMaddress

0 0 0 1 CGRAM address 37s

Set DDRAMaddress

0 0 1 DDRAM address 37s

Read BUSY flag(BF)

0 1 BF DDRAM address 0s

Write toDDRAM or

CGRAM1 0 D7 D6 D5 D4 D3 D2 D1 D0 43s

Read fromDDRAM or

CGRAM

1 1 D7 D6 D5 D4 D3 D2 D1 D0 43s

Cc bit trn bng tm tt cc lnh c ngha nh sau:

I/D 1 Increment 0 DecrementSH 1 Entire shift on 0 Entire shift offS/C 1 Display shift 0 Cursor moveR/L 1 Shift to the Right 0 Shift to the LeftDL 1 8 bits 0 4 bitsN 1 2 Lines 0 1 LinesF 1 5x10 dots Font 0 5x8 dots FontBF 1 Internally operating 0 Can accept instruction

Trn kit th nghim LCD k t 2x16 c kt ni vo Port D ch 4 bit. ch4 bit, c hay ghi mt byte phi tin hnh ci d liu hai ln, ln u l 4 bit cao, lnth hai l 4 bit thp.



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3.4.4 Khi to LCDS kt ni LCD:

Q2MMBT2222A

VCC

R20 2.2KRD7

RD4RD5RD6

Vss1

Vdd2

Vee3

RS4

R/W5

E6

D07

D18

D29

D310

D411

D512

D613

D714

A

15

LCD1

RD3RD2RD1RD0

K16 LCD k t 2x16

Trc khi xut k t ra mn hnh LCD, LCD controller phi c khi to khi mic cp ngun. Trnh t khi to nh lc sau. Trn lc , lnh Display clear cgi tr 0x01 c gi hai ln, ln u l 4 bit cao c gi tr 0x0, ln th hai l bn bit thpc gi tr 0x01. Lnh Function set gi hai ln gi tr 0x2.



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Bt ngun(chn PD7 out ra mc logic 1)

Ch ti thiu 30ms(i VDD > 4.5V)

Gi lnhFunction set

RS RW D7 D6 D5 D4

0 0 0 0 1 0

0 0 0 0 1 0

0 0 N F * *

Ch ti thiu 39s

0 0 0 0 0 0

0 0 1 D C B

Ch ti thiu 39s

0 0 0 0 0 0

0 0 0 0 0 1

Kt thc khi to

0 0 0 0 0 0

0 0 0 1 I/D SH

Gi lnhDisplay on/off control

RS RW D7 D6 D5 D4

Gi lnhEntry mode set

RS RW D7 D6 D5 D4

Gi lnhDisplay clear

RS RW D7 D6 D5 D4

3.5 Cc bc hin thc yu cu 2Bc 1. To project mi ging nh hng dn chng 1 ly tn project l LCD, to

file lcd.asm v chn chip 18f4520. Ta c hnh sau:



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Bc 2. Include file p18f4520.inc vo file lcd.asmBc 3.

Bc 4.

Da vo s nguyn l kt ni vi iu khin vi LCD k t ta define li ddng s dng hn.

#define LCD_D4 LATD, RD0 ; LCD data bits#define LCD_D5 LATD, RD1#define LCD_D6 LATD, RD2#define LCD_D7 LATD, RD3

#define LCD_D4_DIR TRISD, RD0 ; LCD data bits#define LCD_D5_DIR TRISD, RD1#define LCD_D6_DIR TRISD, RD2#define LCD_D7_DIR TRISD, RD3

#define LCD_E LATD, RD6 ; LCD E clock#define LCD_RW LATD, RD5 ; LCD read/write line#define LCD_RS LATD, RD4 ; LCD register select line

#define LCD_E_DIR TRISD, RD6#define LCD_RW_DIR TRISD, RD5#define LCD_RS_DIR TRISD, RD4

#define LCD_INS 0#define LCD_DATA 1

Vit hm xut d liu 4 bit ra cho LCD k t :LCDWriteNibble



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btfss STATUS, C ; Set theregister select

bcf LCD_RS btfsc STATUS, C bsf LCD_RS

bcf LCD_RW ; Set writemode bcf LCD_D4_DIR ; Set data bits to

outputs bcf LCD_D5_DIR bcf LCD_D6_DIR bcf LCD_D7_DIR NOP ; Small NOP bsf LCD_E ; Setup to clock data NOP ; Small

NOP btfss temp_wr, 7 ; Set highnibble

bcf LCD_D7 btfsc temp_wr, 7 bsf LCD_D7 btfss temp_wr, 6 bcf LCD_D6 btfsc temp_wr, 6 bsf LCD_D6 btfss temp_wr, 5 bcf LCD_D5 btfsc temp_wr, 5 bsf LCD_D5 btfss temp_wr, 4 bcf LCD_D4 btfsc temp_wr, 4 bsf LCD_D4 NOP ; Small NOP bcf LCD_E ; Send the datareturn

Bc 5. Tip tc ta vit hm truyn lnh (command) cho lcd k t.Macro LCDWrite_command c mt i s l data, ta dng i s ny truyn lnh

cho lcd. y, LCD ta thit lp ch 4 bt nn khi truyn lnh n cng ch cn 4 bit iu khin. Trong macro ny data1 ch s dng 4 bit cao m thi.

LCDWrite_command macro data1 bcf LCD_RS ;write commandmovlw data1



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lil11movlw 0xFFmovwf delayrcall DelayXCyclesdecfsz COUNTER,F

bra lil11LCDWrite_command 0x20LCDWrite_command 0x20LCDWrite_command 0x80LCDWrite_command 0x00LCDWrite_command 0xf0LCDWrite_command 0x00LCDWrite_command 0x10call LongDelay ;2mscall LongDelay ;2ms

LCDWrite_command 0x00LCDWrite_command 0x20

call Lcd_clearreturn

Bc 8. n y ta c th vit chng trnh hin th k t ln lcd k t. tng thc hin y l lc u ta khai bo mt vng nhgm 32 nh tng

ng vi 32 v tr trn lcd k t. Hm lcd_display ca chng ta s thc hin mt vic ngin l ly d liu cha trong vng nh ny ra hin th ln lcd k t. Cn ngi dngmun hin th ln lcd th ch cn update gi tr vo vng nhny l xong.

Lcd_displaymovff INDF0,temp_wr1movlw .0cpfseq temp_wr1goto Lcd_display1movlw 0x20movwf temp_wr1

Lcd_display1LCDWrite_data temp_wr1

INCF FSR0LCLRF WREGADDWFC FSR0H,F

MOVLW .0cpfseq flag_linegoto Lcd_display_line2

;display line1INCF index_of_lcdMOVLW MAX_INDEX



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CPFSEQ index_of_lcdGOTO Exit_Lcd_displayCLRF Index_of_lcdMOVLW .1MOVWF flag_line

Set_cursor .0,.1goto Exit_Lcd_display

;display line2Lcd_display_line2

INCF index_of_lcdMOVLW MAX_INDEXCPFSEQ index_of_lcdGOTO Exit_Lcd_displayCLRF Index_of_lcdMOVLW .0

MOVWF flag_lineMovlw HIGH Lcd_bufferMovwf FSR0HMovlw LOW Lcd_bufferMovwf FSR0LSet_cursor .0, .0

Exit_Lcd_displayRETURN

3.6 Bi tpa) Vit chng trnh chy ch qua LCD.b) Vit chng trnh thay i ch hin th trn LCD khi nhn nt.



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Bi 4 : Kho st bnh thi

Ni dung:

Kho st cc ch hot ng ca cc bnh thi.Kho st cc thanh ghi iu khin bnh thi.S dng bnh thi trong chng trnh.

Yu cu:S dng b timer 1 c sau 1s m ln 1 n v ri xut gi tr ra led n.Vit chng trnh s dng bnh thi lm ng hiu khin n giao thng.

4.1 Cc bc hin thc yu cu 1Bc 1. To project mi ging nh hng dn chng 1 ly tn project l timer v

chn chip 18f4520. Ta c hnh sau:

Include filep18f4520.inc vo file timer.asmBc 2.Bc 3.

Bc 4.

Khi to PORTB l cng xut.init clrf PORTB ; ton b PORTB l cng xut

clrf TRISB

returnKhi to cc vector ngt.a ch 0x00 bt u chng trnh chnh.a ch 0x08 a ch ca vector ngt c u tin caoa ch 0x18 a ch ca vector ngt c u tin thp.

code 0goto mainorg 0x000008 ; high priority interrupt vector



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goto isr_highorg 0x000018 ; low priority interrupt vectorgoto isr_low

; Vung du lieuudata

bien res 1; Vung bat dau codePRG codemain

call init. . .

;interrupt sevice routine for high priority interruptisr_high . . .

retfie;interrupt sevice routine for low priority interruptisr_low . . .

retfieBc 5.

Bc 6.

Khi to ngt timer0 pht ra ngt 100ms (vi xung clock 4 MHz, chn prescaler2:1, sm 50000).

;=====================;

; Initializing timer 0: 16BIT

;=====================;init_timer0

bsf RCON,IPEN ; cho phep uu tien ngat.bcf INTCON2,TMR0IP ; timer0 uu tien thapbcf INTCON,TMR0IF ; xoa co ngat timer0

bsf INTCON,TMR0IE ; cho phep ngat timer0bsf INTCON,GIEH ; cho phep ngat uu tien caobsf INTCON,GIEL ; cho phep ngat uu tien thapclrf T0CON ; prescaler 2:1movlw HIGH (-50000) ; nap so dem 50000 cho timer0movwf TMR0Hmovlw LOW (-50000)movwf TMR0Lbsf T0CON,TMR0ON ; cho phep timer0 demreturn

Vit chng trnh con chy trong timer, sau 1s tng gi tr hin th ra ngoi ledn.

V c 100ms th c ngt mt ln, do sau 1s ta tng ln mt gi tr th cn 10 lnngt nh vy, nn ban u ta phi khi to cho bin delay = 10. V y l hm chnh thchin chc nng ca bi tp 1.

timer0_isrbcf INTCON,TMR0IFdecfsz delay,1



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;we have to know something

;1. External clock: 4Mhz (this ex);2. Timer0 Prescaler: 1/2 (this ex)

;cycle of timer0 = 1/((Fexternal/4)/2) = 0.5us

;===========================================;

init_timer0 bsf RCON,IPEN ; cho phep uu tien ngat.bcf INTCON2,TMR0IP ; timer0 uu tien thapbcf INTCON,TMR0IF ; xoa co ngat timer0bsf INTCON,TMR0IE ; cho phep ngat timer0bsf INTCON,GIEH ; cho phep ngat uu tien caobsf INTCON,GIEL ; cho phep ngat uu tien thapclrf T0CON ; prescaler 2:1movlw HIGH (-50000) ; nap so dem 50000 cho timer0movwf TMR0Hmovlw LOW (-50000)

movwf TMR0Lbsf T0CON,TMR0ON ; cho phep timer0 demreturn

;===============================================;

; interrupt service routine for high priority interrupts;===============================================;

isr_high ; high priority isr - do nothingretfie

;===============================================;

;interrupt service routine for low priority interrupts;===============================================;

isr_lowcall timer0_isrretfie

;===============================================;

; Timer0 interrupt service routine

;===============================================;timer0_isr

bcf INTCON,TMR0IFdecfsz delay,1bra timer0_isr_1incf LATBmovlw .10movwf delay

timer0_isr_1bcf T0CON,TMR0ONmovlw HIGH (-50000) ; nap lai so dem 50000 cho timer0movwf TMR0Hmovlw LOW (-50000)



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movwf TMR0Lbsf T0CON,TMR0ON ; cho phep timer0 dem laireturnend

Yu cu 2 ca bi thc hnh ny xem nh bi tp

4.3 Bi tpa) Dng bnh thi to xung vung chu k 10ms, duty cycle 30%.



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Bi 5 : K thut qut ma trn phm

Ni dung:

Kho st cu to, hot ng ca ma trn phm.Tm hiu k thut ly d liu t ma trn phm, chng rung phm nhn.Yu cu:

Vit chng trnh ly d liu t phm nhn sau hin th gi tr ca phm nhnra led n.

5.1 Kt ni mch ma trn phm

1 4

2 3

SW1

1 4

2 3

SW2

1 4

2 3

SW3

1 4

2 3

SW4

1 4

2 3

SW5

1 4

2 3

SW6

1 4

2 3

SW7

1 4

2 3

SW8

1 4

2 3

SW9

1 4

2 3

SW10

1 4

2 3

SW11

1 4

2 3

SW12

1 4

2 3

SW13

1 4

2 3

SW14

1 4

2 3

SW15

1 4

2 3

SW16

RD11

RD02

RD33

RD24

RD55

RD46

RD77

RD68

RE19

RE010

GND11

VCC12

J4

CON12A

ROW2

ROW1

ROW4

ROW3

COLUMN1 COLUMN2 COLUMN3 COLUMN4

COL1 COL2 COL3 COL4

R1

10K

R2

10K

R3

10K

R4

10K

VCC R5100R

R6100R

R7100R

R8100R

COL2COL4ROW2ROW4

COL1COL3ROW1ROW3

VCC

Ma trn phm gm 16 phm nhn kt ni chung 4 hng v 4 ct. Bn ct COL1-COL4ni vo bn bit thp ca Port D D0-D3. Bn hng ROW1-ROW4 ni vo bn bit cao caPort D D4-D7. Bn hng c ni vi in trko ln m bo mc logic 1 khi phmkhng c nhn.



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5.2 Cc bc hin thcBc 1. To project mi ging nh hng dn chng 1 ly tn project l Key v


Include filep18f4520.inc vo file key.asmBc 2.Bc 3. Define cc port tng ng vi hng v ct ca ma trn phm d s dng sau

ny. Da vo s mch ta nh ngha nh sau:



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#define COLUMN_1 PORTD, 0#define COLUMN_2 PORTD, 1#define COLUMN_3 PORTD, 2#define COLUMN_4 PORTD, 3

#define ROW_1 PORTD, 4#define ROW_2 PORTD, 5#define ROW_3 PORTD, 6#define ROW_4 PORTD, 7

Bc 4.

Bc 5.

Khi to input v output cho cc port tng ng. y column l output, cnrow l input. Portb dng hin th led n cng c cu hnh l output.

INIT_IO;assigning PORTB is a digital outputMOVLW 0x0FMOVWF ADCON1

; setup portb for outputsCLRF TRISBCLRF PORTBMOVLW 0x0FMOVWF TRISDMOVLW 0xFFMOVWF PORTDRETURN

Bc 6.

Khi to timer, phn ny chng ta hc t chng 4, ta c th c mt hmkhi to timern gin nh sau:

INIT_TIMER0

BSF RCON,IPEN ;enable priority interrupts.BSF INTCON2,TMR0IPBSF INTCON,TMR0IFBSF INTCON,TMR0IEBSF INTCON,GIEHBSF INTCON,GIELCLRF T0CONMOVLW 0x3cMOVWF TMR0HMOVLW 0xAFMOVWF TMR0LBSF T0CON,TMR0ONRETURN

Vit hm Get_key vi 2 i s. i s th nht c tn l temp_wr, chnh l gitr output tng ng vi cc ct ca ma trn phm, i s th 2 c tn l colchnh l gi tr bt u ca mi ct. V d ct 1 th gi tr bng 0, ct 2 th gitr bng 1, ct 3 th gi tr bng 2 v ct 4 th gi tr bng 3.

GET_KEYBTFSS temp_wr, 0



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BCF COLUMN_1BTFSS temp_wr, 0BSF COLUMN_1BTFSS temp_wr, 1BCF COLUMN_2

BTFSS temp_wr, 1BSF COLUMN_2BTFSS temp_wr, 2BCF COLUMN_3BTFSS temp_wr, 2BSF COLUMN_3BTFSS temp_wr, 3BCF COLUMN_4BTFSS temp_wr, 3BSF COLUMN_4

BTFSC PORTD,4 ;BIT TEST F, SKIP IF SETGOTO NEXT_BUTTON_1MOVLW .0MOVWF KeyReg1GOTO EXIT_GET_KEY

NEXT_BUTTON_1BTFSC PORTD,5 ;BIT TEST F, SKIP IF SETGOTO NEXT_BUTTON_2MOVLW .4MOVWF KeyReg1GOTO EXIT_GET_KEY

NEXT_BUTTON_2BTFSC PORTD,6 ;BIT TEST F, SKIP IF SETGOTO NEXT_BUTTON_3MOVLW .8MOVWF KeyReg1GOTO EXIT_GET_KEY

NEXT_BUTTON_3BTFSC PORTD,7 ;BIT TEST F, SKIP IF SETGOTO NEXT_BUTTON_2MOVLW .12MOVWF KeyReg1

EXIT_GET_KEYMOVFF COL,WADDWF KeyReg1,dRETURN

Bc 7. Da vo hm Get_key trn ta c th hon thin hm Scan_button mt cch ddng. y ta nhc li cch m s l phm nhn d liu ngc trv l ti



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mt thi im ch cho mt ct c tch cc (y l mc 0) sau c ngcgi tr t cc hng. Hng 1 tng ng vi ct 1 l s 0, tng t hng 2 vi ct1 l s 4

Khi nhn phm th s c hin tng rung phm, gii quyt trng hp ny ta cmt cch gii quyt y l c d liu 3 ln lin tip mi ln cch nhau 10ms, sau so

snh 3 gi trc c. Nu 3 gi tr bng nhau th ta xem nh c mt nt nhn cnhn. Trong hm Scan_button ta dng 3 bin KeyReg1, KeyReg2 v KeyReg3 lu gitr ca 3 ln c d liu lin tip, khi kim tra 3 bin ny c gi tr bng nhau th ta s luvo bin KeyReg v xut d liu ra PORTB.

Scan_buttonMOVFF KeyReg2,KeyReg3MOVFF KeyReg1,KeyReg2

MOVLW 0x0EMOVWF temp_wrMOVLW .0

MOVWF COLCALL GET_KEY

MOVLW 0x0DMOVWF temp_wrMOVLW .1MOVWF COLCALL GET_KEY

MOVLW 0x0BMOVWF temp_wrMOVLW .2MOVWF COLCALL GET_KEY

MOVLW 0x07MOVWF temp_wrMOVLW .3MOVWF COLCALL GET_KEY

MOVFF KeyReg1,WCPFSEQ KeyReg2GOTO EXIT_SCAN_BUTTONCPFSEQ KeyReg3GOTO EXIT_SCAN_BUTTON

MOVFF KeyReg,WCPFSEQ KeyReg1GOTO Scan_button1



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GOTO EXIT_SCAN_BUTTONScan_button1

MOVFF KeyReg1,KeyRegCALL Button_process

EXIT_SCAN_BUTTONRETURNBc 8.Nh gii thut trn ni l c mi 10ms th ta c d liu mt ln, cho iu

ny c thc hin d dng th ta phi dng n interrupt timer. Ta khi to mtinterrupt timer c sau 10ms th interrupt mt ln. lm c iu ny cc bnc th xem li chng timer c th lm vic mt cch d dng.

y ch gii thiu cho cc bn l hm Timer0_routine, hm ny c gi tronginterrupt timer v trong hm ny ta gi hm Scan_button trn.

TIMER0_ROUTINE

BCF INTCON,TMR0IF

BCF T0CON,TMR0ONMOVLW 0x3cMOVWF TMR0HMOVLW 0xafMOVWF TMR0LBSF T0CON,TMR0ONCALL SCAN_BUTTONRETURN

5.3 Bi tpa) Ci tin hm chng rung phm, khi nhn 1 phm th phi sau 1 thi gian

TimeOutForKey th mi tch cc phm nhn .b) Vit ng dng ng h casio n gin (hin th gi, ngy, cho php chnh sa

ngy gi) s dng ma trn phm v LCD.



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Bi 6 : K thut qut LED

Ni dung:Kho st cu to, hot ng ca LED 7 on, LED ma trn.Tm hiu k thut qut LED 7 on v LED ma trn.

Yu cu:Vit chng trnh cho php hin th gi tr ra led 7 on v led ma trn.

6.1 Cu to LED 7on v LED ma trnLED 7 on gm c 7 on c nh du: a, b, c, d, e, f, g v mt im dp.

LED 7 on c hai loi l Common Anode v Common Cathode, tng ng cc LEDni chung Anode hay ni chung Cathode.

LED ma trn 8x8 hai mu c b tr thnh 8 hng v 8 ct. Mi im c hai LED.



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Cc LED trn cng mt hng ni chung Anode, cc LED cng loi trn cng mt ctni chung Cathode.



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6.2 Kt ni mch

Row.5

Red.5

Green.5

Red.6

Green.1

Green.6

Green.7

Row.6

Green.8

Row.7

Red.7

Red.1

Row.8

Red.8

Green.2

Row.1

Row.2

GR1

24

RD1

23

RW1

22

GR2

21

RD2

20

RW2

19

GR3

18

RD3

17

GR5

1

RD5

2

RW5

3

GR6

4

RD6

5

RW6

6

GR7

7

RD7

8

RW7

9

GR8

10

RW3

16

GR4

15

RD4

14

RW4

13

RD8

11

RW8

12

ML1LED 8x8x2

Red.3

Green.3

Red.4

Green.4

Row.3

Row.4

ENABLE_LED3

C

E

G

e1 d2

g10

c4

dot5

b6 a7

f9

Vcc

3

Vcc

8

8.

LED3

led7

F

BA

ENABLE_LED4

DC

E

G

e1 d2

g10

c4

dot5

b6 a7

f9

Vcc

3

Vcc

8

8.

LED4

led7

F

BA

DOT

D

G

ENABLE_LED1

DOT

Ee

1 d2

g10

c4

dot5

b6 a7

f9

Vcc

3

Vcc

8

8.

LED1

led7

A

C

F

B

DOT

D

DOT

E

G

ENABLE_LED2

e1 d2

g10

c4

dot5

b6 a7

f9

Vcc

3

Vcc

8

8.

LED2

led7

A

CD

F

B

Red.2

Mch LED mrng gm c 4 LED 7 on v 1 LED ma trn hai mu xanh . Mchc ni vo mt phn ca Port PICtail. D liu c dch ni tip v c ci bi IC74HC595, TPIC6595. Module SPI ca PIC m nhn vic dch d liu ni tip thng quachn d liu SDO v chn clock dch SCK. Sau khi dch 4 byte, tn hiu LATCHchuyn t mc 0 ln mc 1 sy d liu ca 4 byte tm ra 4 byte ng ra QA-QH tngng. Tn hiu CLR_DISP tch cc mc 0 khng cho php hin th.



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U1 TPIC6595

SCK

SDO

VCC

VCC

VCC

R5330R6330

Red.1

R7330

R8330

R1330

Red.4Red.3Red.2

Red.6Red.5

Red.8

Red.7

R2330R3330R4330

Row.2 ENABLE_LED2Row.1 ENABLE_LED1

COM10

V+

9

IN11

IN22

IN33

IN44

IN55

IN66

IN77

IN88

OUT118

OUT217

OUT316

OUT415

OUT514

OUT613

OUT712

OUT811

U3

UDN2981

Row.6Row.5

Row.3 ENABLE_LED3

Row.8Row.7

Row.4 ENABLE_LED4

R13100R14100R15100

Green.1

R16100

Green.3Green.2

R9100

Green.6Green.5Green.4

Green.8Green.7

R10100R11100R12100

LATCHCLR_DISP

R21330R22330

A

R23330

B

R24330

C

R17330

ED

DOTGF

R18330R19330R20330

SDI3

SRCLR8

G9

RCLK12

SRCLK13

SDO18

DRAIN04

DRAIN15

DRAIN26

DRAIN37

DRAIN414

DRAIN515

DRAIN616

DRAIN717

U3 TPIC6595

VCC

SDO

VCC

LATCHSCK

LATCH

SDO9

CLR10

G13

SDI14

SRCLK11 RCLK12

QA15

QB1

QC2

QD3

QE4

QF5

QG6

QH7

U4 74HC595

CLR_DISP

SCK

LATCH

CLR_DISP

SCK

CLR_DISP

SCKLATCH

SDI3

SDO18

SRCLR8

G9

RCLK12

DRAIN04

SRCLK13

DRAIN15

DRAIN26

DRAIN37

DRAIN414

DRAIN515

DRAIN6

16

DRAIN7 17

SDI3

SRCLR8

G9

RCLK12

SRCLK13

SDO18

DRAIN04

DRAIN15

DRAIN26

DRAIN37

DRAIN414

DRAIN515

DRAIN616

DRAIN717

U2 TPIC6595

VCC

GND1 +5V2 RC23 RC14 RC05 RA2

6 RA17 RA08 RC39 RC4

10 RC511 RA312

PICtail

CON12

6.3 Cc thanh ghi lin quan v cch iu khin- Thanh ghi trng thi SSPSTAT:



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- Thanh ghi iu khin SSPCON1:

- S khi module Synchronous Serial Port:

Vi s mch trn, mi ln c mt hng LED LED ma trn hay mt con LED 7on hin th d liu. Li dng hin tng lu nh ca mt, d liu ca mi hng LEDma trn hay mi con LED 7 on c xut ra tun t hng (con) ny n hng (con)khc, chng ta s thy c hnh nh ca c mn hnh ma trn LED hay ca c 4 con

LED 7 on.Khi tt c cc hng LED ma trn v tc c cc con LED 7 on c hin th

(qut) qua mt ln, ta ni hin th mt frame. mt khng cm thy hnh nh b rungth s ln hin th frame trong mt giy phi ln hn 24 ln (thng l 30 ln).

u tin tn hiu CLR_DISP tch cc (mc 0) khng cho LED hin th, sau dchbn byte d liu, tn hiu LATCH chuyn t mc 0 ln mc 1 a d liu mong munsn sn ng ra, cui cng a tn hiu CLR_DISP ln mc 1 cho php LED hin th dliu mong mun. C nh vy lp li chu trnh ny.



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Bn byte d liu c dch ra mi ln c ngha tng ng l d liu ca mt hngLED , d liu ca mt hng LED xanh, d liu ca mt con LED 7 on, iu khinhng (con) LED no hin th.

Cch iu khin c minh ha thng qua hnh sau :

Gi tr ca byte control ch cha nhiu nht mt bit 1. Nh hnh v, cn 12 ln xutd liu (4 byte) cho 1 frame gm c LED ma trn v LED 7 on, 8 ln xut d liu cho1 frame gm ch c LED ma trn (khng quan tm ni dung hin th LED 7 on), 4 ln



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xut d liu cho 1 frame gm ch c LED 7 on(khng quan tm ni dung hin th LEDma trn).

6.4 Cc bc hin thc.Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Led v chn

chip 18f4520. Ta c hnh sau:

Include filep18f4520.inc vo fileLed_matran.asmBc 2.Bc 3.

Bc 4.

Khai bo cc buffer cn thit vit driver cho led. V y ta vit driver nnmi ngi khi s dng nhng module ny s khng s dng nhng hm mchng ta vit trong ny ch c th thao tc trn cc buffer m thi.

GREEN_SCREEN_BUFFER RES .8RED_SCREEN_BUFFER RES .8SEVEN_LED_BUFFER RES .8COLUMN_BUFFER RES .8

INDEX_OF_BUFFER RES .1

RED_DATA RES .1GREEN_DATA RES .1SEVEN_LED_DATA RES .1COLUMN_DATA RES .1

Ngoi ra nhn vo mch ta c th d dng nhn thy c rng d liu cachng ta c truyn theo kiu truyn ng b ni tip, chnh xc hn yngi ta s dng chc nng SPI truyn d liu. Do ta phi cu hnh cho

chip lm sao c th hot ng c ch SPI ny.INIT_SPI

CLRF SSPCON1 ;SET Fspi = f/4BSF SSPCON1,5 ;ENALBLE SPI MODEBCF TRISC,5BCF TRISC,3RETURN



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Trn y ta mi ch khi to module SPI n c th hot ng nhng nhn li smch ta li thy c thm vi kt ni na t vi iu khin ra IC74595. IC ny hotng c th ta cn thm mt chn to clock c th chuyn d liu ni tip ra songsong ca IC ny. Ta define thm cho chn Latch ca IC 74595.

#define LATCH_DIR TRISA,1

#define LATCH_DATA PORTA,1ng thi khi to cc PORT lin quan:INIT

MOVLW 0x0FMOVWF ADCON1

BCF LATCH_DIRBCF LATCH_DATACLRF INDEX_OF_BUFFERRETURN

Bc 5.

Bc 6.

Ngoi ra thc hin c bi ny khng th no thiu timerc, v hin

th ra led ma trn ta phi qut tng ct led trn ma trn led.Khi nhn vo cu to ca ma trn led ta thy hin thc mt hnh g trn matrn led th ta phi qut led, v ti mt thi im ch c th hin th mt ct led m thi.Nhvo hin tng lu nh mt m khi qut vi tn s cao th mt ta s thy nh l ct sng ch khng phi chp nhy na.

Vy lm sao bit c ta qut led vi tn s bao nhiu l hp l. Nh trong phim nhkhi xem phim thc cht ta bit l n ang chy vi tn s l 24 hnh /s. y ta cng gis nh vy, c mn hnh ca led cng chp nhy vi tn s l 24 hnh/s, m mi hnh taphi qut 8 ln v c 8 ct. T ta c th suy ra tn s ta cn phi qut cho mi ct l8x24 ln/s. Ty ta c th d dng tnh c timer ca chng ta cn bao nhiu c thqut led c mt cch d dng.

INIT_TIMER0BSF RCON,IPEN ;enable priority interrupts.BSF INTCON2,TMR0IPBSF INTCON,TMR0IFBSF INTCON,TMR0IEBSF INTCON,GIEHBSF INTCON,GIELCLRF T0CONMOVLW 0x3cMOVWF TMR0HMOVLW 0xAFMOVWF TMR0LBSF T0CON,TMR0ONRETURN

Ban u ta khi to cc buffer hin th cng nh qut ct led. d dngtrong vic s l ta s khi to cho Column_Buffer cc gi tr tng ng lm sao,khi xut ra n ch tch cc mt ct ca led m thi. y gi s tch cc ti mict l tch cc mc cao th ta c th khi to cho Column_buffer cc gi tr sau:0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80.



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Bc 7.

Bc 8.

n y mi s chun b xong, ta c th bt u vit hm hin th d liura led. u tin ta s vit mt macro SPI_transmit vi i s s l gi tr byte sc truyn ni tip ra ngoi.

SPI_TRANSMIT MACRO TEMP_DATA;Has data been received (transmit complete)?

BTFSS SSPSTAT, BFGOTO $-2 ;NoMOVF TEMP_DATA, W ;W reg = contents of TXDATAMOVWF SSPBUFENDM

Bc 9.

Tip theo l lm sao ly d liu t cc buffera vo cc bin tng ngxut ra led. Ta vit thm mt Macro na gm 2 i s l buffer v temp_data.Macro ny s lm nhim v l ly d liu ti v tr (c lu trong binindex_of_buffer) ca buffer lu vo temp_data.

UPDATE_DATA MACRO BUFFER,TEMP_DATAMOVLW HIGH BUFFER

MOVWF FSR0HMOVLW LOW BUFFERMOVWF FSR0L

MOVFF INDEX_OF_BUFFER,WADDWF FSR0L,FCLRF WADDWFC FSR0HMOVFF INDF0,TEMP_DATAENDM

Bc 10.

Nh trn gii thiu xut d liu ra led, ngoi vic dng module SPI xut d liu ta cn phi c thm mt tn hiu clock tc ng ln IC74595 th dliu ni tip ca ta mi chuyn qua song song v hin th ra led. Do ta phivit thm mt hm to clock trn chn define khi ny l Latch_data.

CLOCK_STORAGEBSF LATCH_DATANOPNOPBCF LATCH_DATANOPNOPBSF LATCH_DATARETURN

Cui cng l hm quan trng nht, hm ny c gi trong timer thc hinvic qut led.

DISPLAYCALL INCREASING_INDEXUPDATE_DATA RED_SCREEN_BUFFER,RED_DATAUPDATE_DATAGREEN_SCREEN_BUFFER,GREEN_DATA



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UPDATE_DATASEVEN_LED_BUFFER,SEVEN_LED_DATAUPDATE_DATA COLUMN_BUFFER,COLUMN_DATASPI_TRANSMIT RED_DATASPI_TRANSMIT GREEN_DATA

SPI_TRANSMIT SEVEN_LED_DATASPI_TRANSMIT COLUMN_DATACALL CLOCK_STORAGERETURN

6.5 Bi tpa) Xy dng ng dng cho php s 1234 chy qua cc led 7 on.b) Xy dng ng dng cho php 1 dng ch chy qua led ma trn.



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Bi 7 : Kho st b truyn nhn ni tip

Ni dung:

Kho st cng COM my PC, cc thng s truyn ni tip.Kho st b truyn ni tip ca PIC.Tm hiu cch s dng chng trnh Hyper Terminal truyn nhn ni ti p trn

my PC.Yu cu:

Vit chng trnh giao tip gia my tnh v vi iu khin PIC.

7.1 Cc bc hin thc.Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Uart v


Include filep18f4520.inc vo file uart.asmBc 2.Bc 3. Khi to PortB l output, PORTC.6 l output, PORTC.7 l input.

INIT_PORTCLRF LATB ; Clear PORTB output latchesCLRF TRISB ; Config PORTB as

all outputsBCF TRISC,6 ; Make RC6 an output



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BSF TRISC,7RETURN

Bc 4.

Bc 5.

Khi to cc vector ngtorg 00000h ; Reset Vectorgoto Start

org 00008h ; Interrupt vectorgoto IntVector

StartGOTO $

IntVectorRETFIE

Bc 6.

Khi to cho ngt UART, tc 9600baud ti tn s 4Mhz.

INIT_UARTMOVLW 19h ; 9600 baud @4MHzMOVWF SPBRG

BSF TXSTA,TXEN ;Enable transmit

BSF TXSTA,BRGH ; Select highbaud rate

BSF RCSTA,SPEN ; Enable Serial PortBSF RCSTA,CREN ; Enable

continuous receptionBCF PIR1,RCIF ; Clear RCIF

Interrupt FlagBSF PIE1,RCIE ; Set RCIE

Interrupt EnableBSF INTCON,PEIE ; Enable

peripheral interruptsBSF INTCON,GIE ; Enable global

interruptsRETURN

Vit chng trnh trong ngt thc hin nhim v nhn mt d liu t my tnhtruyn xung sau gi li k t cho my tnh nhn li.

IntVector btfss PIR1,RCIF ; Did USART cause

interrupt?goto ISREnd ; No, some other interruptmovlw 06h ; Mask out unwanted bitsandwf RCSTA,W ; Check for errors



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btfss STATUS,Z ; Was either error status bitset?

goto RcvError ; Found error, flag it

movf RCREG,W ; Get input data

movwf LATB ; Display on LEDsmovwf TXREG ; Echo character backgoto ISREnd ; go to end of ISR, restore

context, return

RcvError bcf RCSTA,CREN ; Clear receiver status bsf RCSTA,CRENmovlw 0FFh ; Light all LEDsmovwf PORTBgoto ISREnd ; go to end of ISR, restore

context, returnISREnd

retfie

7.2 Chng trnh mu;=====================================;

; Name: uart.asm; Project: Vit chng trnh giao tip gia my tnh v vi iu khin PIC.; Author: BKIT HARDWARE CLUB

; Homepage: http://www.bkit4u.com/forum; Creation Date: 8 - 8 - 2009

;======================================;

list p=18F4520 ; set processor typeinclude

;************************************************************; Reset and Interrupt Vectors

org 00000h ; Reset Vectorgoto Start

org 00008h ; Interrupt vectorgoto IntVector

;************************************************************; Program begins here



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org 00020h ; Beginning of program EPROMStart

CALL INIT_PORTCALL INIT_UART

Main

goto Main ; loop to self doing nothingINIT_PORT

clrf LATB ; Clear PORTB output latchesclrf TRISB ; Config PORTB as all

outputs bcf TRISC,6 ; Make RC6 an output bsf TRISC,7 ; Make RC7 an inputRETURN

INIT_UART

movlw 19h ; 9600 baud @4MHzmovwf SPBRG

bsf TXSTA,TXEN ; Enable transmit bsf TXSTA,BRGH ; Select high baud rate

bsf RCSTA,SPEN ; Enable Serial Port bsf RCSTA,CREN ; Enable continuous

reception

bcf PIR1,RCIF ; Clear RCIF Interrupt Flag bsf PIE1,RCIE ; Set RCIE Interrupt Enable bsf INTCON,PEIE ; Enable peripheral

interrupts bsf INTCON,GIE ; Enable global interruptsRETURN

;************************************************************; Interrupt Service Routine

IntVector btfss PIR1,RCIF ; Did USART cause

interrupt?goto ISREnd ; No, some other interrupt

movlw 06h ; Mask out unwanted bitsandwf RCSTA,W ; Check for errors btfss STATUS,Z ; Was either error status bit

set?



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goto RcvError ; Found error, flag it

movf RCREG,W ; Get input datamovwf LATB ; Display on LEDsmovwf TXREG ; Echo character back

goto ISREnd ; go to end of ISR, restorecontext, return

RcvError bcf RCSTA,CREN ; Clear receiver status bsf RCSTA,CRENmovlw 0FFh ; Light all LEDsmovwf PORTBgoto ISREnd ; go to end of ISR, restore

context, return

ISREndretfieend

7.3 Bi tpa) Vit chng trnh trn PC, gi 1 chui string xung board, dng ch ny s chy

qua led ma trn hoc LCD.b) Khi nhn 1 phm trn board nhn, s gi 1 chui string ln PC qua cng COM,

vit chng trnh trn PC nhn chui string ny v in ra giao din.



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Bi 8 : Kho st khi chuyn i A-D

Ni dung:

Kho st hot ng khi chuyn i A-D.Kho st cc thanh ghi iu khin hot ng khi chuyn i A-D.Yu cu:

Vit chng trnh c v hin th gi trin p thay i bi bin tr.

8.1 Cc bc hin thcBc 1. To project mi ging nh hng dn chng 1 ly tn project l a2d v chn

chip 18f4520. Ta c hnh sau:

Include filep18f4520.inc vo file a2d.asmBc 2.Bc 3. Khi to module ADC ta c th s dng mt cch d dng.

InitializeADMovlw B'00000100' ; Make RA0,RA1,RA4 analog inputsmovwf ADCON1movlw B'11000001' ; Select RC osc, AN0

selected,

movwf ADCON0 ; A/D enabledmovlw 0x01movwf ADCON2call SetupDelay ; delay for 15 instruction

cycles bsf ADCON0,GO ; Start first A/D conversionreturn



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khi to c module ADC ta ch cn quan tm ch yu ti cc thanh ghiADCCON1, ADCCON0, ADCON2. Nh chng trnh khi to trn ta thy u tin phicu hnh cho cc pin tng ng phi l chn AN0, mc nh ca cc chn ny c chcnng l Input/Output digital. Sau ta phi chn knh ADC tng ng, y ta s dngknh AD0. V mt im quan trng na chnh l bit GO trong thanh ghi ADCON0, khi

bt ny c bt ln th module AD mi bt u chuyn i tn hiu.Bc 4. Tip theo l hm c gi tr ADC:Update_adc

bsf ADCON0,GO ;start conversion btfsc ADCON0,GO bra $-2movf ADRESH,Wreturn

Sau khi chuyn i tn hiu A-D, gi tr s sc lu vo thanh ghi ADRESH. ny ty vo ng dng c th m ta c th bin i gi tr ny ty theo yu cu m tamong mun.

8.2 Bi tpa) Tch hp module LCD, ly gi trin th t bin trhin th ln LCD.b) S dng module ADC ca Pic o nhit trong phng, dng LCD hin th

gi tr nhit .



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Bi 9 : Kho st cc khi chc nng c bit khc

Ni dung:

Kho st khi chc nng WDT.Kho st khi chc nng PWM .Kho st cc ch hot ng ca vi iu khin.

Yu cu:Vit chng trnh s dng chc nng WDT.Vit chng trnh s dng chc nng PWM iu khin sng ca LED.Vit chng trnh s dng chc nng Power control.

9.1 Cc bc hin thc PWMBc 1. To project mi ging nh hng dn chng 1 ly tn project l pwm v


Include filep18f4520.inc vo filepwm.asm.Bc 2.Bc 3. Tch hp module LCD vo project pwm, tham kho bi tp v LCD.

Bc 4. Khi to module PWM ta c th s dng mt cch d dng.Init_pwm

;configure CCP1 module for buzzer bcf TRISC,2movlw 0x80movwf PR2 ;initialize PWM

period



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movlw 0x80 ;initialize PWM dutycycle

movwf CCPR1L bcf CCP1CON,CCP1X bcf CCP1CON,CCP1Y

;postscale 1:1, prescaler 4, Timer2 ONmovlw 0x05movwf T2CONmovlw 0x0F ;turn buzzer onmovwf CCP1CONreturn

khi to chc nng pwm, u tin ta phi cu hnh cho PORTC2 l output. Tiptheo khi to chu k ca PWM thng qua vic cu hnh thanh ghi PR2. Sau ta khi toduty cycle ca xung pwm bng cch cu hnh thanh ghi CCPR1L.

9.2 Chng trnh mu;=====================================;; Name: pwm.asm

; Project: Su dung Pwm de xuat am thanh ra loa.

; Author: BKIT HARDWARE CLUB; Homepage: http://www.bkit4u.com/forum


;======================================;list p=18f4520#include "p18f4520.inc"

; vectors

org 0x000000 ; reset vector bra START

;************************************************************; programSTART

call Init_pwmgoto $

Init_pwm bcf TRISC,2



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movlw .249movwf PR2 ;initialize PWM

periodmovlw .125 ;initialize PWM duty

cycle

movwf CCPR1L bcf CCP1CON,CCP1X bcf CCP1CON,CCP1Y

;postscale 1:1, prescaler 4, Timer2 ONmovlw 0x05movwf T2CONmovlw 0x0F ;turn buzzer onmovwf CCP1CONreturn

END

9.3 Bi tpa) Tm hiu v hin thc chng trnh iu khin RC Servo.

thi nghiem vi xu ly va vi dieu khien

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