thi nghiem ky thuat so_de1

5/20/2018 Thi Nghiem Ky Thuat So_DE1

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TN KTS-Altera DE1 B mn in T - HBK Tp HCM

Kit th nghim K thut s

Altera DE1


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CC BC TH NGHIM K THUT S TRN KIT ALTERA DE1

Nhp file thit k dng m Verilog

Bin dch

M phng chc nng

NoThit k ng?

Yes

Gn chn

Phn tch v m phng thi gian

Not yu cu thi gian?

Yes

Np kit v th mch

Hnh 1: Cc bc thc hin


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Bc 1. Chy chng trnh Quartus II:

Hnh 2: Mn hnh chnh Quartus II.


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Bc 2. To project mi:

1. Chn File >New Project Wizard:

Hnh 3: File menu.

2. Chn th mc lm vic, t tn cho project ri nhn Next:

Hnh 4: To 1 project mi.


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Nhn Yes.

Hnh 5: Quartus

II to th mc mi cho project.

3. Khng cn phi chn thm file no, nhn NEXT:

Hnh 6: Thm file thit k c sn.

4. Chn chip CycloneII EP2C20F484C7N, nhn NEXT.

Hnh 7: Chn chip FPGA.


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5. Khng cn chn EDA TOOL no, nhn Next:

Hnh 8: Chn EDA tools.

6. Bng tm tt cc thng s ci t cho project nh hnh 9. Nhn Finish

Hnh 9: Tm tt cc thng s ci t cho project.


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Chng trnh s quay tr v mn hnh chnh:

Hnh 10: Mn hnh Quartus II cho project mi c to.


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Bc 3. Nhp file thit k dng m Verilog:

3.1. Chn File > New, chn Verilog HDL File, ri nhn OK.

Hnh 13: Chn Verilog HDL file.


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3.2. To file thit k mi: chn File > Save As, chn Save as type = Verilog HDLFile. t tn cho file. Chn Add file to current project. Nhn Save

Hnh 14: t tn file.

3.3 Nhp chng trnh dng m Verilog vo khung Text Editor.

Lu file: File > Save, hoc nhn Ctrl-S.

Hnh 15: Mn hnh Quartus II sau khi to file.


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C th ty chn cc tnh nng ca Text Editor bng cch chn: Tools > Options > TextEditor.

Hnh 16: Cc ty chn cho Text Editor.

C th dng template nhp chng trnh: Edit > Insert Template > Verilog HDL

3.4. a file thit k vo project: chn Assignments> Settings, chn Fileshoc chnProject > Add/Remove Files in Project

Nu dng Quartus II Text Editor v chn Add file to currentproject nh

trong phn 3.2 th file thit k s c np thng vo project.

Hnh 17: Ty chn cc thng s cho project.


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Nu cha c th phi np nh sau:1. Copy file thit k vo th mc lm vic.2. Nhn nt ... chn file

Hnh 18: Chn file

3. Chn file cn thit ri nhn Open. Sau nhn Add, OK.

Bc 4. Bin dch chng trnh thit k:

4.1 Chn Processing > Start Compilation, hoc nhn nt .

Ch bin dch chng trnh cho n khi bo Successful(hoc unsuccessful) ri nhn OK

Hnh 19: Mn hnh sau khi bin dch thnh cng.


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4.2 Khi bin dch xong chng trnh s t ng hin th Compilation Report. Report nycng c th c m bng cch chn Processing > Compilation Reporthoc nhnnt .

Hnh 20: Kt qu bin dch.

Thng bo li:

Hnh 25: Thng bo bin dch c li.

Hnh 26: Ni dung li.

Hnh 27: Xc nh v tr li


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Bc 5. Gn chn ca project cho kit Altera DE 1:

5.1 Chn Assignments > Import Assignments. Chn file DE1_pin_assignments.csv Nhn OK

Hnh 24. Mn hnh Import Assignments

5.2 Chn Assignments > Assignment Editor. Chn Category = Pin. Double-click vo vt sng highlight mu xanh dng ct To. Ri gn cc chn vo

tng ng.

Hnh 25. Drop-down menu hin th tn cc ng vo, ra.

Lu file thit k.

Hnh 27. Hon tt vic gn chn

Bc 6 . M phng mch thit k:

1. Chn File > New- Chn Vector Waveform File- Nhn OK.

2. Mn hnh Waveform Editor nh Hnh 32. Lu vector waveform file (.vwf) Chn thi gian thc hin m phng t 0 n 200 ns bng cch chn Edit > End Timeri

nhp 200 ns. Chn View > Fit in Window


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Hnh 33. Mn hnh Waveform Editor

3. Chn Edit > Insert Node or Bus.

Hnh 34. Hp thoi Insert Node or Bus.

Nhn ntNode Finder.

Hnh 35. Chn nodes a vo Waveform Editor.

Chn Filter = Pins: allri nhn nt List. Chn nt >>ri nhn OK.

Nhn OKtrong ca s hnh 34.

4. Chn cc gi tr logic ca cc ng vo th. Lu vector waveform file.


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Hnh 37. Chn cc gi tr logic ca cc ng vo th

6.1 Thc hin m phng:(Functional Simulation)

Chn Assignments > Settings chn Simulation mode = Functionalri nhn OK.

Hnh 38. Chn Simulation mode = Functional.

Chn Processing > Generate Functional Simulation Netlist. Bt u thc hin m phng bng cch chn Processing > Start Simulation, hoc nhn nt

Hnh 39. Kt qu m phng.


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Bc 7 . Lp trnh cho FPGA trn kit Altera DE1:

Trn kit DE2 t SW19 = RUN(JTAG mode) Kt ni USB cp t my tnh vi USB-Blastertrn kit DE1. Cp ngun cho kit.

Chn Tools>

Programmer. Chn Mode = JTAG. Chn Hardware = USB-Blastertheo Hnh 42. Chn Check box Program/Configure.

Hnh 41. Mn hnh programing.

Hnh 42. Mn hnh chn hardware.

Nhn nt Start bt u np project vo kit DE1.

Bc 8. Th project va thit k:

Tin hnh th project va c np trn kit DE1.Nu mun thay i thit k trc ht phi tt mn hnh Programmer ri thc hin project mi t b2.


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Bi th nghim 1Switches, Lights, Multiplexers

1. Th nghim 1.1:Thc hin mch th nghim c ng vo l 10 cng tc SW90, v ng ra l 10 n LED mu LEDR90 dng c trthi ca cc ng vo.

// Chung trnh Verilog n gin cho bi TN 1.1:module tn1_1 (SW, LEDR);

input [9:0] SW; // toggle switchesoutput [9:0] LEDR; // red LEDs

assign LEDR = SW;endmodule

Cc bc cn thc hin:

1. To project mi.2. Vit chng trnh Verilog cho bi TN

3. Gn chn & bin dch project.4. Np project vo kit TN. Th mch.

2. Th nghim 1.2:

Cho mch multiplexer 2 sang 1 nh hnh 2vi ng vo chn knhs. Nus = 0 ng ra m s bng ng vo x, v n= 1 th ng ra m =y.

x

m

sy

a) S mch

s

s m

0 x x 0 m1 y y 1

b) Bng s tht c) K hiu

Hnh 2. Mch multiplexer 2 sang 1.

Mch c th m t dng m Verilog nh sau:

assign m = ( s & x)

(s & y);

Dng 4 b multiplexer 2 sang 1 nh hnh 2 thc hin mch multiplexer 2 sang 1 - 4 bit nh hnh 3a. Mch c 2 nvo nh phn 4 bitX v Y, v ng ra 4 bitM. Nus = 0 thM =X, cns = 1 thM = Y.


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s

x3 0 m3y3 1

X3 0 m2 s

Y3 1

4X 0 4

MY 1

4

x0 0 m0

y0 1

a) s mch b) k hiu

Hnh 3. Mch multiplexer 2 sang 1, 4 bit.

Cc bc cn thc hin:

1. To project mi.2. Vit chng trnh Verilog vi:

s = SW9 vni vi LEDR9X = SW3-0 v ni vi LEDR3-0Y = SW7-4 vni vi LEDR7-4M = LEDG3-0

3. Gn chn

4. Bin dch project.5. Np project vo kit TN.6. Th mch bng cch thay i cc cng tc SW ri theo di cc n LED xanh, .

3. Th nghim 1.3:

Dng 3 b multiplexer 2 sang 1 nh hnh 2 thc hin mch multiplexer 4 sang 1 nh hnh 4a.Mch c 4 ng vo u, v, wv x; 1 ng ra m; 2 ng vo chn knhs1s0

s1

s0

u 00

v 11 m

w 0

x 1

a) s mch


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0 0 u0 1 v1 0 w1 1 x

s

x

s1s0 m1

s0

u

v 0001

w 10 m11

x

b) bng s tht c) k hiuHnh 4. Mch multiplexer 4 sang 1

Tng t dng 2 mch multiplexer 4 1 nh hnh 4a thc hin mch multiplexer 4 1 - 2 bit nhhnh 5

s1

s0

U2

2V 00

2 01 2W 10 M

2 11X

Hnh 5. Mch multiplexer 4 sang 1 - 2 bit

Cc bc cn thc hin:

1. To project mi.2. Vit chng trnh Verilog vi:s1s0= SW9-8 vni vi LEDR9-8

U-X = SW7-0 v ni vi LEDR7-0M = LEDG1-0

3. Gn chn

4. Bin dch project.5. Np project vo kit TN.6. Th mch bng cch thay i cc cng tc SW ri theo di cc n LED xanh, .


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4. Th nghim 1.4:

Thc hin b gii m c 2 ng vo c1c0 v 7 ng ra t 0 n 6 dng hin th cc k t trn b hin th 7 onnh hnh 6.Bng 1 lit k cc k t cn hin th (gm H,E,L v k t O) tng ng vi cc ng vo c1c0.Cc ng ra tch cc mc logic 0.

c17-segment

decoderc0

0

56

1

4 2

3

Hnh 6. B gii m 7 on

c1 c0 K t

0 0 H

0 1 E1 0 L1 1 O

Bng 1. Bng m ch

Cc bc cn thc hin:

1. To project mi.2. Vit chng trnh Verilog vi:

o Cc ng vo c1c0 ni vi cc cng tc SW1-0o Cc ng ra 0 6 ni vi HEX00, HEX01..HEX06

3. Gn chn

4. Bin dch project.5. Np project vo kit TN.6. Th mch bng cch thay i cc cng tc SW10ri quan st b hin th 7 on.


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2

2

2

5. Th nghim 1.5:Thc hin mch in hin th ch xoay nh hnh 7 hot ng theo bng 2.Cc cng tc SW70 dng to k t v SW98dng chn k t hin th.

SW9

SW8

SW7 62

SW5 4

SW3 2

SW1 0

0 00 11 01 1

2 7-segmentdecoder

0

75

61

4 2

3

Hnh 7. Mch c th chn & hin th 1 trong 4 k t.

Bng 2. Hin th ch xoay HELLO.

module part5 (SW, HEX0);input [9:0] SW; // toggle switchesoutput [0:6] HEX0; // 7-seg displays

wire [1:0] M;

mux 2bit 4to1 M0 (SW[9:8], SW[7:6], SW[5:4], SW[3:2], SW[1:0], M);char 7seg H0 (M, HEX0);

endmodule

// implements a 2-bit wide 4-to-1 multiplexermodule mux 2bit 4to1 (S, U, V, W, X, M);

input [1:0] S, U, V, W, X;output [1:0] M;

. . . code not shown

endmodule

// implements a 7-segment decoder for H, E, L and Omodule char 7seg (C, Display);

input [1:0] C; // input codeoutput [0:6] Display; // output 7-seg code

. . . code not shown

endmodule

Hnh 8. Chng trnh gi cho mch in hnh 7.

SW9 SW8 Hin th0 0 H0 1 E1 0 L1 1 O


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Binary value

0000

Decimal

0

digits

00001 0 10010 0 2. . . . . . . . .

1001 0 91010 1 01011 1 11100 1 21101 1 31110 1 41111 1 5

Bi th nghim 2Numbers & Displays

y l bi th nghim thit k mch t hp thc hin b bin i s nh phn sang s thp phn v mch

cng hai s BCD.

1. Th nghim 2.1:

Dng cc n 7 onHEX1 vHEX0 hin th cc s thp phn t 0 n 9. Gi tr hin th thay i cbng cc cng tc SW74 v SW30 tng ng.

Cc bc cn thc hin:1. To project mi.2. Vit chng trnh Verilog cho bi TN

3. Gn chn & bin dch project.4. Np project vo kit TN. Th mch bng cch thay i cc cng tc v quan st cc n hin th.

2. Th nghim 2.2:

Thc hin 1 phn ca mch chuyn i s nh phn 4 bit V = v 3v2 v1 v0 thnh s thp phnD = d1 d0 nh hnh1, bng 1. Mch bao gm mch so snh ( kim tra V > 9), mch multiplexer v mch A(cha cn thc hinmch B v b gii m 7 on). Mch s c ng vo V 4 bit, ng ra M 4 bit v ng ra z.

Bng 1. Bng gi tr chuyn i nh phn thp phn .

Cc bc cn thc hin:1. To project mi. Vit chng trnh

2. Bin dch project v thc hin m phng3. Vit thm on chng trnh cho mch B v mch gii m 7 on. Dng cc cng tc SW30

nhp s nh phn V v cc n 7 on HEX1, HEX0 hin th s thp phn d 1 d04. Bin dch li ri np project vo kit TN.5. Th mch: thay i gi tr V v quan st cc n hin th.


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zComparator

v3 0m3

0 1

Circuit B

d1

0

75

61

4 2

3

v2 0m2

1

v1 0

1 m1

v0 0m0

1

7-segment 7decoder

d0

0

56

1

4 2

3

Circuit A

Hnh 1. Mch chuyn i nh phn-thp phn.

3. Th nghim 2.3:

Cho mch cng ton phn (FA) nh hnh 2a vi cc ng vo a, b, and ci, cc ng ras v co.cos = a + b + ci.

Dng 4 mch cng FA nh trn thc hin mch cng 4 bit nh hnh 2d.


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0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

oc

s

ci

a s ci

a FA

b 0 bco

1

a) Mch cng FA b) K hiu

b a ci co s b3 a3 c3b2 a2 c2

b1 a1 c1b0 a0 cin

FA FA FA FA

cout

s3

s2

s1

s0

c) Bng s tht d) Mch cng 4 bit

Hnh 2. Mch cng.

Cc bc cn thc hin:1. To project mi v vit chng trnh Verilog cho mch cng:

Ni cc ng voA,Bv cin vi cc cng tc tng ng SW74 , SW30 v SW8 v vicc n LED mu LEDR

Ni cc ng ra cout v S vi cc n LED mu xanh LEDG

2. Gn chn, bin dch v np project vo kit TN3. Th mch bng cch thay i cc gi tr khc nhau caA, Bv c in, quan st cc n hin th.

4. Th nghim 2.4:

Thc hin mch cng 2 s BCD. Ng vo ca mch l 2 s A, B v ng vo cho s nh cin. Ng ra l s BCDtng S1S0v s nh cout.

Cc bc cn thc hin:1. To project mi cho mch cng s BCD. Phi thc hin mch cng 2 s 4 bit A, B (th nghim 2.3)

v 1 mch chuyn i 5 bit tng s3s2s1s0co thnh 2 s BCD S1S0 (th nghim 2.2)2. Vit chng trnh Verilog:

Ni cc ng voA,Bv cin vi cc cng tc tng ng SW74 , SW30 v SW8 v vi ccn LED mu LEDR70

Ni cc ng ra cout v S vi cc n LED mu xanh LEDG40 Dng cc n 7 onHEX3, HEX2 hin th gi tr ca 2 s A v B vHEX1,HEX0 hin

th kt qu S1S0 .

3. Gn chn, bin dch v np project vo kit TN4. Th mch bng cch thay i cc gi tr khc nhau caA, B v c in, quan st cc n hin th.

5. Th nghim 2.5:

Thit k mch t hp chuyn i 1 s nh phn 6 bit thnh s thp phn di dng 2 s BCD. Dng cc cng tcSW50 nhp s nh phn v cc n 7 onHEX1 vHEX0 hin th s thp phn.


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Bi th nghim 3Latches, Flip-flops, Registers

1. Th nghim 3.1:

Hnh 1 m t mch RS latch dng cng logic.C 2 cch dng Verilog m t mch ny: dng cng logic (hnh 2a) v dng cng thc logic (hnh 2b).

R R_g

Qa (Q)

Clk

Qb

S S_g

Hnh 1. Mch RS latch dng cng logic.

// A gated RS latchmodule part1 (Clk, R, S, Q);

input Clk, R, S;output Q;

wire R_g, S_g, Qa, Qb /* synthesis keep */ ;

and (R_g, R, Clk);and (S_g, S, Clk);

nor (Qa, R_g, Qb);nor (Qb, S_g, Qa);

assign Q = Qa;

endmodule

Hnh 2a. Dng cng logic m t mch RS latch.

// A gated RS latchmodule part1 (Clk, R, S, Q);

input Clk, R, S;output Q;

wire R_g, S_g, Qa, Qb /* synthesis keep */ ;

assign R_g = R & Clk;assign S_g = S & Clk;

assign Qa = (R_g

Qb);assign Qb = (S_g

Qa);

assign Q = Qa;

endmodule

Hnh 2b. Dng cng thc logic m t mch RS latch.


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C 2 cch thc hn: dng 1 LUT 4 ng vo (hnh 3a) v dng 4 LUT 2 ng vo (hnh 3b).

RClk

S4-LUT

Qa (Q)

(a) RS latch ch dng 1 bng tham chiu 4 ng vo.

R4-LUT

R_g

4-LUT

Qa (Q)

Clk

4-LUTS

S_g

4-LUT

Qb

(b) RS latch dng 4 bng tham chiu 2 ng vo.

Hnh 3. Cc cch thc hin mch RS latch

Cc bc cn thc hin:

1. To project RS latch2. Vit chng trnh Verilog theo hai cch 2a v 2b.3. Bin dch. Dng tin ch RTL Viewer so snh vi s mch hnh 1. Dng tin ch Technology

Viewer so snh vi s mch hnh 3b.4. To Vector Waveform File (.vwf) cho cc ng vo/ra. To dng sng cho cc ng vo R v S ri

dng tin ch Quartus II Simulator quan st cc dng sng R_g, S_g, Qav Qb


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2. Th nghim 3.2:

Cho mch D latch dng cng nh hnh 4.

DS S_g

Qa (Q)

Clk

QbR R_g

Hnh 4. Mch D latch dng cng logic.

Cc bc cn thc hin:

1. To project mi vi chng trnh Verilog dng 2b cho mch D latch.2. Bin dch chng trnh. Dng tin ch Technology Viewer kho st mch.3. M phng kim tra hot ng ca mch.4. Dng cng tc SW0 cho ng voD, v SW1 cho ng vo Clk. Ni ng ra Q nLEDR0.5. Bin dch chng trnh li v np project vo kit TN.6. Th mch bng cch thay i cc ng vo D, Clk v quan st ng ra Q.


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3. Th nghim 3.3:

Cho mch master-slave D flip-flop hnh 5.

Master Slave

Qm

Qs

D D Q D Q Q

Clock Clk Q Clk Q Q

Hnh 5. Mch master-slave D flip-flop.

Cc bc cn thc hin:

1. To project mi dng 2 D flip-flop ca th nghim 3.2.2. Dng cng tc SW 0 cho ng voD, v SW1 cho ng vo Clk. Ni ng ra Q nLEDR0.3. Bin dch chng trnh.4. Dng tin ch Technology Viewer kho st mch. M phng kim tra hot ng ca mch.5. Th mch bng cch thay i cc ng vo D, Clk v quan st ng ra Q.

4. Th nghim 3.4:

Cho mch in hnh 6 vi D latch, D flip- flop kck cnh ln v D flip- flop kck cnh xung.


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D D Q Qa

Clock Clk Q Qa

D Q Qb

Q Qb

D Q Qc

Q Qc

(a) S mch

Clock

D

Qa

Qb

Qc

(b) Gin d thi gian

Hnh 6. S mch v dng sng ca th nghim 3.4.

Cc bc cn thc hin:

1. To project mi.2. Vit chng trnh da trn on chng trnh gi nh hnh 7.3. Bin dch chng trnh.4. Dng tin ch Technology Viewer kho st mch.5. M phng kim tra hot ng ca mch. So snh hot ng ca cc phn t trong mch.

module D_latch (D, Clk, Q);input D, Clk;output reg Q;

always @ (D, Clk)if (Clk)

Q = D;endmodule

Hnh 7. Chng trnh gi cho D latch.


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Bi th nghim 4Counters

1. Th nghim 4.1:

Cho mch m ng b 4 bit dng 4 T flip-flops nh hnh 1.

Enable T Q

Clock Q

T Q T Q T Q

Q Q Q

Clear

Hnh 1. B m 4 bit.

Cc bc cn thc hin:

1. To project mi thc hin b m 16 bit dng 4 mch m nh hnh 1. Bin dch chng trnh. Ghi nhns phn t logic (LEs) c dng? Tn s hot ng ti a (Fmax)ca mch m l bao nhiu?

2. M phng hot ng ca mch.3. Gn thm nt nhn KEY0lm ng vo Clock, cc cng tc SW1, SW0 lm ng voEnable, Resetv cc

n 7 onHEX3-0 hin th gi tr thp lc phn ca ng ra mch m.4. Bin dch li v np project vo kit TN.5. Th hot ng ca mch bng cch thay i cc cng tc v quan st cc n 7 on.6. Thc hin mch m 4 bit ri dng tin ch RTL Viewer quan st mch v so snh vi mch in hnh 1.

2. Th nghim 4.2:

Thc hin li th nghim 4.1 dng m Verilog sau:

Q


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3. Th nghim 4.3:

Dng module c sn trong th vin LPM (Library of Parameterized Modules) thc hin mch m 16 bit.Thay i LPM cho ph hp, nh Enable, Reset.

4. Th nghim 4.4:

Thc hin mch ng h m giy t 0 n 9s hin th trn n 7 on HEX 0.Phi thc hin 1 mch m to thi gian 1s t xung clock 50 MHz c sn trn kit TN.

5. Th nghim 4.5:

Thc hin mch hin th ch HELLO ln 4 n 7 on HEX3 0, dch t phi sang tri vi thi khong 1stheo mu nh bng 1.

Clock cycle Displayed pattern

0 H1 H E

2 H E L3 H E L L4 E L L O5 L L O6 L O7 O8 H. . . and so on

Bng 1. n ch chy HELLO.

thi nghiem ky thuat so_de1

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