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TRANSCRIPT
Thermal Management in the
“3D-SiP” World of the Future
Presented by
W. R. Bottoms
1 March 18th, 2013
Power (both power delivery and power integrity) and
physical density of bandwidth are the two
major limiting factors for the digital
electronics industry.
Neither of these limiting factors will be
resolved without improvements in Thermal
Management
March 18, 2013 2
Smaller, More Powerful Portable Devices
Are Driving Up Power Density
Changing Landscape
GLOBAL MOBILE DATA TRAFFIC (2009-2015)Exabytes
20090
10
20
30
40
5
15
25
35
45
50
2010 2011 2012 2013 2014
Cisco
CAAGR 2009-2014
109%
Ericsson
CAAGR 2009-2014120%
2015
Source: Cisco and Ericsson Measurements in Global Networks
N8
10.
11
3m
vc-tra
ffic
Traffic doubles every year
Capacity strain on infrastructure
2009
175
1,145
240
1,385
1,535
57.1%
12.2%
4.2%
4.0%
8.2%
27.3%
3.6%
6.7%
19.8%
10.8%
7.5%
6.2%
1,650
2,100
1,285
250
1,390
1,800
260
300
275350
720
0
500
1,000
2,000
2,500
M Units
MOBILE PHONE MARKET
1,500
2010 2011 2015
N1
11
0.1
46
mvc
Bandit Phones
Branded Phones
Smartphones
Smart Phone Packaging Technology PoP + WLCSP+ FCCSP Si Interposer + 3D
Heterogeneous Integration SiP
Networking & Server Packaging Technology Ultra Low Alpha Large Die, Large Package
Heterogeneous Integration SiP Silicon Interposer + 3D
Traffic doubles every year
Capacity strain on infrastructure
Where we are
Where we are going
March 18, 2013 3
In every case Thermal Management
is the limiting factor Data transmission and memory are joining logic making
significant and growing power demands
March 18, 2013 4
Thermal Density Is Impacting
Everything
Qualcomm Presentation At RTI 3D Conference 2012
March 18, 2013 5
The first and most effective
technique for thermal management
is to reduce power requirement
Thermal Management Solutions
Reduce Power Requirements
Continue Moore’s Law scaling
– As long as it’s effective
Use equivalent scaling through functional
diversification
Use the 3rd dimension
New Materials
New device and package architectures
March 18, 2013 6
The 45 Year History Of Knowing What
Comes Next Is Over
Progress has been paced by Moore’s Law and driven by:
• Focus was on design and fab
– Shrinking geometries
– Expanding wafer size
– Higher density designs
For digital circuits there are now limitations that can’t be met by these
activities alone.
March 18, 2013 7
Power Density Limitations Of Moore’s Law It Will Not Be Able To Keep Up This Pace Of Progress
CMOS Power is no longer scaling with feature size
– A majority of the capacitance is in the interconnect
– Resistivity of Copper is rising with decreased feature
size
– Power is rising with increased frequency
March 18, 2013 8
International Electron Devices Meeting December 2012 Kurt Ronse, IMEC
“14-nm chips likely will deliver about 15 to 20 percent performance boosts
over the prior generation, rather than the typical 30 percent boost”
Problems Arising From Shrinking CMOS
Gate tunneling current increases
Subthreshold channel leakage current increases
Device parameter variability increases
Source/drain resistance increases
Copper interconnect resistivity increases
Power no longer scales with feature size, both static and dynamic power dissipation
increase due to these barriers.
March 18, 2013 9
How Can We Reduce Power In Scaling
CMOS?
Reduce leakage currents
Reduce on-chip Interconnect power by:
– Decrease conductor resistance
– Decrease capacitance
Reduce interconnect length
Reduce operating frequency
Reduce operating voltage
Voltage regulator per core
Reduce high speed electrical
signal length
(new transistor designs)
(new material)
(new material)
(3D integration)
(increased parallelism)
(reduced frequency& size)
(new IC designs; FINFET)
(serdes with short path To very wide bus)
March 18, 2013 10
Qi Wang, Cadence technical marketing group director
“In the last 10 to 20 years, there has been a lot of effort devoted to performance, but we have left a lot of margin on the power side. Why do we keep Vdd at 1 volt? There’s no point. You can drop Vdd to 0.3 or 0.4. People need a safer way to do circuit design.”
March 18, 2013 11
Decrease The Operating Voltage
Note: This decreases power requirement but increases need for low cost high k dielectrics
March 18, 2013 12
Functional diversification and
Heterogeneous integration enable
equivalent scaling
This has been titled “More than Moore”
Moore’s Law Scaling Can Not Maintain The Pace Of
Progress And Packaging Enables Equivalent Scaling
Interacting with people and environment
Non-digital content System-in-Package (SiP)
Beyond CMOS
Information Processing Digital content System-on-Chip
Biochips Fluidics
Sensors Actuators
HV Power
Analog/RF Passives
More than Moore : Functional Diversification
90nm
65nm
45nm
32nm
28nm
Λ . . 14nm
Mo
re M
oo
re :
Scal
ing
Baseline CMOS: CPU, Memory, Logic
o o o o
13
“More Than Moore”
Heterogeneous Integration Enabled By Sip
Functional diversification delivers equivalent scaling
The most cost efficient, energy efficient and highest performance
is achieved when each circuit fabric type is fabricated with
process and materials optimized for that component
The contribution of Assembly and Packaging to MtM is
System in Package integration “SiP”.
The package provides:
– The use of the most efficient component for each function
– The delivery of the resources to the components necessary for their function
– The delivery of output/removal of heat and by products from operation of
the SiP
– Protection of the components in the package
March 18, 2013 14
Examples Of 3d-SiP Products
Source: Fraunhofer IZM
March 18, 2013 15
March 18, 2013 16
Use of the third Dimension
3D System Integration
Production Ramp-up Model and Technology/Cycle Timing
Time (arbitrary units) 0 -2 1 2 -1
Development
First Conf.
Papers
First Two Companies
in Production 1
10
100
1000
10,000
Vo
lum
e (arb
itrary un
its) C
ost
(ar
bit
rary
un
its)
1
.01
.001
.0001
.00001
Semiconductor Electronics Has Been
Characterized By An S-curve
Production
In the first S-Curve cycle in the semiconductor industry the
Technology was the transistor
March 18, 2013 17
Production Ramp-up Model and Technology/Cycle Timing
1
10
100
1000
10,000
Vo
lum
e (arb
itrary un
its) C
ost
(ar
bit
rary
un
its)
1
.01
.001
.0001
.00001
Can The 3D IC Maintain Progress
Through A Third S-curve Cycle?
Transistors
Integrated Circuits
3D IC
1D
3D
2D
March 18, 2013 18
Speed and Power Advantages of 3D
3D interconnect decreases path lengths.
– For “n” TSV stacked layers, this may reduce global interconnect path lengths by square root of “n”
– Reduction in interconnect length
• Faster circuit speed
• Reduced power consumption
– Standby power reduced by 75% compared to PoP and MCP packages
– Smaller physical size
– Eventually, lower cost
March 18, 2013 19
March 18, 2013 20
3D Components For Smart Phones
Source: Yole
Thermal management challenges for
3D-SiP Architecture
Finding solutions is not going to be easy
High thermal dissipation density
Hot spots
Differential thermal expansion
Heterogeneous integration – Both circuit type and material
The result is thermal limitations for: – Bandwidth
– Power density
– Cost
– Reliability
March 18, 2013 21
March 18, 2013 22
Hot Spots management is critical for
Heterogeneous Integration
Qualcomm Presentation At RTI 3D Conference 2012
March 18, 2013 23
New Materials are an essential
tool in Thermal Management
New Materials Will Be Required
Cu interconnect
Ultra Low k dielectrics
High k dielectrics
Organic semiconductors
Green Materials
– Pb free
– Halogen free
But improvements are needed
Many are in use today Many are in development
Nanotubes
Nano Wires
Macromolecules
Nano Particles
Composite materials
March 18, 2013 24
Thermal Management Materials
Requirements
Highly coupled Material Properties
Novel materials to achieve optimal performance for each parameter
CTE
Modulus
Fracture
Toughness
Functional
Properties
Moisture
Resistance Adhesion
Examples
Thermal Interface Mat.
Mold Compound
Conductors
Adhesives
Underfill
March 18, 2013 25
New dielectrics
– Both high and low K
New conductors
– Both thermal and electrical
Improved thermal interface materials
Nano-materials
– Particularly as fillers for composite materials
March 18, 2013 26
New Materials Requirements
Si based Low k dielectrics in engineering status today
March 18, 2013 27
Dielectrics And Conductors Are Changing
Properties Value
k 1.8
n633 1.21
E (GPa) 3.0
H (GPa) 0.5
Adhesion, Critical Load (mN) TBD
Etch stability
0.5% HF at RT P
1% KOH at 50 oC P
Porosity > 40%
Source: SBA Materials
Composite Copper is in evaluation.
Current status:
March 18, 2013 28
Dielectrics And Conductors Are Changing
Source: NanoRidge
The first electrical performance improvement in copper since 1913 makes composite copper the most electrically conducting material known at room temperature.
Targets for improvement compared to conventional copper are: 100 % increase in electrical conductivity 100% increase in thermal conductivity 300% increase in tensile strength
March 18, 2013 29
Graphene Supports >10X Cu A/Cm2
March 18, 2013 30
Graphene Has Superior
Electromigration Lifetime
March 18, 2013 31
Carbon Conductors Look Better Than Cu
Many questions still to be answered before graphene or CNT can be considered as a practical
interconnect materials. The results so far are very promising.
March 18, 2013 32
Other Techniques For Thermal
Management
March 18, 2013 33
High Thermal Conductivity Materials For
Thermal Management In Stacked Die
Composite Mold Compound with high thermal conductivity
Thin, high efficiency heat sink
Thermal Vias in the stack
Composite Mold Compound with high thermal conductivity
Composite underfill and inter-layer dielectric with high thermal conductivity
Reduce Power
The “low hanging” Fruit
Move the photons as close to the transistors as
possible
March 18, 2013 34
Microfluidic Cooling Is One Solution
T. Brunschwiler et al., 3D-IC 2009 (IBM)
March 18, 2013 35
What Can We Do To Meet Thermal
Challenges With 3D-SiP Archtecture?
Reduce the power dissipation – Use the 3rd dimension. Stacking can reduce power by as much as the square root of the number of layers
– Reduce operating frequency. Increased parallelism can restore performance at lower power cost.
– Reduce operating voltage. You don’t need the voltage if you operate at lower frequency.
– “Smart” power management in the package. Turn off the power to sections of the circuit not in use; voltage regulator per core.
New materials (for reduced power, improved thermal tolerance and improved heat removal) – Ultra-low K dielectrics. Power dissipation is proportional to C.
– Composite copper. Improved thermal and electrical conductivity.
– Direct band gap semiconductors. Extreme CMOS with Ge and IIIV compounds for higher speed and lower power.
– Carbon nanotubes for improved conductors and heat spreaders.
– Graphene for improved conductors and heat spreaders.
– Nanowires for improved conductors with reduced edge and grain boundary scattering.
– Nano-ribbons for improved conductors with reduced edge and grain boundary scattering
– Nano-solders for higher conductivity and reduced processing temperatures
New Device and Package architectures – Microfluidics to the package and to the chip
– Move photonics closer to the transistors. On package and, eventually, on chip.
– Increased parallelism to meet bandwidth requirements at lower voltage. Bus widths of several thousand.
– Heterogeneous integration in SiP allowing optimal materials and process selection for each different circuit fabric type.
March 18, 2013 36
Thermal Management In The “3d-sip”
World Of The Future
Reduce the power dissipation
New materials
New device and package architectures – Reduce frequency by increasing parallelism
– Lower operating voltage
– “Smart” power management in the package
Examples: low k, composite copper, nano-solders, high k materials, 3D integration, thermal vias,
heat spreaders, SiP to limit interconnect distance
March 18, 2013 37
These thermal management techniques
combined can reduce thermal density by
more than 2 orders of magnitude and
increase thermal dissipation efficiency.
However, thermal management will
continue to be a primary limiting factor
for the electronics industry; at least until
the CMOS switch is replaced.
Thank You for your attention
March 18, 2013 38