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Chapter I: Introduction to thermal effects in HBTs

1.1) HBTs: operation's principle, structure and applications Heterojunction Bipolar Transistors get now-a-days the aim of taking advantage of the superior electric properties of GaAs and other compound semiconductors in a bipolar device. Their operation's principle is very similar to BJTs' one, but with a crucial difference: realizing the base-emitter junction with two different materials adds indeed an important degree of freedom in designing the device to obtain desired performances. In particular, using a base emitter heterojunction allows to definitely overcome the old trade-off between an high emitter efficiency and a low base resistance: in other words, we can now heavily dope base region (as much as the rise of base-emitter parasitic capacitance allows, of course) without sacrificing DC transistor current gain [1]. The consequent low base resistance obviously results in a substantially improved frequency response. The other advantages are high current, high power gain and high efficiency. But, the microwave power devices operated at such a high power level together with the poor thermal conductivity in GaAs, generate a large amount of heat and result in much higher temperature in HBT. Since some physical parameters are strongly influenced by the junction temperature, the device performance operated in power application will be significantly affected. [2] Physically, the presence of a base emitter heterojunction has the effect of limiting the injection of holes from the base into the emitter region, since the potential barrier in the valence band is higher than the one in the conduction band. This fundamental consideration is clearly seen in the energy band structure of the device, which the following image represents an example of:

Figure 1: Schematic HBT band structure.

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In Fig. 1, Ec (Ev) stands for the discontinuity in the conduction (valence) band; instead, En and Ep represent the energy barrier seen by each type of carrier. Obviously, Veb and Vbi are respectively the bias voltage at the base emitter junction and the built-in potential. Because of its high current handling capability (i.e. high output power) and high switching speed (i.e. high cut-off frequency and maximum frequency for oscillation), AlGaAs/GaAs HBT has become an increasingly important and popular semiconductor device in designing power amplifiers for RF and microwave applications. More generally, this technology becomes the only one possible for analogue applications over a certain frequency range (in the field of GHz) and it's already one interesting solution to investigate for high speed digital circuits design.

1.2) Electrical properties and frequency response in HBTs The electrical IV model is rewritten in a form similar to Ebers-Moll equations for a GaAs-based HBT as follows [2]:

where:

Here, in order to achieve a more realistic HBT model, we consider some current contributions in the device that are caused by recombination of minority carriers in the neutral base (Jrb1), and recombination in the emitter-base space charge region (Jrb2), where

Some physical constants and device parameters are listed in Table 1, other ones are the following:

Vp = 1.42 107 cm/sec Vn = 4.16 107 cm/sec

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Vt = 0.0259 V Ec 0.243 eV 1.08 1012 F/cm 2 = 1.16 1012 F/cm Vbi = 1.718 V

Table 1: Physical constants and parameters considered.

The frequency at which incremental current gain drops to unity is called the current gain cut-off frequency fT, which is inversely proportional to the signal delay time EC (carrier transit time) from the emitter to the collector. It can be estimated through the relation

where:

is the emitter region delay time;

is the base-emitter plus base-collector depletion layer capacitance (each one expressed as the conventional depletion capacitance model) in charging time through the emitter diffusion and series resistance;

is the base transit time, being WB the quasi neutral base thickness (depending on collector current) and vnB the minority carrier electron velocity in the base (that is 2Dn/WB);

is the base-collector depletion layer transit time, in which X3 is the collector depletion layer, vs is the GaAs saturation drift velocity and the velocity overshoot factor;

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is the base-collector depletion layer capacitance charging time through collector resistance, given by collector series and contact resistance. In addition to the cut-off frequency fT, another important parameter is the maximum frequency fmax, given by:

The effective base resistance RB related to the device geometry and device parameters is an important factor in determining the frequency performance and can be divided into four parts, according to the following expression:

where:

Rbm is the resistance of the base metallization; Rint is the resistance of the intrinsic base (experienced by the base lateral current to

the underneath emitter); Rext is the resistance of the extrinsic base (encountered by the current as it flows from

the base contact to the portion of the base under the emitter); Rc is the base contact resistance.

Obviously, if Rb and Cjc are all reduced, then fmax should be enhanced.

1.3) Introduction to thermal effects and recent advances in HBTs There are three thermal effects that cause power HBT to malfunction. The first is the temperature-dependent current gain. The current gain decreases monotonically with ambient temperature which is higher than the room temperature. The second thermal effect is secondary breakdown, a well-known phenomenon in Si bipolar transistor under high power operation. It occurs when the device temperature reaches a semiconductor intrinsic temperature at which the electrical properties are dominated by the thermal induced intrinsic carriers. Since the intrinsic temperature of AlGaAs/GaAs is high, the secondary breakdown may not be a thermal problem. The third one is the thermal run-away. It usually occurs at a temperature lower than the other two, and it is the primary problem for limiting the power performances. Thermal instability constitutes indeed a major reason for sudden failure in power HBTs. The nature of this phenomenon is that of a tendency for hot spots to bloom because of a positive feedback between temperature and locally increased current. The positive feedback is that local high temperature causes the lowering of base band-gap, which results in a low turn-on voltage thus inducing more current and more local heat. [2] For a single-emitter finger HBT, the thermal effect arises therefore from the fact that the heat generated in the HBT cannot be dissipated quickly to the ambient area, thus increasing the lattice temperature in the HBT (i.e. self heating effect). To increase the uniformity of current density and thus the power handling capability of the HBT, a multi-emitter finger structure is frequently used. While the multi-finger structure can effectively reduce the self-heating, the thermal effect in such a structure is more complex because thermal coupling among the emitter fingers can also occur if the finger spacing is relatively small. The thermal-coupling effect causes the inner finger to be hotter than the outer fingers and the multi-emitter finger structure consumes more wafer space. But the multi-emitter finger HBT

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can have improved performance and stability over the single-emitter finger HBT if the layout of the multi-emitter fingers is properly designed [3], as it will be shown in the next chapter. For now, it is only important giving evidence to the fact that every HBT here discussed is based on a multi-finger structure. Some other important issues got recently in HBT analysis and significant advances lately introduced in this technology will be also discussed in the following paragraphs.

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Chapter II: Analysis, issues and solutions for thermal effects in HBTs

2.1) The multi-finger emitter structure for improving HBTs' electrical performances Studies on the HBT thermal design and analysis focused on the multi-finger HBT structure in which only the emitter is separated into the island structure (E-island) and both base and collector are contiguous underneath the emitter fingers, as shown in Fig. 2(a). Anyway, there are also two other possible multi-finger structures for HBT, that are those shown in Fig. 2(b) and (c), where HBT has emitter/base island (E/B-island) and emitter/base/collector island (E/B/C-island), respectively. [3]

Figure 2: Structures for (a) E-island HBT, (b) E/B-island HBT, and (c) E/B/C-island HBT.

Compared to the E-island HBT, the E/B-island HBT has a less uniform lattice temperature and current distribution in the base. Similarly, the E/B/C-island HBT has less uniform lattice temperature and current distribution in the collector than the other two devices. Using a two-dimensional device simulator MEDICI, numerical simulations result achieved by Ref.

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[3] authors will be here presented to compare the DC and AC performances of the three HBTs. All HBTs considered are n/p+/n Al0.3Ga0.7As/GaAs/GaAs three finger HBTs with the following typical device make-up: Thickness (nm) Doping (cm-3)

Emitter 100 5 x 1017 Base 100 1019

Collector 700 5 x 1016 Moreover, it's been supposed to have a base/emitter graded layer of 30 nm, an emitter finger area of 4 x 10 m2 and a 10 m finger spacing.

Figure 3: Current gain versus the collector current of the three HBTs simulated at VCE = 2 V.

Figure 4: Lattice temperature contours simulated at VBE = 1.5 V and VCE = 2 V for E-island and E/B-island HBTs.

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Fig. 3 shows the current gains versus the collector current IC of the three HBTs simulated at VCE = 2 V. It can be seen that the E-island HBT has the largest for a wide range of current level. At high current levels (i.e. > 10-3 A/m), this is due to the fact that the lattice temperature in such a device is the lowest among the three HBTs: Fig. 4(a-b) indicate the E-island and E/B-island HBTs lattice temperature contours. At a smaller current (i.e. 10-6 A/m), the largest in the E-island HBT results from the contiguous base structure, which makes the electron-hole recombination in the base less prominent and hence reduces the base current. Fig. 5 shows the cut-off frequencies fT of the three HBTs simulated at VCE = 2 V, indicating that the E/B/C-island HBT has the lowest peak fT. This can be attributed to the fact that the E/B/C-island HBT has the least uniform electric field in the base-collector junction among the three devices. It has been shown in various studies that the free-carrier transit time across the base-collector space-charge region is often the limiting factor for the HBT cut-off frequency. Thus, the lower field in the region between fingers found in the E/B- and E/B/C-island formations increases the overall base-collector transit time and decreases the overall cut-off frequency of the E/B- and E/B/C-island HBTs.

Figure 5: Cut-off frequencies versus the collector current of the three HBTs simulated at VCE = 2V.

Among the three HBT structures studied, the E-island HBT (Fig. 2(a)) appears hence to be the most convenient multi-finger HBT structure for high current gain and cut-off frequency applications. It could be now asked how electric and thermal performances of the HBT change with emitter fingers' number and geometry. To answer this question, an analytical model for multi-finger HBTs, considering the nonuniform temperature distribution in the emitter fingers resulting from the self-heating and thermal-coupling mechanisms has to be developed. Although the following model and issues have been achieved in Ref. [3], many other studies have been done about this thread; in particular, a very good convergence numerical method for simulating self-heating effect in GaAs-Based HBTs has been proposed in Ref. [11].

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First of all, to make a meaningful comparison of the performance of HBTs with different emitter finger structure, it will be considered fixed the total area of the emitter. The finite difference method is used, and each emitter finger is divided into several sub-regions (N elements, see Fig. 6), each with coordinates of xk and yk. The current and temperature in each sub-region are assumed uniform. The temperature Tk at a particular emitter element can be determined from the heat flow equation:

with the following boundary conditions:

where Kth is the thermal conductivity of GaAs, P(x,y) is the power density, t is the substrate thickness and TA is the ambient temperature.

Figure 6: Subregions used in calculations for (a) single-finger and (b) multi-finger HBTs.

The temperature-dependent current IC,k in the kth element can be expressed as a function of base-emitter junction voltage VBEj,k and Tk:

where IC,0 is the collector saturation current. The DC current gain k in the kth element is a function of collector current and is typically expressed as:

where is the base transport factor and is the temperature-dependent emitter injection efficiency, given by:

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where D, N and W denote diffusion coefficient, doping concentration and layer thickness, respectively. For a given total collector current IC, the temperature at each emitter element can first be calculated, and this temperature is used to re-calculate the temperature-dependent collector current at each element. The correct solutions of temperature and current are obtained after several iterations. Using the correct temperature, the DC current at each element and therefore the base current at each element can be calculated. The averaged (or overall) DC current gain of the HBT including the non-uniform temperature distributions can then be found by dividing the total collector current by the total base current. To model the HBT cut-off frequency fT,k in each subregion including the effects of non-uniform current and temperature distributions in the emitter fingers, we first treat the frequency-dependent small-signal current gain k(f) in each emitter element:

where k(0) is the DC current gain of the kth element, j is the imaginary unit, f is the frequency, and f,k is the -3dB frequency. The overall small-signal current gain (f) of the HBT can therefore be obtained as:

The overall cut-off frequency fT can then be determined as the frequency at which |(f)| = 1:

Once the collector current IC,k, DC current gain k(0) and cut-off frequency fT,k for each element are found, the overall cut-off frequency can be calculated.

Figure 7: Temperature distributions in the width direction of emitter fingers for HBTs with (a) 6 and (b) 15 m

finger spacing.

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Results of calculations will now be shown and discussed. Fig. 7 (a) and (b) show the temperature distributions in the emitter-width direction for HBTs with 6 m and 15 m finger spacing, respectively. The temperature is reduced as the number of fingers is increased and the finger spacing is increased. This, of course, comes with the expense of consuming more chip area. The characteristics of averaged DC current gain for the high current level calculated using both the uniform and non-uniform finger temperature profiles are illustrated in Fig. 8. Results simulated from DAVINCI are also included to support the proposed model. It can be seen that the effect of non-uniform temperature distribution becomes more important as the finger number is increased: in general, it can be also seen that considering an uniform temperature profile in each finger gives an underestimated value of current gain. Also, the current gain increases as the number of fingers is increased (i.e., as the emitter finger temperature is decreased).

Figure 8: Averaged current gain calculated using both uniform and non-uniform temperature profiles in the emitter

fingers. The spacing is 15 m.

Figure 9: Cut-off frequency calculated using both uniform and nonuniform temperature profiles in the emitter

fingers. The spacing is 15 m.

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The characteristics of overall cut-off frequency fT versus the current density calculated using both the uniform and non-uniform finger temperature profiles are shown in Fig. 9. The error committed in considering an uniform finger temperature profile is shown, as well as the increasing of the cut-off frequency with the increasing of the number of fingers.

2.2) Focus on thermal runaway: improving stability with optimum multi-finger structure Until now, only emitter fingers of equal length and spacing have been considered, as shown in Fig. 10(a). For this structure, if the spacing is sufficiently small, the temperature of fingers in the device center rises faster than that of other fingers because thermal coupling is higher in the device center than in the device periphery. The heated center fingers draw more current and the temperature increases further, thus causing not only a worsening of the device performances, but also eventually reliability problems related to thermal runaway. At a low collector current, where thermal effects are insignificant, as the collector current increases by increasing the base current, the base-emitter voltage increases, but it decreases at a high collector current. The threshold collector current at which the base-emitter voltage begins to decrease is used as a criterion (called "regression criterion") for onset of thermal instability. This threshold current can be identified from a IC-VBE graph, called "regression loci". After the onset of thermal instability, the current through the peripheral fingers decreases because more current flows through the fingers in the device center. Because of this phenomenon, the temperature of the peripheral fingers decreases although the total power consumption increases. It appears important to observe that, as described in Ref. [4], thermal runaway is not the only possible source of HBTs' instability. For transistors operated at high voltages, in fact, an even more devastating effect can happen: it is the impact ionization or avalanche effect. When this happens in the collector, for a n-p-n transistor, the avalanche current results in a hole current back injected into the base. It causes VBE to drop and leads to device instability (this impact ionization caused instability can be much worsened when the Kirk effect happens). Hence, both thermal runaway and avalanche effect compete to define a SOA ("Safe Operating Area") in which the device can operate without risk of failure. Anyway, there exist many possible solutions to thermal instability problem in bipolar transistors. The most common of that is probably the use of emitter ballast resistors for reducing the transistors' thermal instability: in practice, Re always provides a negative feedback that alleviates the positive feedback caused by the self-heating (and impact ionization as well). Also adding a base resistance has the effect of extending the SOA (i.e. reducing device instability), but only in the case that SOA is controlled by self-heating alone (a base resistance can worsen the device stability if it is controlled by impact ionization instead). Another possible solution makes reference to an U.S. Patent [5] of the year 2002: it consists in modifying the HBT emitter structure adding a negative differential resistance (NDR) element for preventing thermal instability. The NDR element, implementable with a Resonant Tunnel Diode (RTD) or an Esaki Diode structure, is designed to limit the tunneling current to the maximal emitter current density required for safe transistor operation. In a small area device the total current is self-limited. Since a multiple finger transistor consists of a large number of small area devices connected in parallel and since each finger self-limits its emitter current, the thermal instability is prevented. This is accomplished without adding ballast resistance to all of the fingers, thus reducing the total

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emitter resistance of the multiple finger transistor. Since the current crowding effect is reduced, the size of each finger can be increased and the total number of fingers can be reduced (that, obviously, simplifies the transistor fabrication). A third alternative, very attractive solution [6] to reduce the thermal coupling effect, without adding any new element to device structure and without designing a large finger spacing (thus sacrificing too much chip area), consists in modifying the conventional emitter structure in two possible ways, as shown in Fig. 10(b) and (c). The spacing of the emitter finger is adjusted in Fig. 10(b) to reduce heat flow from adjacent fingers to the device center. The length of the emitter finger is adjusted in Fig. 10(c) to reduce the heat generation in the device center.

Figure 10: Structure of emitter fingers for a multi-finger power HBT: (a) reference, (b) space-adjusted, (c) length-

adjusted devices and (d) a simple geometrical model of HBT for thermal calculation.

Using a numerical analysis, based on an iterative method and a set of equations similar to those ones already proposed, it has been found fingers' spacing and lengths drawn in Fig. 10 to be the optimal values for a power HBT whose finger structure and technologic parameters are those reported in Fig. 11 and Table 2, respectively. For all devices, the total area of emitter fingers is 375 m2 and the distance between the device center and the outermost finger is kept constant to 62.5 m.

Figure 11: The structure of an emitter finger for a multi-finger power HBT.

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Table 2: A structure of epitaxial layer for AlGaAs/GaAs HBT.

The peak temperature versus power consumption PDC is shown in Fig. 12(a). For the reference device, the peak temperature increases rapidly after PDC = 235 mW and it becomes 450 K at PDC = 260 mW. The space-adjusted and length-adjusted devices have the peak temperature of 400 K and 380 K, respectively, although PDC is increased to 280 mW. These results indicate that adjusted devices have better thermal stability than the reference one.

Figure 12: (a) Peak temperature versus power consumption for the three devices and (b) temperature of each finger

at PDC = 110 mW and PDC = 260 mW for the three devices.

Figure 13: The regression loci measured at VCE = 8 V for the three fabricated devices.

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The reason can be understood from Fig. 12(b), which shows the temperature of each finger at a given PDC. At PDC = 110 mW, the differences in temperature between fingers are small. When PDC increases to 260 mW, the average temperature increases for all devices. However, the space-adjusted and length-adjusted devices show small temperature differences between fingers. The difference in temperature for the reference device is approximately 110 K, while those for the length-adjusted and space-adjusted devices are 8 K and 16 K, respectively. Because of the heat flow from adjacent fingers, the temperature of the center finger for the reference device is much higher than that of the other fingers. For the space-adjusted device, the heat flow from adjacent fingers to the center finger is reduced by increasing the spacing between fingers. For the length-adjusted device, the power consumption at the device center is reduced by using short fingers. The temperature of fingers #1 and #2 of the reference device at PDC = 260 mW are 340.5 K and 366 K, respectively. When PDC reduces to 240 mW, they increase to 347.2 K and 368.7 K (not shown in Fig. 12). These observations indicate that the current flow at PDC = 260 mW is concentrated to the center finger and the temperature of the center finger is high enough to induce thermal instability. Finally, the measured regression loci for the three fabricated HBTs is shown in Fig. 13 for VCE = 8 V. The thermal collapse occurs at:

IC = 32 mA, PDC = 256 mW (VBE = 1.4437 V) for the reference device; IC = 43 mA, PDC = 344 mW (VBE = 1.4497 V) for the space-adjusted device; IC = 53 mA, PDC = 424 mW (VBE = 1.4574 V) for the length-adjusted device.

The power levels at which the thermal collapse occurs on the space-adjusted and length-adjusted devices are 34% and 67% higher than that on the reference device, respectively.

2.3) HBTs' modified I-V and frequency model with thermal effect To study the behavior and capabilities of AlGaAs/GaAs power HBTs in terms of thermal performance, the physical-based thermionic diffusion model is adequate. Indeed, with respect to the local temperature rise, it suffices to modify the values of the most sensitive physical parameters which define the saturation current, the carrier transit time, etc., in the elementary model. [2] The temperature-dependent GaAs physical parameters are given as:

where: x is the Al mole fraction; Eg the energy bandgap (eV); n, p are electron and hole mobility, respectively; Vs the saturated electron velocity (cm/sec); Dn, Dp the electron and hole diffusion coefficients (cm2/s).

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The relationships proposed in the analytical model are valid only if the following assumptions are employed: (1) Boltzmann statistics are assumed (2) Two or three-dimensional effects are omitted (3) Assume the temperature in the intrinsic HBT, which is much higher than room temperature, is spatially independent (4) The heat generated in the intrinsic HBT is dissipated primarily through the semi-insulated (SI) substrate. Then the heat PS (W) generated in the HBT is:

where AE is the emitter area and VCE, JC are the applied collector-base voltage and current density, respectively. They are both calculated by the thermionic diffusion model. Thus, PS is related to the thermal resistance (Rth) of the substrate as

where T0 = 300 K is the ambient temperature. After some calculations, supposing the thermal conductivity of the SI substrate to be temperature independent, we get Rth (obviously dependent from the thickness of substrate), therefore a set of dependent equations that we can solve with several iterations. The numeric results provided by the proposed model will be now shown, with reference to junction temperature, static I-V output characteristics, current gain and cut-off and maximum frequencies. The calculated rising temperature is shown in Fig. 14 for various applied voltage VBE:

Figure 14: Calculated junction temperature and collector current as a function of VBE where the SI substrate

thickness is (a) 200 m and (b) 50 m. The temperature increases as collector current density is increased beyond 104 A/cm2 and reaches 500, 600, 700 K at maximum current for VCE = 4, 5 and 6 V respectively. As before said, it is evident from the figure that the device dissipated power is proportional to the product of VCE and collector current density. The sudden increase of the temperature over 500 K, due to already discussed phenomenon of thermal runaway, will cause self-

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destruction of the transistor. Therefore, the AlGaAs/GaAs power HBT or other microwave devices, which generate significant heat, will need special process technique (back-side process) to dissipate the generated heat during operation. The back-side process includes wafer thinning, via hole formation, plated heat formatting and dicing into individual chips. The finished devices are usually mounted with the front side upward and the bottom soldered or coated with another material which serves a heat sink. Hence, most of the heat generated in the front of the slice must be conducted through the GaAs SI substrate and into the heat sink. Unfortunately, the poor GaAs thermal conductivity requires SI substrate to be thinned down from its original thickness to a significantly low value (150 to 50 m). Such thinning is absolutely necessary for power HBT and medium to high power Monolithic Microwave Integrated Circuits (MMICs). Fig. 14(b) shows that the junction temperature reaches only 340, 350, 365 K as compared to those in Fig. 14(a), when the SI substrate thickness is thinned down from 200 m to 50 m. The calculated I-V characteristics (shown in Fig. 15) exhibit a negative slope when the base current density is high (or VCE is large), a phenomenon commonly observed in AlGaAs/GaAs HBT DC measurements. The negative slope in Fig. 15(a) is larger than that in Fig. 15(b) due to the thin down process.

Figure 15: IV characteristics for the SI substrate with a thickness of (a) 200 m and (b) 50 m.

Calculated current gain for various collector current is shown in Fig. 16. It's clearly seen that the current gain decreases at moderate to high values of collector current. If the device is assumed to be at ambient temperature (300 K) throughout it volume, solid line indicates that current gain rises monotonically with collector current. Thus, we conclude that the drastic decreases in at high current is resulted from the temperature effect: indeed, the combination of VBE falling toward the center of the emitter, due to electrical series resistance in the base, the increase of intrinsic carrier concentration and the negative temperature dependence of the band-gap, makes the increase of recombination in space charge region, which cause base current increasing drastically.

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Figure 16: Calculated current gain versus collector current density with VCE voltages as parameters for SI substrate

thickness of (a) 200 m and (b) 50 m. Therefore, a drastic reduction in will occur, especially when VCE increases from 4 to 6 V; obviously, the will collapse at higher collector current density in the thinned device, as clearly shown in Fig. 16(b). Calculated fT and fmax at different collector-emitter voltage are shown in Fig. 17(a) and (b):

Figure 17: Calculated (a) fT and (b) fmax versus collector current density at different collector emitter voltages in the

thermal model.

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The fT increases from low to moderate collector current density and then decreases at high collector current density. The decrease of fT in low collector current is resulted from a higher charging time eb due to a higher emitter diffusion resistance at low collector current. The fT degradation in high current region is due to base widening effect which increases the base transit time and increased emitter junction resistance. It is interesting to find that fT is reduced by the increase of VCE, and fmax actually increases slightly but falls off at a low collector current density when VCE is increased. These results clearly show that the commonly observed behavior of , fT and fmax at high JC can be accurately predicted by the present model. The rapid fall-off properties, which degrades the HBT performance, are caused mainly by the higher temperature in the HBT associated with the high JC and large VCE. The high temperature also results in the Kirk effect at a low JC.

2.4) Electrical characterization of an HBT with thermal effect After having analytically described the thermal behavior of a generic, ideal HBT, it could be important to study a characterization procedure for a real device which could take advantage of the results here presented. An interesting example of RF characterization procedure has been proposed in Ref. [7] and its results will be here summarized. The reference equivalent circuit for the HBT characterization is represented in Fig. 18:

Figure 18: The schematic diagram of the system containing the intrinsic device and the parasitic elements.

It's clearly composed by an "intrinsic" HBT and all the parasitic elements of the real device. The physical behavior of the intrinsic HBT is described by the already introduced set of coupled nonlinear differential equations, including heat transfer equation, numerically solvable once one has fixed boundary conditions. For small-signal analysis, time-dependent

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solutions are required. Two time-dependent simulations are used to calculate the small-signal y parameters at each frequency. For the common-emitter mode, these two simulations calculate the time responses of the base and collector current densities. One simulation uses an RF excitation of Vbe(t) = Vbe

0 + vbesin(2ft) applied at the base node with Vce fixed at Vce

0. The other simulation uses an RF excitation of excitation of Vce(t) = Vce0 +

vcesin(2ft) applied at the base node with Vbe fixed at Vbe0 . The parameters Vbe

0 and Vce0

are the DC base-emitter and DC collector-emitter voltages, and vbe and vceare the corresponding RF voltage amplitudes. The resulting RF base and collector currents of ib and ic of the intrinsic HBT allow the small-signal y parameters to be calculated, and the small-signal S parameters with a known load impedance, which is usually 50 in a parametric measurement system, are readily determined. The parasitic elements due to the metal contacts are denoted as Re in parallel with Ce, Rb in parallel with Cb, Rc in parallel with Cc at the emitter, base and collector contacts, respectively. The inductances of the contact leads are depicted as Le, Lb and Lc. The inter-node capacitances are represented by Cbe, Cce and Cbc for base-emitter, collector-emitter and base-collector capacitances, respectively. The Rbx and Rcx are the internal resistances between the intrinsic device and the base and collector contact pads, respectively. This linear network is analyzed to calculate the small-signal S parameters. The HBT devices were fabricated using a thermal shunt technique. A thermal shunt is a thick air-bridge connecting all the emitter elements to large contact pads on the SI GaAs substrate. This technique results in a small thermal resistance of the active device and an immunity to current collapse due to non-uniform junction temperature distribution among the multiple emitter elements. The particular device in this study has a total emitter area of 100 m2. The structure parameters used in the calculation are listed in Table 3:

Table 3: The HBT structure parameters used in the calculations

The S parameters were measured at the DC bias of VCE = 3 V and IC = 30 mA. It is found that the bias point at measurement corresponds to a VBE of 1.407 V, and a junction temperature of 380 K. With these parameters, the applied RF excitation voltages and the resulting RF currents in the time domain are calculated at frequencies between 1 and 40 GHz. The subsequently calculated small-signal S parameters for the intrinsic HBT are shown in Fig. 19, in which the measured small-signal S parameters are also shown: As the frequency approaches 40 GHz, the intrinsic S11 exhibited an amplitude and a phase approaching 1 and , respectively. This indicates that the intrinsic HBT under common-emitter mode behaves like a short circuit as frequency increases. However, the real device

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has a S11 with a magnitude significantly less than 1 (in this case, 0.75 at 40 GHz) and a phase somewhat less than (0.9 at 40 GHz), which indicates the presence of resistive and reactive elements connected to the input port of the intrinsic device. The S22 characteristics for both the intrinsic device and the entire equivalent circuit show a cusp around 10 GHz.

Figure 19: The calculated and measured S parameters for the frequencies between 1 and 40 GHz.

The origin of this cusp is not clear. But judging from the fact that the cusp feature is more distinct in the intrinsic device than in the entire equivalent circuit, it is likely associated with the intrinsic property of the HBT. The parasitic elements smooth this feature of the intrinsic device. One would expect this feature to disappear if the effect due to parasitic elements becomes large. The values of the 14 parasitic elements were obtained using a least-square-fit numerical technique. The 2 of this fitting is 0.0028. Fig. 19 also shows the calculated S parameters using those best-fitted parasitic parameters. The calculation results agree very well with the measured data. Obviously, not only RF, but also DC characterization requests the using of a thermal model of the intrinsic device. As an example, a method for extracting HBT emitter resistance value more precise than the traditional one in presence of significant self-heating effect is proposed in Ref. [8]: its principal issues will be here shortly summarized. For an HBT in the forward active regime of operation, the collector current IC, is approximately given by the following expression (valid over a narrow range of currents):

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The intrinsic base emitter junction voltage VBE' is related to the terminal VBE by the following relation which takes into account the voltage drops incurred by the series resistances:

which yields (assuming constant junction temperature)

As a result of self-heating, however, the device temperature changes with bias according to

where R is the thermal resistance between junction and heat-sink for the device. The temperature thus varies with bias. The temperature dependence of IS in HBTs in general is complicated due to the fact that both base transport and emitter-base barrier transport limitations may be important. In a first degree of approximation, it is possible to express corrections in terms of the measured shifts of IC and VBE with the temperature. We let VBE (about -0.0011 V/°C) be the temperature coefficient of the base emitter junction voltage VBE at constant IC. We find:

The added resistance term in the presence of self-heating is

Or, assuming large values of ,

We find the expression for the ‘true’ emitter resistance to be

This approximate analysis indicates that in the presence of self-heating, the shape of the observed 1/gm against 1/IC curve is unchanged but shifted by an amount equal to RA. The extent of the error depends on the value of VCE. Frequently in the generation of Gumme1 curves, the condition of VCB = 0 is employed and values of VCE approach 1.5 V. For a representative real device with emitter area of 1.4 m x 3 m, R has a value of 2500 °C/W, Re = 17 ad RA = -5 . If not corrected, the extracted resistance Re0 would correspond to 12 , with an error of 42 %.

2.5) Thermal coupling effect between HBTs in GaAs ICs The already discussed self-heating phenomenon, with the related variation of the device performances and the problem of thermal instability, is not the only important thermal effect in HBT. The thermal coupling (between two or more different devices) represents another important aspect to discuss [9]. The thermal coupling is a phenomenon in which the temperature of a device is changed by power dissipation of neighboring devices. This temperature rise alters the bias point of the device and, consequently, changes its electrical performance. This electro-thermal coupling complicates the simulation and design of many GaAs circuits. Similar to a device thermal resistance Rth, which is used to quantify self-heating, the mutual thermal coupling resistance Rth_21 is used to quantify the static mutual thermal coupling between devices,

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and it is defined as the ratio of temperature change in a device (i.e., the reference transistor) to the power consumed by a neighboring device (i.e., source transistor). A simple method for measuring thermal coupling by monitoring the change in collector current using simple current mirror (CM) circuits will be here presented. The simplest current mirror circuit consists of two HBT devices with their base terminals connected together, to a reference terminal, and their emitters are connected on chip through a wide interconnect gold layer and grounded (see Fig. 20). The collector of one of the HBTs (the reference device) is also connected to the reference terminal. The collector of the other HBT (the source device) is connected to a voltage source, VC, and IC is the collector current of this source device. One source measurement unit (SMU) is connected to the reference terminal and the current, Iref, is swept.

Figure 20: A simple HBT current mirror.

At low current and low VC voltage level, HBT power consumption induced temperature difference is minimum and can be neglected. The collector current, IC, of the source device tracks the reference current, Iref, linearly for a given VC voltage. The ratio of the currents in the source and reference transistors can be calculated by:

where IC is source HBT collector current, Iref is current through the reference terminal; Asource and Aref are areas of the source and reference HBTs. F and VA represent HBT current gain and Early voltage; VCE and VBE represent the collector emitter junction voltage of the source and reference HBTs. Since the absolute values of HBT Early voltage and current gain are very large (in the order of 100), the current ratio can be simplified to HBTs’ area ratio. However, as the reference current, Iref, or the collector voltage, VC, increases further (e.g. VC = 4 V, as in Fig. 21), the power dissipation, and consequently the device temperature, in the source device, increases significantly. Thermal effects become important and the collector current, IC, of the source device no longer tracks Iref linearly. As clearly shown in Fig. 21, the nonlinearity in IC-Iref relationship becomes more important as the spacing between the reference and source devices becomes larger (i.e. the thermal coupling becomes smaller). In the nonlinearity range, the equation above becomes invalid and circuit simulation becomes necessary to predict circuit behavior; obviously, in circuit simulation both self-heating and

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thermal coupling have to be included in order to accurately simulate the dependence of the collector current of the source device on both VC and Iref.

Figure 21: Measured input-output characteristics of the CM under test for two values of VC and different values of

the spacing between the transistors. HBT's emitter area are 12 mm2 and 120 mm2, respectively. During the simulation, the power consumption of each HBT at each biasing point was calculated. The powers were converted into the junction temperature rise for each device using the thermal resistance and the thermal coupling resistance. The temperature dependence of a HBTs’ base-emitter turn-on voltage is well known (about -1.3mV/°C), so the temperature rise at a particular HBT bias point can be calculated. The thermal coupling resistance is determined by iterating to obtain the best fit between the simulated and measured I-V curves. Fig. 22 displays the measured and simulated results of the CM under test with 26m separation between HBTs.

Figure 22: Measured (---) and simulated (- - -) IC current (a) without and (b) with including thermal coupling

resistance for the same CM of Fig. 21, with HBTs' spacing of 26 m. These simulations show a significant difference between properly including Rth_21 and simply neglecting Rth_21.

2.6) Recent advances in InP-Based SHBTs and DHBTs InP-based HBTs have recently emerged as the fastest bipolar transistors in the world. There are a number of inherent advantages of these devices in comparison with the more widely used and the more mature GaAs-based HBTs, including lower power consumption, higher

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speed, and larger gain. InP HBTs also offer material compatibility with light-wave technology devices such as InP-based lasers and receivers operating in the 1.3-1.55 m wavelength range, and high current driving capability. [10] An InP-based single-heterojunction bipolar transistor (SHBT) typically consists of a highly doped n-type InGaAs sub-collector layer for low collector resistance, a lightly doped InGaAs collector layer for small base-collector capacitance, a highly doped p-type InGaAs base layer for low base resistance, an n-type InP or InAlAs emitter layer, and a highly doped n-type InGaAs emitter cap layer for small emitter resistance. When a wide band-gap material such as InP or InAlAs is used as the collector material, a double-heterojunction bipolar transistor (DHBT) is formed. A key difference between the GaAs and InP HBT processes stems from the fact that deep isolation by ion implantation in InGaAs and InP does not result in similar high-resistivity layers, as it does in GaAs. The triple-mesa technology is the most commonly used process in high-performance InP-based HBTs. The InP-based HBTs are intrinsically fast because of the small electron effective mass and large -L valley separation in InGaAs, which allows highly non-equilibrium electron transport and extended velocity overshoot effects in the base and collector space-charge region. InP is known to have higher thermal conductivity than GaAs (0.68 versus 0.45 W/cm*K at 300 K). It is therefore common to assume that HBTs fabricated on InP substrates run at lower junction temperatures than in GaAs devices having the same geometry and power dissipation. This is, however, not necessarily true in the presence of an InGaAs sub-collector layer (and also an InGaAs collector layer in SHBTs) because InGaAs has a thermal conductivity of only 0.05 W/cm*K at 300 K. The following simulations show the influence of InGaAs on device thermal behavior and make reference to one-finger and eight-finger InP SHBTs and DHBTs, compared with the corresponding GaAs HBTs of similar layer thicknesses and dimensions. The InP HBTs are assumed to be mesa isolated and are therefore more non-planar than the implant-isolated GaAs transistors. In case of GaAs HBTs, the collector, sub-collector and substrate materials were all made of GaAs. InGaAs and InP are the considered collector material in the InP SHBTs and DHBTs, respectively. For both types of InP transistors, the sub-collector material is InGaAs and its thickness on device junction temperature is investigated. Unless otherwise specified, the thickness of the collector layers in all devices is fixed at 0.8 m and the finger size is 2 x 50 m. The power dissipation per finger was 0.1 W and was assumed to be uniformly distributed in the intrinsic collector region under each finger. No power dissipation is assumed in the base and emitter layers. 300-K thermal conductivity values are used and are assumed to be independent of temperature, even though they all decrease with increasing temperature in practice. Fig. 23(a) compares the peak junction temperature rises as functions of sub-collector layer thickness for one-finger and eight-finger GaAs HBTs and InP DHBTs, and one-finger InP SHBTs. The junction temperature rise in GaAs HBTs is independent of the sub-collector thickness because the sub-collector layer is also made of GaAs and has a thickness that is negligible compared to the substrate thickness of 100 m. In contrast, the junction temperature increases rapidly with increasing InGaAs sub-collector thickness in all InP HBTs. The rises in one-finger InP SHBTs with a 0.8 m InGaAs collector are far more significant than in the multi-finger GaAs HBTs and InP DHBTs of the same layer thicknesses. Even when the InGaAs sub-collector layer thickness approaches zero, the one-finger SHBT still has about the same peak junction temperature rise as an eight-finger InP DHBT with 0.7 m InGaAs

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sub-collector. For the same power density per finger, a multi-finger transistor normally runs at a higher junction temperature than a transistor with fewer fingers because of thermal interactions among its fingers, as already seen.

Figure 23: Dependence of junction temperature rise on (a) sub-collector and (b) collector layer thickness.

When the InGaAs collector thickness is reduced to 0.3 m, the one-finger SHBTs still run at a much higher temperature than eight-finger InP DHBTs with 0.8 m InP collector, as shown in Fig. 23(a). A similar trend in peak junction temperature rise and high junction temperatures are observed when the sub-collector layer thickness is fixed at 0.5 m and the collector thickness varies in the SHBTs (Fig. 23(b)). The results indicate that it is the total amount of InGaAs present in the collector and sub-collector layer that is important in determining the junction temperature of the transistors. Comparison between the temperature distributions in GaAs HBTs and InP DHBTs of the same layer thicknesses shows that the latter operate at lower peak junction temperatures than GaAs devices only when the InGaAs sub-collector layer thickness is less than about 350 nm. This is an important consideration especially for power applications, because power performance may be limited by thermal effects. Measures of the low-power thermal resistances Rth of 2 x 10 m2 InP SHBTs and DHBTs of different InGaAs thicknesses in the sub-collector and/or collector, averaged on different wafer lots, gave the results shown in Fig. 24:

Figure 24: Measured average low-power thermal resistance of 2 x 10 m2 InP SHBTs and DHBTs of different InGaAs thickness in the (sub-)collector layers. Each data point represents a device from a different wafer lot.

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As clearly shown in Fig. 24, Rth was large in SHBTs, and increased substantially when more than 300 nm of InGaAs were incorporated in the sub-collector in DHBTs. In addition to the junction temperature considerations for reliable operation, the presence of InGaAs in the collector of an InP HBT has significant influence on the base-collector reverse saturation current. By introducing only a total of 19.4 nm of InGaAs in the collector, the reverse saturation current increased substantially. Furthermore, an increase in substrate temperature by 100 °C increased the saturation currents in all cases by 2-4 orders of magnitude: in particular, this increase can be related to the current component ICB0,n due to the intrinsic free carriers in the collector. Under the common-emitter operation configuration, this base-collector current component ICBO,n does not go to the external base terminal but goes to the neutral base and gets amplified through the current gain mechanism of the transistor, leading to an additional current component ICB0,n in the collector current, where is the current gain of the transistor. Based on this argument and ignoring thermal effects on impact ionization and other process-related leakages, InP HBTs with thick InGaAs sub-collectors show worse output conductance and breakdown-like behavior than devices with thin sub-collectors, because of the increase in junction temperature and the corresponding exponential increase in intrinsic carrier concentration.

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Chapter III: Conclusions In this report, some essential issues about HBTs' behavior, stability and performances have been presented with particular reference to thermal effects on any of these aspects. The increasing importance of these devices in the design of power amplifiers for high frequency applications (i.e., the high current handling capability often asked to these devices) together with the poor GaAs thermal conductivity obviously take to the need of developing a valid theory of thermal effect in HBTs and finding convenient design rules. First of all, after a short introduction about the nominal working of these devices, it has been shown as better thermal performances and stability can be achieved designing an optimum multi-finger emitter structure, based on different emitter fingers lengths and spacing. In particular, the problem of thermal runaway has been discussed with defining a Safe Operating Area for the device and shortly presenting some possible solutions, other than the optimum finger design, that have been discussed. Afterwards, the nominal HBTs' I-V model and frequency response have been modified for including thermal effects essentially due to self-heating phenomenon. With reference to a procedure using an iterative method, calculated results for I-V characteristics and principal figures of merit have been presented. The RF and DC characterization problem for an HBT has then been discussed. First of all, calculated small-signal S parameters have been presented using a hybrid model, in which a numerical simulation including the thermal effect and a network analysis were applied to an AlGaAs/GaAs HBT under common emitter operation. Then it has been focused on an alternative extraction procedure for Re of the transistor, widely more precise than the traditional one in presence of thermal effect. Other than already discussed self-heating effects on HBTs' stability and performances, another important consideration has been done about the problem of thermal coupling among near HBTs working on the same GaAs I.C.: a drawback of the presented method is that it only provides the real part of the thermal coupling, which is anyway still important for DC operation. The effect of considering or not the mutual thermal resistance has been shown with particular reference to the measured behavior of a simple current mirror. Finally, recent advances and thermal properties of InP-based HBTs have been introduced. These devices have shown higher fT, fmax and power gain than GaAs-based devices of comparable breakdown voltages; thermal behavior of InP SHBTs and DHBTs has been discussed with reference to an important technological parameter as InGaAs sub-collector or collector layer thickness. The choice of discussing as last the new InP HBTs has not been casual. These devices have been progressing rapidly over the past few years and have shown significant performances as lower power consumption, larger gain and mostly higher speed: an InP/InGaAs HBT developed at the University of Illinois at Urbana-Champaign, designed with compositionally graded collector, base and emitter, has been demonstrated to cut off at a never before reached frequency of 710 gigahertz. Besides being record breakers in terms of speed, HBTs made of InP/InGaAs are ideal for monolithic optoelectronic integrated circuits: the band-gap of InGaAs fits for detection of 1.55 m wavelength signal used in optical communication systems. All these clear considerations easily leads today to predict that the HBTs' next future goes straight in that direction.

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