Thermal design of gallium arsenide MESFETs for microwave power amplifiers

P.W. We bb

Indexing terms: MESFETs, Surface mount power amplijkrs

Abstract: In the traditional design of microwave power amplifiers using gallium arsenide field effect transistors, the active devices are mounted onto a thermally conducting heatsink, and matching circuits at the input and output take the form of microstrip, usually using aluminium oxide as the dielectric. The thermal attachment of the transistor is often a problem with this technology and the use of many bond wires can lead to manufacturing problems because of unpredictable phase shifts associated with their variable length. The author describes a number of surface mount alternatives to this technology and assesses the associated thermal implications. Three dielectric alternatives are considered, namely aluminium oxide, aluminium nitride and diamond.

1 Introduction

Currently, the traditional design of the gallium arsenide MESFET amplifier, used in many microwave applica- tions, consists of input and output circuits fabricated in microstrip usually using aluminium oxide substrates of the order of 10 mils ( 2 5 4 ~ ) thickness, between which a gallium arsenide MESFET is placed [l]. The MES- FET is soldered to a metal heat sink, which forms an electrical ground plane for the circuit, and this heat sink has a raised section to which the MESFET is attached. The ground plane is often made of copper tungsten, for reasons of thermal expansion difference between the gallium arsenide chip and the heat sink, but copper has been used where the solder layer allevi- ates thermal expansion differences. The MESFET is connected to the input and output matching circuits with gold bond wires, which can be very large in number. The output stage of a typical solid state microwave power source, would consist of a number of power MESFETs, which drive through a power com- biner to give the required total microwave power required for a specific application.

Problems which commonly arise with this technology are the attachment of the active device to its heat sink 0 IEE, 1997 IEE Proceedings online no. 19970872 Paper frst received 3rd April and in revised form 13th August 1996 The author is with the the School of Electronic and Electrical Engineer- ing, University of Birmingham, Edgbaston, PO Box 363, Birmingham B15 2TT. UK

IEE Proc.-Circuits Devices Syst., Vol. 144, No. 1, February 1997

and the considerable number of bonding wires. It is important to achieve a uniform low thermal resistance over the whole active device area to avoid local thermal hot spots and this is not always easy to achieve as GaAs chips are very small and brittle and often require mechanical scrubbing to produce a satisfactory thermal bond. The bond wires also introduce unwanted induct- ance and any variation in the nominal length of these bond wires can lead to unwanted phase shifts in the contribution of that section of the device to the power output, reducing the magnitude of the total output.

This paper assesses the thermal design of alternative ways of constructing such microwave amplifiers, and at the same time seeks to improve the reproducibility of the thermal and electrical bonding process. One method of achieving this goal is to mount the active device face down as a flip chip and electrically and thermally connect it to a suitable substrate using a solder bump technology. Solder does not have a particularly high thermal conductivity but solder bump technology is well developed. In the past, very small gallium arsenide MMICS have been attached to microstrip circuit using gold bumps with compression bonding but this seems an unlikely process with larger die. A surface mount technology is not really consistent with a microstrip design technique, as it is undesirable to consider making connections to a ground plane through the dielectric supporting layer. The electrical circuit would therefore be of a coplanar design, which itself has other advantages [2]. The variable parasitic series inductance of the bond wires would be replaced by a more reproducible parallel capacitance. The notion of flip chip mounting of the gallium arsenide MESFET is not new and test hybrid modules have been manufactured as early as 1983 on beryllia substrates [3]. Unfortunately, little device and mounting detail is available in this reference, but photographs suggest a flip chip mounted prepackaged device. Since 1983, a number of companies have considered experimenting with this design approach but have not pursued the technology. One’s initial reaction to this form of thermal design would be to suppose that the thermal resistance might be too high, and this is the motivation for this thermal assessment. It is also very important to note that the efficiency of some of the MESFET type devices currently being manufactured has improved significantly over the last year or so, and this factor is also very important as it makes the thermal design less critical, as the heat dissipated in the active device is reduced as the circuit efficiency increases.

To assess the thermal design, it is necessary to make a comparison with a conventionally mounted structure.

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To achieve this, a typical ten-gate MESFET structure will be modelled as a conventionally mounted structure and then suitably modified for mounting as a flip chip. The steady-state thermal modelling CAD tool used in this paper uses a finite difference method and was written by the author (unpublished). It is three dimensional and may be run on a PC. It can easily handle problems with a node count in excess of lo6, returning a solution in about 30 minutes or so for the simulations described here. The tool allows for the variation of thermal conductivity with temperature, where this is thought to be important, and uses NAG graphics for displaying temperature profiles and contours. The isometric projections shown in this paper have been mapped onto a uniform square grid for display. This grid is not that used in the solution, which is appropriately variable in three dimensions. The thermal conductivities of the various materials used in this work are included in an appendix.

_-- v band pad

vi a X

U 2 0 p m

the drain. The size of the chip is 8 4 0 p (X) by 7 4 0 p (Y), see Fig. 1. The exact volume of dissipation affect the final temperature to some extent but, as a comparison is being made between various structures, the matter is of little consequence.

These dimensions can be considered typical of C- band structures. The gate widths of microwave MES- FETs made by a selection of manufacturers are between 100 and 2 0 0 p , and source and drain metalli- sations are up to 2 0 p wide, as in this model. These are generally large devices with typically 100 gates, but often grouped in sections of up to ten gates per section. The vertical dimension is also typical, although in the case of one manufacturer the GaAs is only 30pm thick, backed with 5 0 ~ of gold.

Fig.2 flip chip showing areas to be contacted by Jolder bumps There is no need for the bridge on the GaAs chip

Layout of gallium arsenide MESFET modfled for mounting as

Fig. 1 Dimension of via indicates outside via edge whether solid or plated; gate width = 1 4 0 p , gate length = lpm; chip dimension is 840p.m by 740pm with MES- FET placed centrally on it

Layout of representative gallium arsenide MESFET

ESFET device structures

2.1 Model I The layout of the conventionally designed MESFET (model 1) is shown in Fig. 1. The device has ten channels. The gallium arsenide is 85pm thick and is backed with a gold layer which is 30pm thick. The sources are connected to bond pads with a bridge supported by polyimide through which the gates pass. There are vias which connect to the gold back. These vias may be solid, plated inside with gold up to a thickness of 20ptn, or may be eliminated from the model. The gate width is l40pm and channel length 1 pm, the gate metallisation being 0 . 5 ~ thick. The source and drain metallisations are 2 0 p wide and 3 p thick. All metallisations are gold. The spacing between the edge of the drain and gate is 4 . 5 ~ and the source to drain spacing is 10 pm, making the gate to gate spacing 3 0 ~ . In all simulations the device dissipates 0.5 watts equally distributed between the gates. The dissipating volume is assumed to be 1 . 0 c ~ n in length by 0.3 deep and the width of the gate, it is displaced from the position of the gate 0.5pm towards

46

2.2 Model2 The structure of model 2 is shown in Fig. 2. The basic detail is the same as model 1 except that the bridge through which the gates pass has been removed. Solder bump technology contacts the device in the areas shown. In the diagram of Fig. 2 the solder comes within 5 p of the source metallisation edges.

2.3 Model3 This structure is shown in Fig. 3. The gate and drain contacting is similar to model 2. The sources are con- nected with a gold bridge which is l o p thick and which is raised 10pm above the drain metallisation. The metal of the gate and drain in the region of the solder contacts have been increased so that they are planar with the top of the source bridge. The source electrical and thermal contact to the structure is made with one large area solder bump.

2.4 Model4 In this model, solder bumps contact all the source and drain metallisations and the metallisation marked source in Fig. 2 is reduced in size so that the arrangement is symmetrical, The source and drain metallisations are the same width as the active gate region and their only thermal and electrical contact is

IEE Proc -Circuits Devices Syst Vol 144, No I , February 1997

through the solder bumps. The metallisation necessary to interconnect the sources and drains of the MESFET is transferred to the dielectric. The sources are interconnected as in Fig. 1, but the connection does not require any bridge structure as the interconnection is on the dielectric and contact to the gates is on the gallium arsenide chip. The gate arrangement is as shown in Fig. 2 but the contact pad and corresponding solder bump is moved away from the channels, as shown in Fig. 1, to allow for the source interconnection on the supporting dielectric.

....._ --_I

I lgold bridge : :solder bump --- . _ _ _ _

gate 20 pm drain

Fig.3 Layout of gallium arsenide MESFET mod$ed for mounting as f l i p chip showing areas to be contacted by solder bumps and area covered by a bridge connecting source metallisation

3 Substrate structure

In the case of model 1 the GaAs chip is soldered with 2 5 p of solder to a section of the heat sink raised by 254pn-1, being the same dimension as the dielectric thickness to be used in the flip chip simulations. The heat sink (or ground plane) is made from copper tungsten and is lmm thick. The heat sink is 3mm square and the chip is mounted centrally. This size of the base is such that making it any larger would make virtually no difference to the channel temperature. In the simulations, the bottom of the heat sink is at 50°C.

For the flip chip structures the thickness of the dielectric is normally 2 5 4 ~ . The solder bumps, which unless otherwise stated are 3 6 p thick, make thermal contact to the dielectric support through a gold metallisation layer which is 4 . 5 ~ thick. According to manufacturers who use solder bump technology 1 2 p resolution has been demonstrated and solder bumps need not be square in shape, which is in keeping with the suggested thermal designs.

The choice of 36pm for the solder bump height is certainly on the pessimistic side and likely in practice to be in the range 15 to 25pn-1 minimum. The metallisa- tion on the dielectric will affect the thermal path and in the simulations this area is normally the same shape as that of the chip gold metallisation on the other side of the solder bump. In reality, the metallisation on the dielectric will be larger than this and would serve to reduce the thermal resistance. Again the bottom of the

IEE Proc -Circuits Devices Syst , Vol 144, No. 1, February 1997

3mm square dielectric base is held at 50°C. Three dielectrics are considered namely aluminium

oxide, aluminium nitride and diamond. The permittivities of manufactured A1,0, and A1N substrates are about 10 and 8.9 depending on precise composition, with similar microwave dielectric loss, so that the electrical circuit sizes would be similar. Diamond has a permittivity of 5.7 so that this substrate would be useful at higher frequencies. There does not appear to be any published data on dielectric loss in this material.

Typically, the smallest node spacing in the chip is 0.1 pn and largest 40pn but in the dielectric the node spacing is as large as 2 5 0 ~ . The node spacing is smallest where the thermal gradient is largest.

4 Simulation results

A comparison between the various structures is best made in terms of thermal resistance which is defined here to be the maximum temperature rise within the device measured with respect to the heatsink, divided by the input power. Some temperature profiles or isometric projections will be shown to confirm the substance of the model or where they demonstrate some important feature.

Fig. 4 X-dimension = 200 ~ 600 m, Y-dimension = 200 - 595 w; the maximum tem- perature is 12.1"C

Surface temperature of conventionally mounted MESFET

4.1 Model I In the case of the conventional device structure, simulations with solid, plated and no vias were first considered as it seemed that this might be an important thermal feature. This device was also simulated as a flip chip with solder bumps positioned where the bonding pad areas are shown in Fig. 1. The notion was that the gold backing would carry the thermal flux to the vias and then to the dielectric substrate through the solder bumps. This flipped chip must have a higher thermal resistance than the conventionally mounted structure but it was of interest so that the consequence of mounting existing transistors in this way might be assessed. As a confirmation of the model, Fig. 4 shows the temperature over part of the surface of the conventionally mounted chip as seen from above. Note the effect of the source bridge metallisation conducting the heat flux towards the bond pad regions. Fig. 5 shows the temperature distribution of half of the structure through a vertical cross-section, at constant 'I" (see Fig. l), of the gallium arsenide, gold, and solder layers. This thermal distribution is altered little, whether the vias are solid, plated or are absent. The

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corresponding thermal resistances are 45.46, 45.50 and 45.6"C/W, respectively.

The device described as model 1 was simulated as a flip chip mounted on the three material bases as described in Section 3. The results are shown in Table 1, which shows the thermal resistance and the value relative to the conventionally mounted device with plated vias.

1800 E c.1600- 3

0 ffl c -

.- E 1400-

1200

U I

>

Table 1: Thermal resistances of model 1 mounted as a flip chip

-

-

Thermal resistance ("C/W) and relative value compared to the conventionally mounted device

Base Via type Solid Plated No via

Aluminium oxide 83.39 (1.83) 83.70 (1.84) 84.44 (1.86)

Aluminium nitride 57.37 (1.26) 57.67 (1.27) 58.39 (1.28)

Diamond 53.36 (1.17) 53.77 (1.18) 54.36 (1.19)

The presence of the via seems to make only a marginal difference to the thermal resistance and, to emphasise the point, the device was simulated with the gold back replaced by a diamond film of the same thickness. For the aluminium oxide base, the thermal resistance was 80.57"CIW (1.77) with a solid gold via which is only marginally different to that for the gold backing. The conventional and flipped chip were simulated with a gallium arsenide thickness of 20pn and an aluminium nitride base. The relative significance of the via and gold plated back is decreased if the gallium arsenide thickness is reduced, with the relative thermal resistance increasing to 1.48 compared to 1.27 for the 8 5 p m GaAs thickness. The actual thermal resistances are lower for the structure with reduced GaAs thickness.

Fig. 5 Temperature distribution through conventionally mounted transistor in X-direction showEL%$fdevice Positions of gold and solder layers are easily identified as is solid gold via

This model was also simulated with solid vias and aluminium oxide and aluminium nitride bases with the source metallisations contacting the base dielectric three times the original size. For aluminium oxide the thermal resistance was 79.99"CIW (1.75) and for the aluminium nitride 57.29"C/W (I .26). Predictably the effect is more significant in the former case. The effect is clear if the thermal contour map over the surface of

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the dielectric is examined, where large thermal gradients may be observed around the edge of the metallisation in the case of the aluminium oxide base. The thermal distribution in the proximity of the channels within the gallium arsenide volume is changed little in form (see Fig. 5) whether the chip is mounted conventionally or as a flip chip.

Table 2: Thermal resistance of model 2, and comparative values with the conventionally mounted device

Thermal resistance ("C/W) and relative value

Base Solder bump size Aluminium material (bump height) oxide Aluminium

Diamond

nitride

Large (36pm) 73.24 (1.61) 44.27 (0.973) 39.40 (0.866)

Small (36pm) 79.72 (1.75) 51.74 (1.14) 47.00 (1.03)

Small (20pm) 72.23 (1.59) 43.71 (0.961) 38.90 (0.850)

4.2 Model2 This model was simulated with no vias as the results of the previous Section indicate that this feature will make little difference, the gold back, however, was retained. Two different areas for the solder bumps were used, one in which the solder bump covered the entire area of the source fingers (large area) and one in which there is a 5 p n space around the bump (small area) as in Fig. 2. Two solder bump heights were used: 3 6 p n and 20pn. The results are shown in Table 2. The gate and drain arrangements were the same in each case.

2200 I

iooo~, , , , , , ,

800 1200 1600 2200 X -dimension, pm

Fig. 6 Temperature contours over surface of aluminium oxide dielectric for Model 2, with large solder bumps Contour step is 1°C; the maximum temperature is 6921°C; note large thermal gradient at gold edges

Additionally, the simulation with an aluminium nitride base was repeated for the case of the smaller solder bumps but with the dielectric base thickness doubled. The thermal resistance and comparative values increased to 53.27"CW and 1.17, a relatively small change. Figs. 6 and 7 show the thermal distribution over the surfaces of the dielectrics aluminium oxide and aluminium nitride, respectively, for the case of larger solder bumps. It is clear why, in this and other cases, aluminium nitride is far superior for heat transfer. The high thermal conductivity of gold compared with alumina tends to make the gold contact

IEE Proc -Ciucuits Devices Syst , Vol 144, No I , Febuuary 1997

pad an equithermal surface. It was found that the thermal resistance of this structure did not vary linearly with solder bump thickness. This was due to the change in relative heat flow through the various areas of solder contact. The thermal resistance as a function of solder thickness is shown in Fig. 8.

whereas for the change to diamond it is about 53%, quite different to the ratio of the thermal conductivities of aluminium nitride and diamond.

Table 4: Thermal resistance of model four and compara- tive values with the conventionally mounted device

Thermal resistance ("C/W) and relative value

22001

0 c-1600- ._ v)

.: lhOO - ?

1200

I I loo0 t I

800 1200 1600 2200 X-dimension, krn

Fig. 7 for Model 2 with large solder bumps Contour step is 0.2"C; the maximum temperature is 53.39"C

Temperature contours over suflace of aluminium nitride dielectric

0 5 10 15 20 25 30 35 40 solder thickness, p,m

Thermal resistance of model 2 as f i c t i o n of solder bump thick- Fig.8 ness

4.3 Model 3 In this case the conducting path with the smaller cross- sectional area between the chip and the dielectric is gold rather than solder, and the structure should, there- fore, have a relatively smaller thermal resistance. The bridge is an ideal one and it is difficult to assess the constructional problems involved in making it an ideal shape although a number of manufacturers make power MESFET structures with source connecting bridges. The results of the simulations are shown in Table 3.

Table 3: Thermal resistance of model 3 and comparative values with the conventionally mounted device

Thermal resistance ("C/W) and relative value

Base material

Aluminium oxide Aluminium nitride Diamond

74.36 (1.63) 41.33 (0.908) 35.02 (0.77)

Notice that the change in thermal resistance from the aluminium oxide base to nitride base is about 44%,

IEE Proc-Circuits Devices Syst., Vol. 144, No. 1. February 1997

Base material

Aluminium oxide Aluminium nitride Diamond

75.82 (1.67) 39.46 (0.867) 32.64 (0.717)

4.4 Model 4 The results of these simulations are shown in Table 4, and are little different to those of model 3. The thermal resistances are however improved on model 2 which is a structure requiring a similar constructional technique.

The aluminium nitride model 4 structure was also simulated with a solder bump thickness of 15pn instead of 36p-n and this factor as expected makes a significant difference the thermal resistance being 30.93"CW and relative value 0.68. For this latter case, the temperature across the surface of the gallium arse- nide is shown in Fig. 9. The maximum channel temper- atures are nearly uniform over the device and this is in contrast to the aluminium oxide based structure where the centre channels are significantly hotter than their immediate neighbours. This last structure was also modelled with the chip mounted at the corner of the dielectric A1N base. The thermal resistance increased by less than 0.1%, indicating that there would be little thermal interaction if a number of transistors were mounted in close proximity.

Fi .9 Tem erature over plane of gallium arsenide surface for model 4 wi2 15 pn s o h r bumps X-dimension = 200 ~ 640pn1, Y-dimension = 200 - 5 8 0 ~ ; the maximum tem- perature is 63.48"C

5 Discussion

Four typical alternative designs were considered with three different dielectric mounts, and these were compared with the traditionally mounted transistor. There are other alternative chip designs, and many parameter variations are possible within the typical structure described. Some flip chip structures would have to utilise membrane probing to test the devices before mounting, as the sources or drains may not be interconnected before final assembly, but this should not be problematic. Also, from the practical consideration of design rule, checking the solder bumps would need to have dimensions less than the

49

connecting metallisations, which is not the case in some of the models described here.

There are two clear conclusions, first, as expected, aluminium oxide is not a good choice of substrate, and secondly the inclusion of vias through to a high con- ductivity base on the GaAs chip is not helpful. The exclusion of vias makes fabrication simpler and, from an electrical view point, it can reduce unwanted para- sitic capacitance. Although one would not expect the conventionally designed transistor, model 1, to have a good thermal resistance when mounted as a flip chip, it is only about 20% worse if aluminium nitride or dia- mond was used as the dielectric base. In all the flip chip structures examined, the thermal resistance is com- parable to, or less than, the conventionally mounted transistor.

In solder bump technology, barrier metallisations are needed to prevent interaction of the solder with the gold based metallisations. These layers are very thin and would not be expected to affect the thermal models. In the manufacture of model 1 for flip chip mounting, they would represent additional and unwanted processing steps. However, if the transistor is designed specifically as a flip chip, there are a number of possible benefits: (a) Vias which are used to reduce source electrical inductance are unnecessary. (b) The chip may be thick, making manufacturing han- dling easier. (c) The gate and source metallisations may cross with- out the necessity for a dielectric bridge on the GaAs chip. (d) The variable and unwanted parasitic inductance of the bond wires is eliminated. (e) The electrical and thermal contact to the chip should be much more reproducible, making manufacture easier and fine tuning of the final product unnecessary.

An important feature of any thermal design is an assessment of thermal expansion effects in the steady state, during powering up and for pulsed operation. Having the dielectric base and transistor materials with the same thermal expansion coefficient by no means negates these problems. The thermal expansion coefficients of GaAs, A1,03, A1N and Diamond are approximately (x 10-6/K) 5.9, 6.5, 3.5 and 1.2, at room temperature. This is the only area in which aluminium oxide shows any possible constructional advantage and aluminium nitride is better matched than diamond. It should be said that Beryilla would be best for thermal expansion, having a value of 6.3 x 10-6/K and its thermal conductivity is also about 40% better than aluminium nitride. BeO, however, does have handling problems and this eliminates its commercial utility.

It is worth noting that the author has, in the past, examined many GaAs power MESFETS from a number of sources, using infrared thermal imagers, and

there is significant variation in thermal resistance with apparently identically mounted chips, and thermal hot spots are not uncommon.

6 Conclusions

This assessment of the thermal resistance of a number of flip chip structures demonstrates the feasibility of a surface mount coplanar microwave technology for microwave power amplifiers. The technique would be advantageous where a large number of identical units were required, for example, in the manufacture of a phased array radar system. Although diamond has a very good thermal conductivity, in this application it does not show a significant thermal improvement over aluminium nitride which currently must be a better choice on grounds of cost.

7 Acknowledgment

The author would like to thank Dr Paul Bestwick of GEC Marconi Materials Technology Ltd for his advice on a number of technical issues.

References

WALKER, J.L.B.: ‘High power GaAs FET amplifiers’ (Artech House, 1993) GILLICK, M., ROBERTSON, I.D., and JOSHI, J.S.: ‘Coplanar waveguide two-stage balanced MMIC amplifier using impedance- transforming lumped-distributed branchline couplers’, IEE Proc.,- Microwaves, Antennas Propug., 1994, 141, (4), pp. 241- 245 WALLACE, P., WOHLERT, A., and IMMORLICA, A.A.: ‘Flip-chip FETs on BeO: a new miniature hybrid technology’. Proceedings of the Microwave applications technology conference, Washington, DC, 1983, pp. 55-56, BRICE, J.C.: ‘Properties of Gallium Arsenide’ (EMIS Datarev. Ser. INSPEC, London, 1986, No. 2)

Appendix

The values of the thermal conductivities of the various materials used in the simulation are given in Table 5. The actual thermal conductivities of aluminium oxide and nitride depend on composition, in particular, the oxygen content of the nitride lowers its thermal conductivity. The values used here are representative. Only the GaAs material has a temperature dependent thermal conductivity.

Table 5: Thermal conductivities of materials used in the simulation

Thermal conductivities, W/mK

Gold 330 Polyimide 0.2

Copper/tungsten 240 Diamond 2000

Aluminium nitride 180 Aluminium oxide 25

Goldkin solder 57.3 Note Pb/Sn 63/37 is about 50

Insulating gallium arsenide: variable with temperature accord- ing to Brice [41

50 IEE Proc.-Circuits Devices Syst., Vol. 144, No. I , February 1997