there's plenty of room at the bottom 12/29/1959
TRANSCRIPT
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1Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
There's Plenty of Room at the Bottom
12/29/1959Feynman asked why not put the entire Encyclopedia Britannica (24 volumes) on a pin head (requires atomic scale recording).
He proposed to use electron microscope to “write” the words, and to “read” the words.
He also thought that biological systems were already writing and reading information at the molecular (or nano) scale.
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2Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
The Nanometer Sizescale
Nanotube
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3Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Fabrication Techniques for Nano-Scale Structures
• ‘Top-down” Approaches– Lithography (E-beam,EUV)– Nano Imprint– Dip-Pen Nanolithography
• ‘Bottom-up' Approaches– Selective growth – Self-assembly – Scanning Tip Manipulation
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4Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06 e-beam lithography resolution factors
• beam quality ( ~1 nm)
• secondary electrons ( lateral range: few nm)
performance records
organic resist PMMA ~ 7 nm
inorganic resist, b.v. AlF3 ~ 1-2 nm
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5Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
The benchmark of Top-down Approach5nm-Gate Nanowire FinFET
2004 Symposium on VLSI Technology, p.196
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6Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Technology Gap for Top-Down Approach
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7Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
How to make a single-Crystal Si Nanowire
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8Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Y.Ono et al., “Si complementary single-electron inverter”, IEDM, pp.367-370, 1999
Oxidation rate slows down withmechanical stress induced by surrounding oxide
Si Nanowire by thermal oxidation
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9Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Prober et al, APL, 94 (1980)
30-nm wire fabrication by directional thin-film deposition
Triangular cross-section
Rectangular cross-section
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10Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
dummystep
SiO2Si
Substrate
dummystep
SiO2Si
Substrate
SiO2Si
Substrate
SiO2
Substrate
Conformal CVD film 10-20nm spacer
Spaceras etching mask
Sidewall Spacer to define nm wires
nm Si
~10nm
(1) (2)
(3) (4)
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11Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Twin nanowiresWith anisotropic etching of SOI
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12Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
• Sacrificial layer method, deposition method, etc.• Cheaper and mass-productable methods• Soft mat’l vs. hard mat’l
Tas et al., Nano Letters, 2, 1031 (2002)
Nanochannel fabrication
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13Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
www.nanonex.com
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14Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
D. Piner, J. Zhu, F. Xu, and S. Hong, C. A. Mirkin, "Dip-Pen Nanolithography", Science, 1999, 283, 661–63.
* as small as 15 nm linewidths and ~5 nm spatial resolution
Dip-Pen Nanolithography
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15Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Cutting window through a thin layer of Si oxide
Line dose: 3.3, 2.5, and 1.7 x 10-3 C/cm,
for the three lines from top to bottom;
“Local” E-beam
Etching an 8-nm Ag thin film
on Si(100) using the LEEB/STM
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16Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
By E-Beam
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17Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Growth Modes
* Au nanoparticles as catalyst
Nanowire Growth byVapor-Liquid-Solid Method
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18Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
1D Functional HeterojunctionsLOHNs
• NanoElectronics•Thermoelectrics
COHNs
•NanoOptics•NanoFludics
Nanotape
•Selective sensors
Si/SiGe AlGaN/GaNTiO2/SnO2GaN/AlGaN
Prof. P. Yang, Chemistry
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19Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
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20Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Step Coverage(Al2O3)
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21Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Chemical Modification of Single Walled Nanotubes
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22Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Silicon probe with a conductive single walled carbon nanotube (<2 nm diameter). The tip is at the end of a flexible cantilever designed for the atomic force microscope.
http://www.media.mit.edu/nanoscale/research/sensors.html
A nanotube-bundle tip was used as thenegative electrode to locally oxidize silicon and write the oxide pattern ‘C-Tube’. OH- ions (from condensed H2O on tip) are driven by the strong field into the solid and induce the oxidation by reacting with Si holes in bulk Si.
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23Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
http://www.almaden.ibm.com:80/vis/stm/gallery.html
Title : Carbon Monoxide Man
Media : Carbon Monoxide on Platinum (111)
Title: Atom
Media: Iron on Copper (111)
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24Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06Probe Manipulation Technique
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25Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
The smallest transistor
-60 -40 -20 0 20 40 60
-200
-100
0
100
I (pA
)
Vsd(mV)
Vg = 6.4 VVg = 6.9 VVg = 7.4 VVg = 7.7 V
Operation onlyat low temp
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26Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Potassium Doping of CNT (n-type)
Javey et al, Nano Lett. 2005
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27Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Field Assisted Assembly
metallic particle+-V +V
Long-range forces attract nanowires to substrate
particle moves in gradientof field towards region of
highest field strength
dielectric medium
Theresa MayerEE Dept.
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28Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Field Assisted Assembly
Nanowires attracted and aligned totop electrodes
Alignment process is self limiting
SiO2+V -V
+ -
∆V = 0V
Siliconsubstrate
SiO2+V -V
+
-
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29Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
•Nanowires serve dual purpose: both active devices andinterconnects.•All key nanoscale metrics are defined during synthesis andsubsequent assembly.•Crossed nanowire architecture provides natural scaling andpotential for integration at highest densities. •No additional complexity (with added material).
Crossed Nanowire Architecture
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30Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
E-field Enhanced Fluidic Alignment
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31Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Surface Programmed Assembly M. Lee et al Seoul National Univ 2004
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32Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06Logic Gates and Computation from Assembled NanowireBuilding Blocks
Huang et al, SCIENCE VOL 294 9 NOVEMBER 2001
*p-Si and n-GaN NWs
The OR and AND gates has no signal gain
AssemblyY. Huang,, Science 291,630 (2001).
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33Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Applied Physics Letters, 82 2491(2003)
Carbon Nanotube Interconnects
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34Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Empirical : Resolution (in Å) ~ 23 Areal Throughput (in µm2/hr) 0.2
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35Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Principle and Practice of Top-Down Integration
* A sequence of Additive and Subtractive steps with lateral patterning
•Planarization is used to control critical dimensions (lithography, etching, and thin-film deposition)•Self-aligned structure used whenever possible•Alignment is done for ALL lithography steps (registration marksalways available on substrate)
Si wafer
ProcessingSteps
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36Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
Grand Challenges of The Bottom Up Approach
Bocheva et al, PNAS April 16, 2002 vol. 99 no. 8 4937–4940
What is the optimum functional building block using self-assembly ?
How do we align the different functional blocks for integration ?
- Alignment marks- 2D or 3D alignment
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37Professor N Cheung, U.C. Berkeley
Lecture 26EE143 S06
0.001
0.01
0.1
1
10
100
0 10 20 30 40
curr
ent (
nA)
time (min)
A)
Light Emitting Sensing Magnetic Assembly
Wavelength Conversion
Thermoelectronics BimorphMechanics
Catalysis
20 nm
Finite size effect.. Chemical/thermal stability issue for devices
Interface/complexity/functionalityThe integration issue: nano-micro-macro continuum.