the system-level evaluation of the ganoncmos components
TRANSCRIPT
GaNonCMOSThe System-Level Evaluation of the
GaNonCMOS Components
GaNonCMOS 2nd Webinar
Online – 25 May 2021
Agenda
GaNonCMOS introduction – Jean-Pierre Locquet (KUL)
Magnetic components – Paul McCloskey (Tyndall)
Controller and driver development for higher frequency power conversion with GaN devices - Norbert Fiebig (IHP)
Review of key development in GaN HEMT – Fouad Benkhelifa (Fraunhofer IAF)
Developments in PCB embedded components – Gerald Weidinger (AT&S)
Electrical results with the new components - Seamus O'Driscoll (Tyndall)
Q&A
2
Introduction
GaNonCMOS
Introduction
Jean Pierre Locquet
Functional Nanosystems Group – KU Leuven
Belgium
Power electronics applications
4
Project partners
Switzerland
Austria
Belgium
Germany
Belgium
Ireland
Austria
Belgium - Germany
Germany
Germany
5
Improve GaN epiwafers to develop ultra-low loss switches for applications
below 100V
Develop new soft magnetic core materials and inductor packaging
techniques that can allow low-profile, in-substrate, or chip-scale, in-package
Enable the fabrication of devices for low temperature integration processes
Develop miniaturized packages to allow operation at maximum speed and
high energy efficiency (granular multi-voltage PoL VRMs)
Integrate GaN power switches with CMOS drivers densely together using
direct wafer bonding (DWB)
Long term reliability improvements over the full value chain
Key innovations in GaNonCMOS
6
Demonstrators and applications
7GaN chip
CMOS chip
Laminate
BEOL
iVR for Server
Industrial,
Automotive, Aviation,
Consumer, ICT
Regulators on-die; inductors in organic substrate
Hand-held,
POL+ iVR for Server,
Automotive, Energy
Monolithic Regulator
embedded-in-PCB
8
Novel low cost, reliable GaN-based processes, components, modules & integration
Project concept
VRM system-level modelling & design
Materials exploration & development
Components development & fabrication
Reliability & characterization
Demonstration & piloting
Thin Film Magnetic
Components
Paul McCloskey
TNIUCC
• Thin Film Magnetics integrated on Silicon
• Thin Film Magnetics embedded in PCB
Outline
10
Thin Film Magnetics Integrated on Silicon - Micro-
transformer
• Advantages of a solenoid construction:-
o Laminated magnetic core fabricated on a single layer
Unlike a closed core which requires two layers => Lower cost
o No magnetic via required to connect top and bottom magnetic layers
• Fabricated in a CMOS-compatible back-end-of-line (BEOL) process
Thin Film Laminated Magnetic Core Section of solenoid structure
Dielectric 1 = oxide,
other dielectrics are polymerMicro Transformer
11
Motivation and Specification
• Smart Switches for future generation power systems will:-
o Include integration of GaN switches with CMOS control logic
o Enable; higher switching frequency, better gate driving, control telemetry and switch protection features
• Magnetics on Silicon for galvanic isolation of gate drive
o Gate drive for a high frequency (10 – 30 MHz) LLC resonant converter
o Provides signal isolation for both of the primary side bridge switch drives and the secondary side synchronous rectifiers
Parameters Values
Turns ratio 1:1
Transformer volt-seconds 10 V.ns
Magnetizing inductance
(L11)40 nH
Swtching frequency (fSW) 20 MHz
Coupling coefficient (k12) > 0.8
DC resistance (RDC) < 500 mΩ
Saturation current (ISAT) > 500 mA
Parasitic capacitance
(C12)
As low as
possible (to
minimise CM
injections)
Micro Transformer specification
12
Laminated Magnetic Core
Cross section of laminated magnetic core
• Laminated thin films of a cobalt based amorphous alloy (CoZrTa or CZT)
is used as the magnetic core material
• The real component of the permeability remains stable up to 100 MHz
frequency, while the imaginary component (which represents loss)
remains low
Complex permeability spectrum of a laminated CZT/ AlN stack
13
FEM Simulation Results
• Maximum magnetic flux density (~ 1T) is near the central region of the core.• Spacing between copper windings is large (40 mm) in comparison to dielectric 1 thickness (1 or 5 mm)
o Hence electric field between windings is largely coupled through silicon substrate.• 5X thicker oxide (dielectric 1) =>
o ~3X reduction in electric field intensity between copper traces and silicon o ~3X reduction in the parasitic inter-winding capacitance
• Important to minimise parasitic capacitance in order to reduce Common Mode (CM) injections
Magnetic flux density distribution in the core
for 20 MHz 500 mA current applied in one
winding
DC Electric field
distribution in vertical
cross-section of
transformer for 1V
potential difference
between copper
windings. Si-oxide
thickness
a) 1µm, b) 5µm.
14
Results extracted from S-Parameter
Measurement
4-port S-parameter measurementMagnetizing
inductance vs
frequency Coupling coefficient vs frequency
AC
resistance
vs
frequency
Q-factor vs frequency
• Thin-film magnetics on silicon (tf-MoS)
transformers demonstrate highly stable
magnetizing inductance, coupling
coefficient upto 200 MHz frequency.
• Low loss and high Q-factor in 1 MHz –
20 MHz frequency range.
15
Comparison of Simulated and Measured Results
Measured Simulated
Parameters TX1 TX5 TX1 TX5
Si-oxide base thickness 1 µm 5 µm 1 µm 5 µm
Swtching frequency (fSW) [MHz] 20 20 20 20
Magnetizing inductance (L11) @ fSW
[nH]
41.2 38 39.3 39.3
Coupling coefficient (k12) 0.85 0.84 0.83 0.83
DC resistance (RDC) [mOhm] 286 301 310 310
Quality factor @ fSW 12.8 12.6 13.7 13.7
Parasitic capacitance (C12) [pF] 13 3.5 10.76 3.68
Measured and FEM simulation results
Measured results show a good match to the modelled parameter values
16
Conclusions
• Micro-transformers fabricated in a CMOS-compatible back-end-of-line (BEOL)
fabrication process
• Measured electrical parameters such as magnetizing inductance, coupling
coefficient, resistance, quality factor and inter-winding parasitic capacitances
exhibited good match with the modelled parameter values
• Thin-film magnetics-on-silicon (tf MoS) micro-transformers exhibited stable high
frequency performance and low inter-winding capacitance
17
Motivation: • Excellent soft properties and high frequency performance of thin film magnetic
core
• Low DCR arising from PCB copper thickness (e.g. 70 mm)
Thin Film Magnetics embedded in PCB
18
19Tyndall Confidential
FEM of “Embedded in PCB” inductor
• Upper and lower solenoid windings - each with two 70 mm traces connected by micro via’s
• Magnetic sheet is laminated thin film core
Device Length (mm)
Device Width(mm)
Magnetic Core thickness (mm)
Magnetic Core Permeability
2.9 2.5 4 360
Tyndall Confidential
Fabrication of “Embedded in PCB” inductor
Schematic of Inductor: LHS – lower PCB, RHS – Upper PCB
LHS -lower PCB with mounted solder balls;
RHS – Lower PCB with mounted solder balls and magnetic core
X-Ray image of inductor with embedded core
20
Tyndall Confidential
Characterisation of “Embedded in PCB” inductor
• S-parameters obtained from VNA measurements and values of L & R extracted
• Magnetic core => X 3.27 inductance enhancement
• Inductance stable to 100 MHz
• Maximum measured Q-factor =23
• Ldc/Rdc = 0.5 (nH /Ω)
Ldc
(nH)Rdc
(mΩ)L @40 MHz (nH)
R@40 MHz (mΩ)
Ldc/Rdc
(nH /Ω)
52 102 50.5 551 0.5
21
Tyndall Confidential
AT&S Embedded Component Packaging Process
• Reliability test conditions of solder
reflow
• 260 C thermal
• 10 cycles
• Passed Reliability Testing
AT&S Embedding Process
Permeabilty stable after embedding
Thin Film Magnetic Core
embedded in PCB
22
23Tyndall Confidential
Conclusions
• Solenoidal “embedded in PCB” inductors fabricated using flip chip attach of two PCB’s
• Utilised thin film magnetic core and exhibited stable inductance to 100 MHz
• Low DC resistance due to use of thick copper
• Compatible with AT&S Embedded Component Packaging Process
Acknowledgement
This work was supported by the EU H2020 GaNonCMOS project (Grant Agreement No 721107).
o https://ganoncmos.eu/
The authors would like to acknowledge:o Central Fabrication Facilities (CFF) at Tyndall National Institute o Electronics Packaging and Reliability Group at Tyndall National Institute o AT&S Austria
24
www.ihp-microelectronics.com
Controller & driver development
for higher frequency power
conversion with GaN devices
Norbert Fiebig
IHP
IHP in Frankfurt (Oder), Berlin-Brandenburg
26
Research Institute of the
Leibniz Association
• ~ 350 employees from 27
countries, incl. 154 scientists
• Founded in 1983, new building
incl. clean room since 2000
• Owned by State of Brandenburg
IHP: Innovations for High Performance Microelectronics
• Basic funding from the German and local government → 65 %
• Third party funds → 35 % (public funded research projects, research fabrication
services)
• 1000 m² clean room → 130 nm & 250 nm RF SiGe BiCMOS processes on 8” wafers
• Member of the “Research Fab Microelectronics Germany” (FMD)
Research Programs & Strategic Goals of IHP
27
Integrated Circuit Design Goals and Challenges
28
Goals
• Driver and controller are essential building blocks of voltage
regulator modules
• Design of dedicated ICs for the project demonstrators
• Package and stack level PCB, and chip level demonstrators
• Core functionalities, no packages
• Aligned in die size and pad arrangement
Challenges
• Driver IC in standard CMOS technology
• Negative output swing of about -3.5 V
• High peak output current
• Isolation of different negative and positive voltage domains
• Fast transitions in non-overlapping fashion
• Controller IC offering a flexible system design
• Pulse width modulator (PWM) externally tunable in frequency and sawtooth amplitude
• Extra rail-to-rail operational amplifier for an on-board compensation network
Two Chip Solution
29
Driver IC
• Low-side and high-side branches
• Separate PMOS and NMOS outputs
• Over-dimensioned for
evaluation purposes
• Die size extremely driven by
padframe requirements
Controller IC
• PWM generator using a saw-tooth
• Adjustable Frequency
• Extra op amp for compensation
network
-
+
+
from error amp
PWM comparator
CR R2
-
+-
+
+
I0
R1 R3
IF
Die size 2.1 x 2.1 mm²
Die size 1.5 x 1.5 mm²
Evaluation Results – Driver IC
30
Fully functional branches
Base design for improvements
PWM input
high side
low side
Evaluation Results – Controller IC
31
First run fully functional
Working up to 10 MHz
Wide supply range
PWM clock
PWM output
Evaluation Results – PCB Demonstrator
32
Both ICs are part of a closed loop buck
converter together with IAF’s GaN switches
Efficiency of driver plus controller and
half-bridge GaN switches around 91%
for 2 MHz , 50% duty cycle and
25 W output load
©Tyndall
Combined Controller and Driver IC
33
Half-bridge driver for enhancement GaN switches combined with
a general purpose PWM controller for 12-V DC-DC converters
• 40% less die area at higher complexity and
advanced features
• PWM splitting and dead times controlling
• Condensed layout and optimized
pad arrangement
Die size 1.5 x 1.8 mm²
Evaluation Results
34
PWM controller and driver sections working fully functional stand alone
and in co-operation as well
Parameter Typ.
Value Unit
Supply voltage VDD, VDD1 VNN - VGNDS, VVBS - VSW
3.3 -3.5
V V
Supply current VDD, VDD1 VNN - VGNDS, VVBS - VSW
< 1 < 4
mA mA
Output peak current ± 1.8 A
PWM frequency 2 MHz
Duty cycle (fPWM = 2 MHz) 5 … 70 %
Delay times td,LH, td,HL (PWMIN to outputs)
< 20
ns
Dead times tdead,LH, tdead,HL (Rdel= 1 kΩ)
tdead,LH, tdead,HL (Rdel= 10 kΩ)
3
36
ns ns
Galvanic isolation 20 V
Operating temperature ϑamb 0 … 125 °C
Combined Chip for Direct Wafer Bonding
35
• Half-bridge GaN chip on top of the combined driver controller IC
• Bonded in 4” wafer formation
High Side
Low Side
Die sizes 2.65 x 2.65 mm² & 1.92 x 1.92 mm²
GaN chip
CMOS chip
High Voltage Converter Applications
36
Proof of concept
• Standard 0.13µm BiCMOS
• Galvanically isolated supply domains
• Specially isolated level shifters
• Galvanic isolation >64 V successfully proven
Die size 0.9 x 1.5 mm²Driver output signal (red) at 48 V
Review of key development
in GaN HEMT
Fouad Benkhelifa
Fraunhofer Institute for Applied Solid State Physics IAF
GaN HEMT activity
38
Fraunhofer IAF at a glance
◼ Ultra high frequency circuits for radar, communication and satellites
◼ Power electronics for mobile communications, radar and energy conversion
◼ Photodetectors for the infrared und ultraviolet spectral range
◼ Infrared semiconductor lasers for sensor systems and medical applications
◼ Diamond technology for electronics and quantum sensor systems
© Fraunhofer IAF
1000 m2
Clean room area
285Employees
Since1957in Freiburg
Key research topics
◼ Fraunhofer IAF is one of the leading research institutions worldwide in the field of
III-V semiconductors and diamond technology.
◼ We develop electronic and optoelectronic devices and integrated circuits as well as
modules based on III-V compound semiconductors.
39
CORE COMPETENCES
Devices and integrated circuits: simulation-aided design
III-V semiconductor epitaxy of complex device structures
Front- & backside processing for single devices and integrated circuits including mounting and packaging
Testing and characterization: materials analysis, device and circuit testing up to 1.1 THz, instrumentation for optical characterization from UV to LWIR
Modules & demonstrators for systems und subsystems
GaN HEMT activity
40
Applications
E-mobility: Battery charger of electronic and hybrid cars
Production technology: RF generators for plasma excitation
48 V power supplies for server farms
Features
◼ Considerable energy saving potential due to high switching frequencies
◼ High efficiency
◼ Operation possible under high voltages and temperatures
◼ Robust and compact devices
© Fraunhofer IAF© Petair – Fotolia.com © Fraunhofer IAF
Integrated power electronics with gallium nitride (GaN)
GaN HEMT activity
41
D D
SW
1
SW
2
SEM photo of a 25 V class GaN-based HEMT half bridge
IAF in GaNonCMOS project
IAF tasks are the optimization, fabrication and delivery of ultra low-
loss GaN-based HEMT switches, based on standard and explorative
technologies, to fulfill the integration of GaN power switches with
CMOS drivers for the different integration schemes
GaN HEMT activity
42
100 V Class – Devices
◼ LGD = 3.0 µm
◼ LG = 0.5 µm
◼ LGS = 1 µm
Intrinsic Structure Layouts
Ls Ld
Lgd
Lg
Lgs
Lgd
Lg
Lgs
Ls Ld
25 V Class – Devices
◼ LGD = 1.5 µm
◼ LG = 0.5 µm
◼ LGS = 0.7 µm
GaN HEMT activity
43
25 V- Layout-Design for PCB-Embedding
Integrated Topologies: Asymmetrical Low-Voltage Half-Bridge Switch
33 mΩ + 16 mΩ, < 50 V HEMTsAsymmetric GaN-on-Si half-bridge for Point-of-Load applications
GaN HEMT activity
44
GaN-HEMT Process Flow
Ohm contact formation
Passivation
Isolation (Implantation)
Drain Source
First metal interconnect
Field Plate
source draingateSiN
GaN / AlGAN HEMT
SEM cross section of gate’s HEMT fingerGate formation
Gate
GaN HEMT activity
Si substrate
n.i.d GaN
Al0.25Ga0.75N barrier
GaN cap
Buffer template
C doped GaN
MOCVD grown GaN HEMT epi-structure
45
Photography of the fabricated half-bridge converter: Chip size of 2 x 2 mm2
D
D
SW1
SW2
Half bridge device composed of a low
side switch (w=306 mm gate width) and
high side switch (w=153 mm)
0 4 8 12 16 2010-8
10-7
10-6
10-5
10-4
10-3
10-2
Drain bias (V)
VGS = - 4 V
Dra
in C
urr
en
t (A
)
10-8
10-7
10-6
10-5
10-4
10-3
10-2
Ga
te cu
rren
t Cu
rren
t (A)
Low side switch
0 4 8 12 16 2010-8
10-7
10-6
10-5
10-4
10-3
10-2
VGS = - 4 V
Drain bias (V)
Dra
in C
urr
ent
(A)
10-8
10-7
10-6
10-5
10-4
10-3
10-2
Gate
curre
nt C
urre
nt (A
)
High side switch
Breakdown Voltage Assessment (Mapping across 4” wafer)
GaN HEMT activity
46
0.0 0.2 0.4 0.6 0.8 1.0
-2
0
2
4
6
8
10
12
14
16
18
20
c03..D5.SW2
Curr
ent [A
]
Vds [V]
-4.0V
-3.0V
-2.0V
-1.0V
0.0V
1.0V
Ron = 29 mΩ Ron = 51 mΩ
0.0 0.2 0.4 0.6 0.8 1.0
0
5
10
15
20
25
30
35
c11.D5.SW1
Curr
ent [A
]
Vds [V]
-4.0V
-3.0V
-2.0V
-1.0V
0.0V
1.0V
On-wafer characterizationMeasure the low (221 mm) and high (110 mm) side parts
Pulse I-V and Ron of a Half-Bridge
GaN HEMT activity
47
4-inch GaN-based epi-wafer was thinned and diced
Single half-bridge chips were sent to AT&S partner for packaging
GaN half-bridge devices were embedded by AT&S
X-Ray photo of a GaN embedded half bridge Card containing 6 chips, delivered by AT&S
GelPaK box containing the individual switches
Embedding half-bridge chips @ AT&S
GaN HEMT activity
48
Embedded half-bridge chips evaluation
0 5 10 15 2010-7
10-6
10-5
10-4
10-3
10-2
HS: card Nr.: 3
Dra
in c
urr
en
t (A
)
Drain-source bias (V)
VGS = - 5 V
10-7
10-6
10-5
10-4
10-3
10-2
Gate
curre
nt (A
)
On board the breakdown voltage and I-V output characteristics of the embedded chips
Measure the low (221 mm) and high (110 mm) side parts
0.0 0.2 0.40
5
10
15
20
25
30
Dra
in-s
ou
rce c
urr
ent
(A)
Drain-source bias (V)
VGS = + 1 V
Step: - 1 V
LS: Card Nr.: 6
W = 221 mmI = 28 ARon Embedded = 16 mΩRon_Wafer = 29 mΩ
Ron reduction, thanks to the embedding technology
GaN HEMT activity
49
Highly accelerated stress test of embedded GaN chips
HAST in oven for 96 hours at 130°C, 85%RH Measure the LS and HS switches of 20 embedded chips
0 5 10 15 2010-7
10-6
10-5
10-4
10-3
10-2
HS: 18 chips working
Dra
in c
urr
en
t (A
)
Drain-source bias (V)
VGS = - 5 V
10-7
10-6
10-5
10-4
10-3
10-2
Gate
curre
nt (A
)
Results
◼ No delamination after X-ray examination
◼ No decrease of the maximum available drain current
◼ No increase of the RON
◼ Yield of 85 % after temperature and humidity storage
Austria
GaN HEMT activity
Next testing: Temperature cycling: 2000 cycles, -55°C to +125°C (TCy)
Ron_Wafer = 29 mΩRon Embedded = 16 mΩRon Storage = 17 mΩ
50
Embedded Point-of-Load (PoL) Demonstrator
POUT = 30 W @ 24-to-12 V
Embedded AT&S and IAF
chips
0
10
20
4.0 4.5 5.0
-5
0
DC = 0.08
tDEAD = 2 ns L = 600 nH
fSW = 1 MHz
VS
W [
V]
-2
-1
0
1
2
I L [
A]
VG
S [
V]
time t [µs]
12 V – 1 V PoL
GaN HEMT activity
51
GaN channel
AlGaN barrier
Buffer template
Si substrate
p-GaN
Gate
Source Drain
Standard GaN-HEMT
fabrication
0 1 2 3 4 5 6 7 8 90
100
200
300
400
500
600
700
800
Drain
Cu
rren
t (m
A/m
m)
Gate bias (V)
0
40
80
120
160
200
VDS = 7 V
Tran
scon
du
cta
nce
(m
S(m
m)
0 1 2 3 4 5 6 7 8 910-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
101
102
103
Drain
Cu
rren
t (m
A/m
m)
Gate bias (V)
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
101
102
103
Gate
curre
nt
(m
A/m
m)
VDS = 7 V
Threshold voltage of + 2 V
Low leakage currents & high drain current density
Large gate swing ( VGS = + 9 V)
LG = 0.6 µm
LGD = LGS = 0.7 µm
W = 50 µm
Normally-off HEMT based on p-GAN/AlGAN/GaN
GaN HEMT activity
52
0 1 2 3 4 5 6 7 8 90
100
200
300
400
500
600
700
800
Dra
in C
urr
en
t (m
A/m
m)
Gate bias (V)
0
100
200
300
400
500
600
700
800VGSmax
= 9 V
Step: -1.5 V
0 5 10 15 20 25 3010-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
Dra
in C
urr
en
t (A
)
Gate bias (V)
10-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
Ga
te c
urr
en
t (A
)
VGS = 0 V
LG = 0.6 µm , LGD = LGS = 0.7 µm , W = 50 µm
I-V and breakdown performances
GaN HEMT activity
53
100 V class single switch: gate width = 97 mm
20 A drain current capability
100 V breakdown voltage achievement
0.0 0.5 1.0 1.5 2.0 2.5 3.00
5
10
15
20
25
Dra
in c
urr
en
t (A
)
Drain bias (V)
VGSmax = 9 V
Step: - 2 V
0 20 40 60 80 10010-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
D3 SW1 W = 97 mm
Ga
te c
urre
nt (A
)
Dra
in c
urr
en
t (A
)
Drain bias (V)
VGS = 0 V
I-V and breakdown performances
LG = 0.6 µm
LGD = 3 µm
LGS = 1 µm
GaN HEMT activity
Embedding
Embedding Technology ECP
Embedding Magnetic
Materials
DemonstratorsGerald Weidinger
AT&S Austria
Embedding
55
Embedding
56
Embedding
57
Embedding
58
Embedded GaN
Demonstrator
Embedding
59
Embedded Inductor
Demonstrator
Embedding
60
Embedding
61
Embedding
62
Embedding
63
Embedding
64
Embedding
65
Embedding
66
PwrSiP Voltage Regulator
Designs using GaN Devices
Séamus O‘Driscoll
TNIUCC
• Considering 12 – 48 V Application Space for GaN switches
• Proof-of-Concept Converter Demonstrators
• PCB-DEMOs, because ultimately heterogeneous integration is involved:
• GaN switches, CMOS control/protection and drive, capacitors, magnetic materials
• Power Systems in Package, PwrSiP: PCB-Level, Stack-Level, Chip-Scale
• To prove the component technologies being developed
• PCB-Embedded Magnetic Materials and Devices (TNIUCC, AT&S)
• 130 nm BCD Controller & Driver (IHP)
• 25 V GaN d-HEMT (IAF)
Outline
68
12-1 V POL Design Space Analytic Exploration
(Based on EPC 30V Technology)
• Pareto-Front method to project CMOS and GaN Switch Areas for
Optimised VR Designs – Analytic and Simulation Verified
• 1-2 MHz & 450 nH Inductor to achieve > 90% Power Path for 1
V output
• Allowed us specify switching bridge areas
Refer TI Application Report SLPA009A Power Loss Calculation with Common Source Inductance Consideration for Synchronous Buck Converters
69
• 25V IAF RON.QGt = 20 mΩ.nC
• 15V EPC2040 RON.QGt = 18 mΩ.nC
Prototype IAF Switch FOM vs Commercial Device
EPC20140
Ig = 490 uA
for 2us
VDS 6-0 V
IAF B3
W=110
Ig = 490 uA
for 2us
VDS 6-0 V
Simulations Brendan O’Sullivan
(PhD Student Tyndall)
IAF_B3_W110
(25V d-HEMT)
Qg to Miller
Plateau Start
Qg to Miller
Plateau End
Qg to Driver
Voltage RDS_on
(mΩ)
Ron.Qgt
(mΩ.nC)
Simulation time
(ns)
585 920 1375 @ -0.45V
Qg (pC) 273 433 626 31.39 20
Egt (pJ) 475.3 934 1640
EPC2040
(15V e-HEMT)
Qg to Miller
Plateau Start
Qg to Miller
End
Qg to Driver
Voltage RDS_on
(mΩ)
Ron.Qgt
(mΩ.nC)
Simulation time
(ns)
440 706 1250 @ 3.95V
Qg (pC) 202 328 585 30.22 18
Egt (pJ) 256 550 1340
25 V vs 15 V; d-HEMT vs e-HEMT
70
PCB-Demonstrators
PCB DEMO-1
• COTS Driver & Switches
to prove new components
one-by-one
• Develop PCB-Embedded
Magnetic Materials &
Devices
PCB DEMO-5
v1IHP driver, IHP
PWM Controller, 25
V IAF Switching
Bridge
PCB DEMO-4• 10–30 MHz LLC Resonant Converter, 12-1 V @ 2.5 ADC
• PCB-Embedded Tx (6:1:1) with Leakage Inductance for Resonant
Lr
- embedded commercial sheet powdered ferrite
- embedded Tyndall thin-film laminated metal alloy, Co-Zr-Ta MoS
• Gate-Driver chipset with 10 nV.s MoS signal-isolating transformer
• Low Voltage SR chip
0_txdr
signal coupling primary
driver
10Vns 50nH 1:1 MoS
600 X 762.8 µm
0_txhbdr
signal recovery secondary
driver for 100pF load
428 X 490 µm
0_lvdswdr
signal recovery secondary
driver for 3V3 synchronous
switches
1.0028 X 1.25096 mm
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Tyndall designed and fabricated world’s highest Q MoS inductor at 30MHz for on-chip power conversion< 45um height.
Low DCR
High QAC
Magnetic Component Technology based on Peak Q Frequency
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Magentic Component Technology based on Peak Q Frequency
The highest frequency bulkcommercial ferrite materials have max. PF @ ~ 9 MHz
(140 mT.MHz) for PV = 500 mW/cm3
[1]
PCB-Embeddable Magnetic Materials: 96+% Efficient
Inductors
(1) “Measurements and Performance Factor Comparisons of Magnetic Materials at High Frequency “, Alex Hanson et al., IEEE TRANSACTIONS ON POWER ELECTRONICS, NOVEMBER 2016
(2) “PCB Embedded Toroidal Inductor for 2MHz Point-of-Load Converter” R. Murphy, Tyndall, et al., G. Weidinger et al., AT&S, EU H2020 CIPS2020, “GaNonCMOS” www.ganoncmos.eu
(3) High Frequency Magnetic Sheet Materials –Performance Factor Comparisons and Design of Toroidal Inductors Embedded in PCB, R. Murphy, Tyndall, Zhibo Cao, IHP et al., APEC 2021
• A process for evaluating Magnetic Materials, [2]
• 5-15 nH/mm2 (isotropic mag material, closed-core)
• Low DCR – 0.05-0.5mR/nH
• Facilitates Coupled-L – halve inductor area
• Copper vias enormously help with heat conduction from PCB/ Magnetic Core to Surface
• => Can do BSAT limited Designs as opposed to Power Loss Density limited for wounds
Applying to PCB-
Embedded for
Stack-Level or
PwrSiP
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• PCB Demo 5 is a single phase closed loop buck converter
• This demo contains the following devices:
• IHP Controller v1
• IHP Driver v2
• IAF c4 25 V GaN HEMT Switching Bridge
• Low Loss Air-Core Inductor – Rac valid with large signal
• The aim of this demo is the testing & characterization of the IHP devices
• The converter was set operating at a 50% duty cycle at 2 MHz with a DC load of 1 A
• 12-6 V @ 2.2 MHz: Power Path Efficiency = 92.06%
• (incl. Driver and Controller) = 90.19%
• 12-2.5 V @ 2.2 MHz: Power Path Efficiency = 85%
IHP Driver IAF 11 mR,
22 mR
IHP PWM
PCB-DEMO-5 on standard test “motherboard”
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PCB Demo 5 – Closed Loop Buck Converter
PCB Demo 5 – Closed Loop Buck Converter -
@ 1 A
Closed Loop
Operation
• Parasitic inductances – PCB-level (optimised)
~ 300 pH at each power path node
• Very low IQ for Driver – 10’s nA
• 15 MHz controller capability but Dmin issue @ ~
5%
• PWM controllers are generally available to 2
MHz
• With monolithic switchers to 6 MHz
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PCB Demo 4: 12-1 V, 2.5A, 10+ MHz Converter with ZVS
& Embedded Tx
• Relatively small variation of switching frequency for wide line and load
variations
• Efficiency >90% with substrate embedded Resonant Lr/ Tx (6:1:1)
• Efficiency maintained high in the operating range (ZVS over the entire
operating range)
• Highest density PwrSiP Converter option: 10+ MHz
• Good for large step down ratio
• 12-LV or 48V POL for 48 V Server, Automotive
• Good for Isolated-Bias
• Good for Gate Driver Secondary Side Bias – Large Integrated
Switches
GaN switches – IAF
BVDSS=25V Synchronous CMOS
rectifiers – IHP
BVDSS=2.5V
Lm=280nH
Lr=28nH
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Comparison of Simulated and Measured Results
“Thin-film Magnetics-on-Silicon Integrated Transformer for Isolated
Signal and Power Coupling Applications”, Zoran Pavlovic et al.,
CIPS 2020
• MoS potentially allows
functional Tx isolation (IEC
950) for primary-side gate-
drive applications (not
crossing safety isolation
barrier)
• Requires thick oxide to
minimise CIO for CMTI with
high dVSN/dt
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PCB Demo 4: 12-1 V, 2.5A, 10+ MHz Converter
System Simulations with Gate Driver IC, LV SR, MoS-GD-Tx and PCB Embedded Tx
MoS_GD_TX
1:1
Embedded Tx/Lr 6:1:1 Signal Recovery and
SRs
Creates 10 nV.s pulses
for MoS Tx
Recovers HS, LS
DRives
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PCB Demo 4: 12-1 V, 2.5A, 10 MHz Converter, near f0
VCr
Vpri Tx
I_Lm
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• 300 nH LMAG , 30 nH Leakage Resonance, 95% target at 10 MHz, 2.5A DC output.
• Embedded commercial material, 3M15TF, achieves large-signal Q = 20 at 10 MHz
• Up to 4 sheets of 0.1mm film compatible with standard PCB core thickness – 23 mm OD
LLC Transformer
modelled in Maxwell
with Large signal
material-in -device
measured Q = 20 at
10 MHz, 17 mT.
WP = brown, WS =
pink, green
PCB Demo 4: 12-1 V, 2.5A, 10 MHz, PCB Embedded Tx+Lr
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Conclusions
• 1st Revision 25 V IAF GaN Switching Bridge achieves state-of-the art performance for GaN
• IHP Driver IC performs very well to 15+ MHz and has low IQ
• PwrSiP employing PCB embedded inductors with commercially available magnetic materials can achieve good large-signal Q (>20) and enable 96+% efficient inductors
• could be a very good solution for 10+ MHz and magnetising inductances << 300 nH
• They are 2-D devices => area challenged for L values > 200 nH but a good solution for > 10 MHz
• LLC Resonant Converter could be a very good solution for isolated bias: gate driver secondary side powering for Power Switches with integrated Gate Driver
• LLC Resonant Converter could be a very good solution for 48-LV POL
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Acknowledgement
This work was supported by the EU H2020 GaNonCMOS project (Grant Agreement No 721107).
o https://ganoncmos.eu/
The authors would like to acknowledge:o Central Fabrication Facilities (CFF) at Tyndall National Institute o Electronics Packaging and Reliability Group at Tyndall National Institute o AT&S Austria
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Results brief
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Look at our website to find more
information about our results:
www.ganoncmos.eu
Download our 15-page results brief!!!
Questions & answers
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Contacts
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Jean Pierre [email protected]
Functional Nanosystems Group – KU Leuven, Belgium
Paul [email protected]
Tyndall National Institute, Cork, Ireland
Norbert [email protected]
The Leibniz Institute for High Performance Microelectronics, Frankfurt/Oder,
Germany
Fouad [email protected]
Fraunhofer IAF, Freiburg, Germany
Gerald [email protected]
AT & S Austria Technologie & Systemtechnik AG, Leoben, Austria
Séamus O‘[email protected]
Tyndall National Institute, Cork, Ireland