the patti board gianluca lamanna (infnpisa) tel62 workshop – pisa – 30.1.2014
DESCRIPTION
DS90LV047Very simple board: DS90LV047 translatorsTRANSCRIPT
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The Patti Board
Gianluca Lamanna (INFNPisa)
TEL62 workshop – Pisa – 30.1.2014
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The PATTI board
• The PATTI board is a TELL1/TEL62 daughter board– Same TDCB form factor
• Main purpose: pulser for TDCB– 128 LVDS channels per board (512 channels per TELL1/TEL62)– Same TDCB connectors– Firmware, performance and primitive production stress test.
• Additional features: standalone testbench– LTU interface: you don’t need any L0TP to produce triggers– Production of SOB/EOB: you don’t need any «SPS»– Choke/error signals: test of readout perfomance
• Versatility:– All the functions are controlled with PP firmware
• Five boards in production: Birmingham, Frascati, Napoli e Perugia + spare
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• Very simple board: DS90LV047 translators
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PATTI layout
SAMTEC 200 pins – TEL62 connector
TDC connectors
LVTTL-LVDS translators
I/O:- 4 lemos (SOB, EOB,
TRIGGER, SPARE)- LTU connector- 8 LEDS - Choke/error
receiver
Power from Murata connectors: 3.3V and +5V,-5V
• The logic will be done in the PP
• Independent SOB,EOB production
• Trigger and choke/error
• Interface with LTU
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PATTI board
Tell1 connector
TDCB connectors
Power
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PATTI board
LTU
SOB, EOB, Trigger, Spare
Choke & Error
LEDs
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Why you need a PATTI?
• The PATTI is a pulser+”standalone” trigger processor
TEL62
TDCBPATTILT
U
TTCe
x
TTC
Choke/Error
TELL
1/ TE
L62
Sob/eob
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Firmware
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Choke/error generation
• Inspill and outspill time• Sob/eob signals to the LTU• Trigger sob/eob generation
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Pulser• Customizable clock
(several possibilities) to read a memory timeslot
• The memory is 32bx512– Each line is the configuration
of all the channels in a timeslot
• An external signal can be used to trigger the reading of the memory
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Trigger generation
• Several possibilities to generate the trigger:– Each pulse is a trigger– Downscaled – Random or periodic uncorrelated with the pulser– Memory– external
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Preliminary manual
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PATTI controller
• Configure the frequency of the pulser independently for each connector
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• 512 timeslots available for ch. Configuration– Ex: 0x0000000F ch.#0,1,2,3 ON 0x000000F0 ch.#4,5,6,7 ON 0x0000000F ch.#0,1,2,3 ON ……….
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• Individual channel masking
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• Trigger correlated/uncorrelated with the pulsers• Choke/error, programmable burst
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Status
Implemented Tested ValidatedElectric testsPulserClock variableTriggerSob/EobLTU comm.Choke/errorTEL62 versionGUITdspyManual
X
X
XX
XXX
X XX X
XXXX
XXX
(50%)
(20%)
(80%)
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Conclusions
• The PATTI is very useful build a complete test bench in the lab, both to test TDC capabilities and primitives generation
• The required board are in production (for the moment we have 4 boards in Pisa and 1 board at CERN)
• Firmware validation test will be completed in the soon • What you need:
• TEL62+TDCB to test, LTU+TTCex (in any case PATTI can produce triggers on LEMO), TDCB cables, some lemo and… .
• …for the moment you need a TELL1• Version for TEL62 foreseen
• Manual in preparation• GUI for control in preparation• TDSPY control in preparation