the making of the perfect mosfet final
TRANSCRIPT
The Making of The Perfect MOSFET
Alan ElbanhawyFairchild Semiconductor
PESC 2006 June 21, 2006
2 2
Outline
• MOSFET Components• Silicon Losses• Packaging Related losses• Gate Driver Losses• Integration and Design Optimization• Conclusion
3 3
MOSFET Components
Silicon
Package
Gate Driver
• Parasitic Inductances• Parasitic Resistances• Skin Effect• Thermal Resistance• Footprint• Price
• Conduction Losses• Dynamic Losses
• Distributed Parameters Effects, Rg
• Shoot Through• Reverse Recovery Losses• Price
• Rise and Fall Times• Sink and Source Currents • Source Resistance• Parasitic Inductances•Thermal Resistance• Footprint• Price
4 4
:= RonOpt VinputRg FOMKDrive fsw
Iload Vout Vdrive
Optimum on Resistance RDS(ON) as a function of load current and input voltage for the top MOSFET
Power dissipation as a function of the on resistance RDS(ON) and the load current
Conduction Losses
Optimum Range for RDS(ON)
5 5
Distributed and segmented parameters model
C
L
1 2 GateDriver
Synchronous Rectifier
Control MOSFET
R g 10
S 9
R g 9
0
S 1 0
0
C
G a t e D riv e r
1 2
S 1S 2
R g 2
L1 2
R g 1 0
H S
MOSFET Outlines
Gate lead
R g C g d
C g s
Q
C g d
C g s
RRRRRRRRRR d riv e r
C g dC g dC g dC g dC g dC g dC g dC g dC g d
C g sC g sC g sC g sC g sC g sC g sC g sC g s
D
2 14 36 58 710 9
6 6
Effect of distributed Rg-Cgs and die current Density
Gate voltage and drain currents at different Segments
Vgth
Uneven Power dissipation across the die during turn on!
The first and last segment currents for different combinations of Rg and Cgs
7 7
Clearly tri = Rg*Cgs*Constant. This equation shows that the current rise time is directly proportional to Rg*Cgs which dictates that both parameters must be minimized for better performance
Effect of Rg on Current Rise Time
Current Rise time, tri
tri
LambertW e
Vp Gm Cgs Rg tr Gm Vgth tr Gm IloadVp Gm Cgs Rg
Vp Gm Cgs Rg tr Gm Iload :=
Gm
LambertW e
Vp Cgs Rg Vgth trVp Cgs Rg
Vp Cgs Rg Vp Gm/( )
Current Fall time, tif
:= tif
ln
Vgth
VpRg Cgs
ln
Gm Vgth Gm Iload
Vp GmRg Cgs
8 8
Effect of Rg on MOSFET Vds Rise and Fall Times
VDS Rise time
VDS Fall time
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Lab Verification, tri, trv
Rg = 0 Ohm, Current Rise time
Rg=4.7 Ohm, Current rise time
Vds Rise time
Vds Rise time
10 10
Shoot Through in Synchronous Buck Converter
1 2
M1
L11 2
1 2
M2
0
C
• Conduction Losses• Dynamic Losses
• Distributed Parameters Effects, Rg
• Shoot Through• Reverse Recovery Losses• Price
1 2
M1
L11 2
1 2
M2
0
C
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Segm
ent Instantaneous P
ower
Gate Threshold Voltage
Gate-S
ource V
oltage
Segments Currents
Segments gate-source voltage
Distributed Parameters Model Solution, Voltages and Currents
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Distributed Rg Influence on Shoot Through Current
Drain Current
Gate-SourceVoltage
Gate thresholdVoltage
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Gate threshold voltage Vgth
Drain current
Gate to source voltage
Distributed CGD Influence on Shoot Through Current
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Distributed CGS Influence on Shoot Through Current
Gate thresholdVoltage
Gate-SourceVoltage
Drain Current
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Lumped parameters Model with Parasitics
C
L
1 2 GateDriver
Synchronous Rectifier
Control MOSFET
Full parasitic model
Added source and gate inductances
only
Simple model
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Loop Inductance Effects on Shoot Through
Loop Inductance Influence on Shoot Through Current
-2.00E+01
0.00E+00
2.00E+01
4.00E+01
6.00E+01
8.00E+01
1.00E+02
1.20E+02
1.40E+02
1.60E+02
9.89E-06 9.90E-06 9.91E-06 9.92E-06 9.93E-06 9.94E-06 9.95E-06 9.96E-06 9.97E-06 9.98E-06
Time
Dra
in C
urr
ent
- A
mp
0.2nH
0.4nH
1.0nH
2.0nH
4.0nH
6.0nH
8.0nH
10nH
No Inductor
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Reverse Recovery Current
-4.00E+01
-3.50E+01
-3.00E+01
-2.50E+01
-2.00E+01
-1.50E+01
-1.00E+01
-5.00E+00
0.00E+00
5.00E+00
9.90E-06 9.91E-06 9.91E-06 9.92E-06 9.92E-06 9.93E-06 9.93E-06 9.94E-06
Time - Seconds
Cu
rre
nt
- A
mp
Loop Inductance 0nH – 10nH
Loop Inductance Effects on Reverse Recovery
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Parasitics, Current Parasitics, Current rise and fall timesrise and fall times
Parasitics, Current Parasitics, Current sharingsharing
Fall time as a function of the Source inductance Ls and Load Current IL Vgth=1.5, gm=30
Source Inductance Effects
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Low Drain Current
High Drain Current
Source Inductance Effects
trg
LambertW ( )gm Kd Ls Vgth e
Kd gm
2Ls gm Vgth IL
Kd gm2Ls
gm Kd Ls
:=
Kd gm2Ls Kd gm
2Ls gm Vgth IL gm Kd
( )
:= tfg 2 Ls a IL a Ls Vgth
ln
a Vgth2
IL 2 Vgth a IL
a Vgth2
PdHS :=
IL2 ( )RdsonHS( )1 ( )TmaxHS Tamb Rpackage 0.5 Vcc IL fs ( )tr1 tf1
Rise time Fall time
Power Dissipation
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Parasitic Resistance and Skin Effect
Ts Ts t
Ipk i(t)
:= Id Ipk
n 1
2 Ipk ( )sin n ( )cos n tn
The Fourier series for a square wave
for n=20 and n=200
Frequency Spectrum
-1
-0.5
0
0.5
1
1.5
2
2.5
3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
Harmonic
Am
plit
ud
e
Square wave synthesis
Square wave Frequency Spectrum
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Package Effects, Parasitics and Skin Effects
Parasitic resistance as a function of frequency
BGA
49568.17374922.8 59179.030982.095504.0FF
DS eeR
09916.8085494.9275894.94F
DS eR
22 22
Skin Effect and Power Loss for HS MOSFET
Conduction loss (z-axes) as a function of the fundamental switching frequency f and the silicon on-resistance for an
The percentage error (z-axes) as a function of the switching frequency f and the silicon on-resistance for a
BGA 5 x 5.5 mm Package
SO8 Package
:= Pc Il2 ( )Rdson DC
:= Pcf Ipk2 2
( )Rdson DC
n 1
2 Ipk2
( )sin n 2( )Rdson f
n2 2
:= ErrorPercent100 ( )Ipk
2 ( )Rdson DC Pcf
Ipk2 ( )Rdson DC
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Package Thermals
• JC = 0.46 C/W• Heat sinking from the top of the package• Very low footprint and profile
Power Ball Grid Array BGA package is an example of the modern packages to address all the requirements of high frequency and high power densities modern DC-DC converters
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Gate Driver Influence on Losses
Uneven current
distribution
:= VgOpt1
2
Id2
bt Vo
VinId
2bb
1
Vo
Vin
( )Cint Cinb fs
Rg = 6
Rg = 4
Rg = 2
Rg = 6
Rg = 4
Rg = 2
Fall Time
Rise Time
Optimum gate Drive voltage
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Parasitic Drain Inductance EffectsParasitic Drain Inductance Effects
• Ls is PCB trace and package inductance, Cp is MOSFET Coss and stray capacitanceLs is PCB trace and package inductance, Cp is MOSFET Coss and stray capacitance
• For tr & tf >> tFor tr & tf >> tresres : :
• Overstress voltage = Overstress voltage =
• Power Dissipation = Power Dissipation =
For 20A, 10nH, 1nF and 1MHz:For 20A, 10nH, 1nF and 1MHz:
Overstress voltage = 60Volt Overstress voltage = 60Volt
Power Dissipation =4W = 4Power Dissipation =4W = 4
VdrainVdrain IindIind
Vin
L1 2
C
0
I
1
2L ID
2fs
IDL
C
Current as a function of L and time
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MOSFET Driver Comparison
70
72
74
76
78
80
82
84
86
88
90
0 20 40 60 80 100 120 140
Load Current
Eff
icie
nc
y %
Driver #1
Driver #2
Driver #3
Why match MOSFETs and gate drivers?
• Use one VRM board with three different drivers• All MOSFETs, Inductors and Filter capacitors are identical in all three cases• The very same PCB• The same test setup and test condition on an ATE
How will the efficiency curves be different?
Gate Driver Influence on Losses
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Current Density (A/m^2)Top MOSFET On
Current Density (A/m^2)Bottom MOSFETs On
Integration and Design Optimization
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Conclusion
The pursuit of the perfect MOSFET must be launched simultaneously on three fronts, silicon, package and gate driver.
The optimization of the MOSFET parameters requires an extremely careful consideration of the individual parameter and its effect on all the loss mechanisms in a given power MOSFET and all of these in conjunction with each other and the effect of a given combination of these parameters on the overall performance of the device in the intended application which in our case is a synchronous buck converter
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Thanks for your attentionThanks for your attentionQuestions?Questions?