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The Inclusive (Measurement ) FVTX aka iFVTX

sponsored by LANL-DR in FY ‘06-08

• FPIX Chip

• Module/Hybrid

• Testcard

• Pixel Plane

• Assembly/Integration

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The Interaction Region at Phenix

Space for Vertex upgrade detectors

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Outline

From Hybrid to Module

From Module to Testcard

From Testcard to Pixel Plane

From Pixel Plane to Station

From Station to Full Detector

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Pixel Module

FPIX2

Silicon Sensor

HDI

Support Structure

Wire bonds

NO

T TO

SCA

LE

VTT

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8 Chip Module

• Dimensions:Dimensions: 111.0mm x 11.1mm 111.0mm x 11.1mm + 2x 10.0mm x 11.1 mm tabs+ 2x 10.0mm x 11.1 mm tabs• Line width: Line width: 5050mm• Line to line clearance: Line to line clearance: 5050mm• Metal layer thickness: Metal layer thickness: 1212mm

• Number of layers: Number of layers: 4 4 • Via pad/hole: Via pad/hole: 150/70150/70mm• Lamination: Lamination: 2525m epoxym epoxy• Film thickness (polymide): Film thickness (polymide): 5050mm

HDI designed by Fermilab/ made by (?) Mircoconex/Dyconex /CERN:HDI designed by Fermilab/ made by (?) Mircoconex/Dyconex /CERN:

HDI CAD top layer.

HDI + 8 bare die chips.

HDI + 8 chips with detector.

(SINTEF PSPRAY)

Several iterations, now minimal HDI

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Production Flow

Chip and Sensor Test

Hybridization by VTT

Hybrid Test

HDI Electrical Test

Module Assembly

Test-card Assembly

Test and Burn-in

Pixel Plane Assembly

Test and Burn-in

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Pixel Module Assembly

• Fixture with Vaccum Chuck

• Gluing of FPIX to HDI

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Testcard and Wire Bonding

• Testcard for each module

• Gluing of module to card

• Wirebonding of HDI to card

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Ready Test Card

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PCI-based Test stands – PTA card

Perform module test• ‘PINGA’ test software• Initial characterization with inject pulser• Hit map • Absolute calibration • Burn-in (normal operation for 72 hours)• Repeat hit map• Q&A and module classification

http://www-ese.fnal.gov/Phenix/PingaHelp/index.html

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Module Removal for Plane Assembly

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4 Stations in FVTX Frame

2 Planes per Station

6 Identical Planes for Stations 2,3,4

Smaller Plane for Station 1

Room Temperature

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PCB

The Layout of a Plane

Cooling

TPG

FPIX on HDI

Power

Bias

Pulser

LVDS Output

Voltage

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The Actual Plane and Stations

Flex Blades (Temperature compensation)

Two Planes Sandwich to get Station• Modules Inside• Connectors Outside

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Large Pixel Plane (10 modules)

Active components are Repeater and Regulator

Delivery Imminent

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Small Pixel Plane Concept (4-5 Modules)

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Module Mounting and Cooling

PEEK tube

HDI

TPGSensor

Readout Chip

Placing and wirebonding

Cooling with Fluor-carbon at temperature that keeps the

HDI at assembly temperature

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Cables to Pole Face

Five flat cables either side of active area on plane

20 per large station, 12 per small station , total 72

48 low voltage, high voltage cables

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Status and Plans

Status

• All FPIXs are procured• All Si-detectors are procured• 15 Hybrids are delivered• 25 HDIs delivered, preparing production order• 10 module PCBs delivered• Several test cards are ready• Wire bonding at Si-det• Test stands are ready• Assembly gigs are ready

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Preproduction and Production Plan

Proto (spare)• TPG• TPG + Cooling• Test• PCB• Mate PCB TPG• Test• 15 Modules on Cards• Test• Assemble Plane• Test

Production• TPG• TPG + Cooling• Test• PCB 3 small - 6 large• Mate PCB TPG• Test• 88 Modules on Cards• Test• Assemble Planes• Test• Assemble Stations• Cage• Assemble Detector

VTT Rework ?

• 15 FPIX only Modules on Cards

• Test• Assemble Plane• Test

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iFVTX

FPIX 2.1

20 Module Station

8 chip module

4 Pixel Planes