the gbtia, a 5 gbit/s radiation-hard optical receiver for the slhc upgrades

The GBTIA, a 5 Gbit/s radiation-hard optical receiver for the SLHC upgrades

Mohsine Menouni, CPPM - Marseille

Gui Ping, SMU - Dallas - Texas

Paulo Moreira, CERN - Genève

TWEPP 2009 : Paris, France / September 21-25 [email protected] 2

Outline

Introduction

Specifications of the GBTIA chip

Receiver architecture

Transimpedance design

Limiting amplifier design

Pin diode bias and leakage current effect

Measurement results

Conclusion and Perspectives


GBTIA Specifications

The GBTIA is a regenerative optical receiver for data transmission up to 5 Gbit/s

It provides the proper signal level for the clock recovery and deserializer stages

Main specifications:

Bit rate : 5 Gbit/s (min)

Total jitter : < 40 ps p-p

Sensitivity: 20 μA p-p (-17 dBm) for BER = 10-12

pin diode capacitance Cd ~ 400 fF

Dark current : 0 to 1 mA

Power supply : 2.5 V ± 10%

Power consumption < 250 mW

Large range of temperature : From -20 C to 80 C

Die size: 0.75 mm × 1.25 mm

Radiation tolerant (up to 200 Mrad)


Overview of the GBTIA design Integrating the TIA with the LA in the same chip presents

the risk to degrade performances Propagation of the crosstalk noise trough power supplies or the

substrate

A fully differential architecture Better tolerance to the supply noise

However the input referred noise (thermal noise) is larger than for the single ended

The power consumption is higher

The photodiode is AC coupled to the TIA No Need of an offset control circuit at the output of the TIA

A high value of the low cut off frequency

Parasitic of the coupling integrated capacitances limits the bandwidth

Transimpedance amplifier (TIA) Define the sensitivity of the optical receiver

Wide bandwidth

Low noise

Limiting Amplifier and output buffer (LA) Provide a clean signal to the output

High gain

Wide bandwidth

Offset level compensation

Additional features : Internal voltage regulator (with enable/disable control)

leakage-current indicator

Carrier-detect and signal-strength indicators

Squelch function (with enable/disable control)


Transimpedance Amplifier

Shunt feedback amplifier is widely used for high speed receiver designs

To increase the bandwidth :

Decrease the feedback resistor

Increase the amplifier open loop gain

Decrease the input node capacitance

To minimize the thermal noise :

Increase the feedback resistor

Decrease the input node capacitance

Increase the amplifier transconductance

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Bandwidth extension technique

In order to maintain a low level of noise with keeping a large bandwidth, the shunt peaking technique is used in the design

Shunt peaking

Introduction of an inductance in series with the load resistance

Enhances the bandwidth

The frequency response is characterized by the ratio m

Factor m

Normalized f3dB Response

0 1.00 No shunt peaking

0.32 1.60 Optimum group delay

0.41 1.72 Maximally flat

0.71 1.85 Maximum bandwidth

CRmL .. 2


Implemented TIA structure

Differential structure is adopted

Inductive peaking

The target bandwidth of 3.5 GHz is achieved for the worst case of process and temperature (simulations including parasitic)

High transimpedance gain (RF=380 )

Low level of input referred noise

Cascode

Reduces the Miller effect

Current density is optimized

High current density needed to achieve high cut off frequency for the input transistor

Input transistor size optimized for an input capacitance of 700 fF

2 V supply required

2 V

In+In-

380 380

Out- Out+

2 nH 2 nH

200 200

7.8 pF 7.8 pF


Limiting Amplifier requirements Considering the sensitivity and the gain of the TIA :

the photocurrent is converted to a minimum voltage of 12 mV pp

This voltage is amplified by the Limiting Amplifier to reach the proper voltage necessary for the following stages

The design of the LA demonstrates a high gain to achieve the 400 mV pp

Gain is around 40 dB in typical condition (28 dB in worst-case scenario)

The minimum overall bandwidth is 3.5 GHz

The noise contribution of this stage is maintained negligible : The input referred noise is maintained lower than 850 µV

RMS (12mV/14) for a BER of 10E-12

The input capacitance of the LA is sufficiently low so that it does not reduce the TIA bandwidth

The number of stages is set to 5 (4 LA + a buffer) More stages introduce a high power dissipation

Offset cancellation is incorporated in LA block to prevent the mismatch in the differential amp from saturating the latter stages

In order to maintain a wide bandwidth while delivering large current to the load, the amplifiers stages in the LA are designed to have increasingly larger size and current

Minimize the load capacitance seen by the previous stage

Allow bandwidth extension

The gain of the first stage (LA1) is set to a high value to reduce the noise

LA1 LA2 LA3 LA4 BufferTIA

2 mA 2 mA 4 mA 8 mA 8 mA

Limiting Amplifier

Offset cancellation


Limiting Amplifier stage

High bandwidth topology for each stage

Cherry and Hopper structure

gm stage followed by shunt-feedback stage

Second stage uses active “inductors”

by active inductive peaking, the bandwidth is increased by 34% over a resistive loaded topology.


Output Buffer Stage

Needs to be able to deliver 4 mA current to a 50 load at full speed

The output stage needs to be able to fully switch 8 mA taking into consideration double termination.

The buffer has not to present too large capacitance to the preceding stage

Vinn

Vinp

50

Off chip 50 transmission line

Voutp

Voutn

8 mA


Pin diode leakage current effect

The pin diode leakage current increases with the radiation dose and can reach a value of 1 mA for a high dose level

AC coupling is adopted for the fully differential receiver:

The AC coupling capacitance is integrated in the chip

The value is made as high as possible : 7.8 pF

In order to maintain the low cutoff frequency to a reasonable value we need a high value for the photodiode bias resistance

Since we have to maintain a voltage across the photodiode, this resistance is implemented with active device

Photodiode biasing

The voltage across the pin diode decreases to 0.6 V for Vdd = 2 V

The low cut-off frequency increases

The simulated cut off frequency is around 1 MHz for IDC = 1 mA

Still compatible with the GBT encoding

The DC level has an effect on the noise and the sensitivity

For the low level of the leakage current, the shot noise is negligible comparing to the thermal noise

When the DC level is around 1 mA, the shot noise level becomes comparable to the thermal noise

A sensitivity degradation is expected at the end of life of the SLHC

Simulations show a sensitivity loss of 3-4 dB

Vdd

IDC

IDC CC

CC

iAC

iAC

Long consecutive identical bits


Outline

Introduction

Receiver architecture

measurement results

Chip photograph and test boards

Eye diagram measurements

Bit Error Rate estimate

Performances versus power supply

BER measurements with the GBT protocol and error correction

Radiation effects

Influence of the optical DC level on the BER

Summary and Perspectives

Thanks to :

Luis Amaral, Jan Troska and Csaba Soos

for their help with the test setup


Chip photograph and test boards 0.13-μm bulk CMOS process.

IBM CMOS8RF-LM technology, a standard eight-metal-layer

The n-MOSFET fT of this technology is in the range of100–120 GHz

Die size: 0.75 mm × 1.25 mm

2 PCB boards were designed in order to evaluate the GBTIA performances

Board for optical tests Use a pin-diode as a signal source

PDCS60T-XS : high speed photodiode Pin diode from Enablence

Top illuminated 10 Gb/s photodiode

Low capacitance: 240 fF

Responsitivity : 0.9 A/W at = 1310 nm

The connection between the TIA and the pin diode is made very short < 200 µm

Board for electrical tests PIN diode is replaced by an electrical network

Voltage source to adjust the input current

Input Capacitance is set to 500 fF

PCB parasitic capacitances were minimized

This board was used essentially for irradiation test

Bandgap reference

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Input-

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output-

Pin

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ng


Eye diagram measurements (1/2)

12 Gbit/s Serial Pattern Generator

Commercial 10 Gbit/s Optical transmitter

18 GHz BW serial data analyzer

Optical attenuator to adjust the optical level for the pin diode

PRBS Generator

Agilent N4903A

Optical TxOptical

Attenuator

GBTIA Test Board

Lecroy SDA18000

data databclock

ch1

ch2

ckin

DC blocking connectors

outp

outn


Eye diagram measurements (2/2)

Measured differential eye diagrams at 5 Gbit/s for different optical power at the input (-6 dBm and -18 dBm)

Well opened eye diagram for -6 dBm and still correct at 18 dBm

The test PRBS sequence length is 27-1

A constant output swing of 400 mV

For a power supply of 2 V the power consumption is 90 mW (120 mW at 2.5 V)

For -6 dBm input :

Rise time = 30 ps

Total jitter = 0.15 UI @ BER = 10-12

UI = 200 ps

For -18 dBm input :

Rise time = 60 ps

Total jitter = 0.55 UI @ BER = 10-12

Eye diagram 5 Gbit/s optical power = -6 dBm

Eye diagram 5 Gbit/s optical power = -18 dBm


Bit Error Rate measurements

Test set up to evaluate the BER of the optical link using the GBTIA chip as a receiver

The Bit Error Rate Tester (BERT) is the Xilinx platform ML421 Virtex-4 Rocket-IO FPGA

Transceivers operating up to 6.5 Gbit/s

BER calculation is based on the comparison of the transmitted and the received data

Measuring a very low BER is time consuming

Low BER is determined using extrapolation from the measurements of BER versus the input optical power

Optical Tx Optical

Attenuator

GBTIA Test Board

Lecroy SDA18000

din dinb

ch1

ch2

ckin

DC blocking connectors

Bit Error Rate Tester (BERT) Xilinx ML421

platform

Clock generator

dout doutb

ckin

ckinb

ck ckb


Bit Error Rate Estimate

Vdd = 2 V and T = 25 °C

Data pattern : PRBS7

The sensitivity for a BER of 10-12 is estimated around -19 dBm

Bit Error Rate versus Input Optical Level Data pattern PRBS7

1E-14

1E-12

1E-10

1E-08

1E-06

1E-04

-26 -24 -22 -20 -18 -16 -14

Optival power (dBm)

BE

R


Performances versus power supply

BER versus Input OpticalPower

1E-14

1E-12

1E-10

1E-08

1E-06

1E-04

1E-02

-30 -25 -20 -15 -10 -5

Optical Power (dBm)

BE

R

BER @1.8V BER @2.0V BER @2.2V


BER measurements with the GBT encoding

The SEU on the photodiode are likely to be the main source of errors

In the GBT chip an error correction system is implemented

Reed-Solomon error-correcting encoder/decoder

For this test set up, the GBT encoder decoder was implemented in virtex-4 FPGA used in the BERT platform

Without error correction, the sensitivity of the optical receiver still around -19 dBm

The sensitivity is improved by 2 dB if the correction encoder is enabled

Bit Error Rate versus Input Optical Level Data pattern : GBT encoding

1E-14

1E-12

1E-10

1E-08

1E-06

1E-04

1E-02

-26 -24 -22 -20 -18 -16 -14

Optival power (dBm)

BE

R

GBT prtocol

GBT protocol with errorcorrection


Eye diagram versus the total dose

Electrical board used for irradiation test

Irradiation test done at CERN using Xray facility

Only the GBTIA chip is submitted to Xray beam

No degradation is observed after a dose rate of 200 Mrad

200 Mrad eye diagram (input=500 mV )

200 Mrad eye diagram (input=50 mV )

Prerad eye diagram (input=500 mV )

Prerad eye diagram (input=50 mV )


BER versus the total dose

BER versus the total dose

1E-14

1E-12

1E-10

1E-08

1E-06

1E-04

-24 -22 -20 -18 -16

Equivalent optical input level (dBm)

BE

R

Prerad

10M

100M


Influence of the optical DC level on the BER

the leakage current of the photodiode increases to 1 mA at a high level of dose

In order to measure the influence of this leakage current, the pin diode is illuminated by an additional DC laser source

In this case we checked that the integrated bias circuit ensures a sufficient voltage across the pin diode

We don’t observe a notable degradation of the BER coming from the effect of the low cut-off frequency

The value of this frequency still compatible with the GBT encoding data

The power penalty introduced by the shot noise of the leakage current is around 4 dB

Bit Error Rate versus the DC Optical Level Data pattern : GBT encoding

1E-14

1E-12

1E-10

1E-08

1E-06

1E-04

-26 -24 -22 -20 -18 -16 -14 -12 -10

Optical power (dBm)

BE

R

DC courant = 0

DC current = 0.45 mA

DC current = 0.92 mA

Power penalty


Conclusion and Perspectives

Main Specifications in terms of bandwidth and sensitivity are respected

Eye diagram is well opened at 5 Gbit/s

Sensitivity of -19 dBm for a BER of 10-12

The effect of the leakage current is estimated

The sensitivity is degraded by 4 dB

The value of the low cut off frequency still compatible with the data encoding used for the GBT

Radiation effects :

Radiation tolerance is proven up to 200 Mrad

We have to estimate the single event upset tolerance

Work has started to encapsulate the GBTIA and the photodiode in a TO Package

A final design is scheduled to implement the additional features :

Leakage-current and signal-strength indicators

Carrier-detect

Squelch function (with enable/disable control)

Bit rate 5 Gbit/s

Transimpedance gain 20 k(typ)

Output voltage ± 0.2 V (50 )

Sensitivity for BER =10-12 -19 dBm

Supply voltage 2.5 V ± 10%

Power consumption 120 mW

Radiation tolerance > 200 Mrad

Penalty for high dark current 4 dB

the gbtia, a 5 gbit/s radiation-hard optical receiver for the slhc upgrades

Documents

input capacitance

noise thermal noise

wlow level of input

low level of noise

input node capacitanceincrease

input node capacitanceto

proper signal level

ffdark current