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technical handbook
Book
Integrated circuits
Part 6a
Professional analog ICs
MULLARD
a 1983
PROFESSIONAL ANALOG ICs
CONTENTS
FUNCTIONAL AND NUMERICAL INDEXMAINTENANCE TYPE LIST
GENERAL
PACKAGE OUTLINES
OPERATIONAL AMPLIFIERS =
TELECOMMUNICATIONS = jv
DOMESTIC APPLIANCES
GENERAL INDUSTRIAL
r? BOOk 4 Part 6a
ntegrated circuits
Professional analog ICs
MULLARD LTD., MULLARD HOUSE, TORRINGTON PLACE,
LONDON, WC1E7HD
Telephone 01-580 6633 Telex: 264341
The Mullard technical handbook system.
The Mullard Technical Handbook is made up of four sets ofBooks, each comprising several parts:-
Book 1 (light blue) Semiconductor Devices
Book 2 (orange) Valves and Tubes
Book 3 (green) Components, Materials andAssemblies
Book 4 (purple or Integrated Circuits
dark blue)
Book 4, Integrated Circuits, comprises the following parts:-
Part 1 Bipolar ICs for radio and audio equipment
Part 2 Bipolar ICs for video equipment
Part 3 ICs for digital systems in radio, audio andvideo equipment
Part 4 Digital ICs- CMOS
Part 5 High-speed CMOS
Part 6 Analog ICs (Signetics)
Part 6a Professional analog ICs
Part 7 Bipolar memory ICs
Part 7a Integrated fuse logic
Parts TTL Logic ICs
Part 9 Microprocessors, microcomputers andperipheral ICs
.a comprehensive data library
Most of the devices for which full data is given in these
books are those around which we would recommend equipment
to be designed. Where appropriate, other types no longer
recommended for new equipment designs but generally
available forequipment production, are listed separately. Data
sheets for these types may be obtained on request. Older devices
for which data may be obtained on request are also included in
the index of the appropriate part of each book.
Because the Technical Handbook system forms a
comprehensive data reference library the current Mullard Quick
Reference Guides should always be consulted for details of the
Mullard preferred range.
The data contained in these books is as accurateand up to date
as possible at the time of going to press. It must be understood,
however, that no guarantee can be given on the availability of the
various devices, or that their specifications may not be changed
before the next edition is published.
Each part is reviewed regularly, and revised and re-issued where
necessary. Revisions to previous data are indicated by an arrow in
the margin.
Requests for copies of Quick Reference Guides and individual
data sheets (please quote the type number) should be sent tor-
Technical Publications Department, Mullard Limited,
New Road, Mitcham, Surrey CR4 4XY Telex 22194.
Prices and availability information for Mullard componentsshould be obtained from Mullard House, orfrom one of the
Mullard Distributors listed on the back cover.
I
Milliard Data BaseFor the equipment designer,
technical information on
electronic components is
vital. Mullard market the
widest range of components
in the U . K, . supported by a
comprehensive information
service - the Mullard Data
Base.
Brief details are given
here. For further informa-
tion and an order form,
please write to:-
Technical Publications Dept.
Mullard Limited.
New Road. Mitcham,
Surrey CR4 4XY
Regular Publications
Mullard Bulletin
A must for designers, this
bi-monthly, newspaper -style
publication briefly describes
new components and offers
ler information on subjects
of interest.
Consumer Electronics
A review, in newspaper style,
published every four months.
Articles and features of
interest to those in the
consumer electronics industry,
with emphasis on television
technology and allied subjects.
Bulletin
fr-.<\ectoi ,yali
ftoes
*J§^?
Technical Brochures
and Range Leaflets
Mullard publish hundreds of
it brochures on
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application. Make sure your
name is on the mailing
the Mullard Bulletin, which
describes and offers newpublication
Presteltoo!
Mullard publication;-'
also be ordered dire*
through PRESTFLThe Mullard data base
begins on page 556201
Electronic Componentsand Applications
Aquar' ical journal
covering, in depth,
developments in electronics
based on the work of Philips,
ind Milliard
laboratories Please ask for a
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eagb*
Bts&
Quick reference guides
All products marketed by
Mullard are listed
alpha- numerically and
described briefly in these
guides. Part 1 covers passive
components, discrete
semiconductors, and valves
and tubes: Part 2 deals with
integrated circuits, including
Signetics.
Technical Data Sen/ice
This service provides deta.
up-to-date information on the
characteristics and
performance of Mullard
components.
criberstoanyorallol
the four handbook sections
veall relevant handbooks,
looseleaf binders, monthly
i ngs of new data sheets,
and new handbook parts as
they are published.
For those not wishing to
subscribe to the Data Service,
tbook parts can be
purchased individually.
Individual data sheets are
available free-of-charge. and
can be obtained by quoting the
type num!
**-*
**-*******
FUNCTIONAL AND NUMERICAL INDEX
MAINTENANCE TYPE LIST
INDEX
SELECTION GUIDE BY FUNCTION
type number function page
OPERATIONAL AMPLIFIERS
TCA220 triple operational amplifier
TCA520B; D operational amplifier
TEA1016 dual operational amplifier and comparator
TELECOMMUNICATIONS
Modulators
TBA673 ring modulator for telephony and industrial equipment
TCA240; D dual long-tailed pair/double-balanced modulator
3541
47
57
75
A.F. amplifiers
TBA915GTCA210;TTCA980G
I.F./A.F. circuits
TCA770A; DTDB108Q
audio amplifier
audio amplifier
microphone amplifier
i.f. limiting amplifier, FM detector and a.f. preamplifier
i.f. limiting amplifier, FM detector and a.f. amplifier
Telephone transmission and DTMF circuits
TEA1021P; D DTMF generator for telephone dialling
TEA1042 telephone transmission circuit for handsfree loudspeaking
TEA1043P; D DTMF generator for telephone dialling
TEA1044P; D DTMF generator for telephone dialling
TEA1046P; D DTMF/speech transmission IC for telephone applications
,TEA1053; 1054 telephone transmission circuits
TEA1055 telephone transmission circuit
TEA1060; 1061 versatile telephone transmission circuits with dialler interface
TEA1062; 1063 versatile telephone transmission circuits
DOMESTIC APPLIANCES
TCA280A general-purpose triggering circuit
TDA1023 proportional-control triac triggering circuit
TDA1024 on-off triac triggering circuit
TEA1010; T touch-controlled lamp dimmer circuit
TEA1058; T touch-controlled lamp dimmer circuit
61
67
91
85
97
<103
109
123
129
135
137
149
161
175
189
203
217
231
237
-\rMarch 1983
INDEX
SELECTION GUIDE BY FUNCTION (continued)
type number function page
GENERAL INDUSTRIAL
Control circuits for switched-mode power supplies (SMPS)
TDA1060; A; B control circuits for SMPSTEA1039 control circuit for SIMPS
Motor drive circuits
SAA1027SAK150BT
stepping motor drive circuit
servo-motor control circuit
Transistor arrays
CA3046 five-transistor array
TDA3081 seven-transistor array
TDA3083; D five-transistor array
Miscellaneous
SAA1029TDA1540DTEA1017
universal industrial logic and interface circuit
14-bit DAC with 85 dB S/N ratio
13-bit series-parallel converter
271
307
249
263
245
293
297
255
287
301
March 1983^\r
NUMERICAL INDEX
INDEX
type number function page
CA3046 five-transistor array
SAA1027 stepping motor drive circuit
SAA1029 universal industrial logic and interface circuit
SAK150BT servo-motor control circuit
TBA673 ring modulator for telephony and industrial equipment
245
249
255
263
57
TBA915G audio amplifier
TCA210 audio amplifier
TCA210T audio amplifier
TCA220 triple operational amplifier
TCA240 dual long-tailed pair/double-balanced modulator
61
67
67
35
75
TCA240D dual long-tailed pair/double-balanced modulator
TCA280A general-purpose triggering circuit
TCA520B operational amplifier
TCA520D operational amplifier
TCA770A i.f. limiting amplifier, FM detector and a.f. preamplifier
75
189
41
41
85
TCA770D i.f. limiting amplifier, FM detector and a.f. preamplifier
TCA980G microphone amplifier
TDA1023 proportional-control triac triggering circuit
TDA1024 on-off triac triggering circuit
TDA1060 control circuit for switched-mode power supply
85
91
203
217
271
TDA1060A control circuit for switched-mode power supply
TDA1060B control circuit for switched-mode power supply
TDA1540D 14-bit DAC with 85 dB S/N ratio
TDA3081 seven-transistor array
TDA3083 five-transistor array
271
271
287
293
297
TDA3083D five-transistor array
TDB1080 i.f. limiting amplifier, FM detector and a.f. amplifier
TEA1010 touch-controlled lamp dimmer circuit
TEA1010T touch-controlled lamp dimmer circuit
TEA1016 dual operational amplifier and comparator
297
97
231
231
47
TEA1017 13-bit series-parallel converter
TEA1021P DTMF generator for telephone dialling
TEA1021D DTMF generator for telephone dialling
TEA1039 control circuit for switched-mode power supply
TEA1042 telephone transmission circuit for handsfree loudspeaking
301
103
103
307
109
~^rMarch 1983
INDEX
NUMERICAL INDEX (continued)
type number function page
TEA1043P DTMF generator for telephone dialling
TEA1043D DTMF generator for telephone dialling
TEA1044P DTMF generator for telephone dialling
TEA1044D DTMF generator for telephone dialling
TEA1046P DTMF/speech transmission IC for telephone applications
TEA1046D DTMF/speech transmission IC for telephone applications
TEA1053 telephone transmission circuit
TEA1054 telephone transmission circuit
TEA1055 telephone transmission circuit
TEA1058 touch-controlled lamp dimmer circuit
TEA1058T touch-controlled lamp dimmer circuit
TEA1060 versatile telephone transmission circuit with dialler interface
TEA1061 versatile telephone transmission circuit with dialler interface
TEA1062 versatile telephone transmission circuit
TEA1063 versatile telephone transmission circuit
123
123
129
129
135
135
137
137
149
237
237
161
161
175
175
MAINTENANCE TYPE LIST
SAA1114;ZSAK140TAA960TAA970TBA221D
TBA915TCA410A;B;DTCA580TCA680; B; DTCA980
TDA0301DTDA0319DTDA0324DTDA0358DTDA0555D
TDA0723DTDA0741DTDA0748DTDA1034;NTDA1034B;NB
successor type: TBA915G
successor type: TCA980G
TDA1034D;NDTDA1458DTDA3082TDA4250B;
March 1983^r
GENERAL
Type designation
Rating systems
TYPEDESIGNATION
PRO ELECTRON TYPE DESIGNATION CODEFOR INTEGRATED CIRCUITS
This type nomenclature applies to semiconductor monolithic, semiconductor multi-chip, thin-film,
thick-film and hybrid integrated circuits.
A basic number consists of:
THREE LETTERS FOLLOWED BY A SERIAL NUMBER
FIRST AND SECOND LETTER
1. DIGITAL FAMILY CIRCUITS
The FIRST TWO LETTERS identify the FAMILY (see note 1).
2. SOLITARY CIRCUITS
The FIRST LETTER divides the solitary circuits into:
S : Solitary digital circuits
T : Analogue circuits
U : Mixed analogue/digital circuits
The SECOND LETTER is a serial letter without any further significance except 'H' which standsfor hybrid circuits.
3. MICROPROCESSORS
The FIRST TWO LETTERS identify microprocessors and correlated circuits as follows:
Microcomputer
Central processing unit
Slice processor (see note 2)
Correlated memories
Other correlated circuits (interface, clock, peripheral controller, etc.)
4. CHARGE-TRANSFER DEVICES AND SWITCHED CAPACITORS
The F I RST TWO LETTERS identify the following:
NH : Hybrid circuits
NL : Logic circuits
NM : Memories
NS : Analogue signal processing, using switched capacitors
NT : Analogue signal processing, using CTDsNX : Imaging devices
NY : Other correlated circuits
MA
MBMDME
Notes
1. A logic family is an assembly of digital circuits designed to be interconnected and defined by its
basic electrical characteristics (such as: supply voltage, power consumption, propagation delay,
noise immunity).
2. By 'slice processor' is meant: a functional slice of microprocessor.
~\rDecember 1982
TYPEDESIGNATION
THIRD LETTER
It indicates the operating ambient temperature range.
The letters A to G give information about the temperature:
AB
C
DE
F
G
temperature range not specified
to + 70 °C-55to + 125 °C-25 to + 70 °C-25 to + 85 °C-40 to + 85 °C-55 to + 85 °C
If a circuit is published for another temperature range, the letter indicating a narrower temperature
range may be used or the letter 'A'.
Example: the range to + 75 °C can be indicated by 'B' or 'A'.
SERIAL NUMBER
This may be either a 4-digit number assigned by Pro Electron, or the serial number (which may be a
combination of figures and letters) of an existing company type designation of the manufacturer.
To the basic type number may be added:
A VERSION LETTER
Indicates a minor variant of the basic type or the package. Except for 'Z', which means customized
wiring, the letter has no fixed meaning. The following letters are recommended for package variants:
C
DF
L
P
QT
U
for cylindrical
for ceramic DILfor flat pack
for chip on tape
for plastic DIL
forQILfor miniature plastic (mini-pack)
for uncased chip
Alternatively a TWO LETTER SUFFIX may be used instead of a single package version letter, if the
manufacturer (sponsor) wishes to give more information.
FIRST LETTER: General shape SECOND LETTER: Material
C : Cylindrical CD : Dual-in-line (DIL) GE : Power DIL (with external heatsink) MF : Flat (leads on 2 sides) P
G : Flat (leads on 4 sides)
K : Diamond (TO-3 family)
M : Multiple-in-line (except Dual-, Triple-, Quadruple-in-line)
Q: Quadruple-in-line (OIL)
R : Power QIL (with external heatsink)
S : Single-in-line
T : Triple-in-line
A hyphen precedes the suffix to avoid confusion with a version letter.
Metal-ceramic
Glass-ceramic (cerdip)
Metal
Plastic
10 December 1982^r
GENERAL
RATING SYSTEMS
The rating systems described are those recommended by the International Electrotechnical Commission
(IEC) in its Publication 134.
DEFINITIONS OF TERMS USED
Electronic device. An electronic tube or valve, transistor or other semiconductor device.
Note
This definition excludes inductors, capacitors, resistors and similar components.
Characteristic. A characteristic is an inherent and measurable property of a device. Such a property
may be electrical, mechanical, thermal, hydraulic, electro-magnetic, or nuclear, and can be expressed
as a value for stated or recognized conditions. A characteristic may also be a set of related values,
usually shown in graphical form.
Bogey electronic device. An electronic device whose characteristics have the published nominal values
for the type. A bogey electronic device for any particular application can be obtained by considering
only those characteristics which are directly related to the application.
Rating. A value which establishes either a limiting capability or a limiting condition for an electronic
device. It is determined for specified values of environment and operation, and may be stated in any
suitable terms.
Note
Limiting conditions may be either maxima or minima.
Rating system. The set of principles upon which ratings are established and which determine their
interpretation.
Note
The rating system indicates the division of responsibility between the device manufacturer and the
circuit designer, with the object of ensuring that the working conditions do not exceed the ratings.
ABSOLUTE MAXIMUM RATING SYSTEM
Absolute maximum ratings are limiting values of operating and environmental conditions applicable to
any electronic device of a specified type as defined by its published data, which should not be exceed-
ed under the worst probable conditions.
These values are chosen by the device manufacturer to provide acceptable serviceability of the device,
taking no responsibility for equipment variations, environmental variations, and the effects of changes
in operating conditions due to variations in the characteristics of the device under consideration and
of all other electronic devices in the equipment.
The equipment manufacturer should design so that, initially and throughout life, no absolute maximumvalue for the intended service is exceeded with any device under the worst probable operating con-
ditions with respect to supply voltage variation, equipment component variation, equipment control
adjustment, load variations, signal variation, environmental conditions, and variations in characteristics
of the device under consideration and of all other electronic devices in the equipment.
-\rOctober 1977 11
GENERAL
DESIGN MAXIMUM RATING SYSTEM
Design maximum ratings are limiting values of operating and environmental conditions applicable to a
bogey electronic device of a specified type as defined by its published data, and should not be exceed-
ed under the worst probable conditions.
These values are chosen by the device manufacturer to provide acceptable serviceability of the device,
taking responsibility for the effects of changes in operating conditions due to variations in the charac-
teristics of the electronic device under consideration.
The equipment manufacturer should design so that, initially and throughout life, no design maximum
value for the intended service is exceeded with a bogey device under the worst probable operating
conditions with respect to supply voltage variation, equipment component variation, variation in
characteristics of all other devices in the equipment, equipment control adjustment, load variation,
signal variation and environmental conditions.
DESIGN CENTRE RATING SYSTEM
Design centre ratings are limiting values of operating and environmental conditions applicable to a
bogey electronic device of a specified type as defined by its published data, and should not be exceed-
ed under normal conditions.
These values are chosen by the device manufacturer to provide acceptable serviceability of the device
in average applications, taking responsibility for normal changes in operating conditions due to rated
supply voltage variation, equipment component variation, equipment control adjustment, load variation,
signal variation, environmental conditions, and variations in the characteristics of all electronic devices.
The equipment manufacturer should design so that, initially, no design centre value for the intended
service is exceeded with a bogey electronic device in equipment operating at the stated normal supply
voltage.
12 October 1977
PACKAGE OUTLINES
PACKAGEOUTLINES
In this chapter the package outlines are given for the following types, except for those marked with an
asterisk which are included in the device data sheet.
type number package code description
CA3046SAA1027SAA1029SAK150BTTBA673*
TBA915GTCA210TCA210TTCA220TCA240
TCA240DTCA280ATCA520BTCA520DTCA770A
TCA770DTCA980GTDA1023TDA1024TDA1060
TDA1060ATDA1060BTDA1540DTDA3081TDA3083
TDA3083DTDB1080TEA1010TEA1010TTEA1016
TEA1017TEA1021PTEA1021DTEA1039TEA1042
TEA1043PTEA1043DTEA1044PTEA1044DTEA1046P
SOT-27TSOT-38ASOT-38
SO-14;SOT-108ASOT 14
SOT-1 10B
SOT-38
SO-14; SOT-1 08ASOT-38SOT-38
SO-16;SOT-109ASOT-38SOT-97ASO-8; SOT-96ASOT-38
SO-14;SOT-108ASOT-110BSOT-38SOT-97ASOT-38
SOT-38SOT-74SOT-135ASOT-38ZSOT-38Z
SO-16;SOT-109ASOT-38SSOT-97C2SO-8; SOT -96AC1SOT-38
SOT-102HESOT-38SOT-74B
SOT-110BSOT-101A
SOT-38
SOT-74BSOT-102ASOT-133
SOT-101A
14-lead dual in-line; plastic (SOT-27K, M, T)
16-lead dual in-line; plastic (SOT-38A)
16-lead dual in-line; plastic (SOT-38)
14-lead mini-pack; plastic (SO-14; SOT-108A)
10-lead cylindrical; metal (TO-74; reduced
height; SOT-14)
9-lead single in-line; plastic (SOT-1 10B)
16-lead dual in-line; plastic (SOT-38)
14-lead mini-pack; plastic (SO-14; SOT-108A)
16-lead dual in-line; plastic (SOT-38)
16-lead dual in-line; plastic (SOT-38)
16-lead mini-pack; plastic (SO-16;SOT-109A)
16-lead dual in-line; plastic (SOT-38)
8-lead dual in-line; plastic (SOT-97A)
8-lead mini-pack; plastic (SO-8; SOT-96A)
16-lead dual in-line; plastic (SOT-38)
14-lead mini-pack; plastic (SO-14; SOT-108A)
9-lead single in-line; plastic (SOT-1 10B)
16-lead dual in-line; plastic (SOT-38)
8-lead dual in-line; plastic (SOT-97A)
16-lead dual in-line; plastic (SOT-38)
16-lead dual in-line; plastic (SOT-38)
16-lead dual in-line; ceramic (cerdip) (SOT-74)
28-lead dual in-line; ceramic (cerdip) (SOT-135A)
16-lead dual in-line; plastic (SOT.-38Z)
16-lead dual in-line; plastic (SOT-38Z)
16-lead mini-pack; plastic (SO-16; SOT-109A)
16-lead dual in-line; plastic (SOT-38, S)
8-lead dual in-line; plastic (SOT-97A, C2)
8-lead mini-pack; plastic (SO-8; SOT-96A, AC1
)
16-lead dual in-line; plastic (SOT-38)
18-lead dual in-line; plastic (SOT-102HE)
16-lead dual in-line; plastic (SOT-38)
16-lead dual in-line; ceramic (cerdip) (SOT-74, B)
9-lead single in-line; plastic (SOT-1 10B)
24-lead dual in-line; plastic (SOT-101A)
16-lead dual in-line; plastic (SOT-38)
16-lead dual in-line; ceramic (cerdip) (SOT-74, B)
18-lead dual in-line; plastic (SOT-102A)
18-lead dual in-line; ceramic (cerdip) (SOT-133)
24-lead dual in-line; plastic (SOT-101A)
14 March 1983^r
PACKAGEOUTLINES
type number package code description
TEA1046DTEA1053TEA1054TEA1055TEA1058
TEA1058TTEA1060TEA1061TEA1062TEA1063
SOT-149
SOT-102ASOT-102ASOT-102ASOT-97C2
SO-8;SOT-96AC1SOT102ASOT-102ASOT-38
SOT-38
24-lead dual in-line; ceramic (cerdip) (SOT-149)
18 lead dual in-line; plastic (SOT-102A)
18-lead dual in-line; plastic (SOT-102A)
18-lead dual in-line; plastic (SOT-102A)
8-lead dual in-line; plastic (SOT-97A, C2)
8-lead mini-pack; plastic (SO-8; SOT-96A, AC1)
18-lead dual in-line; plastic (SOT-102A)
18-lead dual in-line; plastic (SOT-102A)
16-lead dual in-line; plastic (SOT-38)
16-lead dual in-line; plastic (SOT-38)
~\rMarch 1983 15
14-LEAD DUAL IN-LINE; PLASTIC (SOT-27K,M,T)
J VPACKAGEOUTLINES
8,25 max
L^n^q^Ji^nFTfrtop view
Positional accuracy.
(m) Maximum Material Condition.
Centre-lines of all leads are
within ±0,1 27 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
+0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
Dimensions in mm
SOLDERING
1. By hand
Apply the soldering iron below the seating plane (or not more than 2 mm above it).
If its temperature is below 300 °C it must not be in contact for more than 10 seconds; if between300 °C and 400 °C, for not more than 5 seconds.
2. By dip or wave
The maximum permissible temperature of the solder is 260 °C; this temperature must not be in
contact with the joint for more than 5 seconds. The total contact time of successive solder wavesmust not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body mustnot exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forcedcooling may be necessary immediately after soldering to keep the temperature within the permis-sible limit.
3. Repairing soldered joints
The same precautions and limits apply as in (1 ) above.
~\rMarch 1983 17
PACKAGEOUTLINES
16-LEAD DUAL IN-LINE; PLASTIC (SOT-38.S)
22 max - -« 8,25 ma
3,9
3,4
+
- Vv W V7 _
2,2;
max
, 14x
ink
0,53max
4,7max
* 0,51I
mi n t
0.7612 '
•*-(»|
0,2 5 /i"@|(
1,4 max
j-iAAiJiAAj^u^16 15 14
3
13
U
12
5
11
6
10
7
9
8
-> -
1 2
UJy^LJ^L^yUtop view
tj7 Positional accuracy.
© Maximum Material Condition.
(1) Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
Dimensions in mm
SOLDERING
1. By hand
Apply the soldering iron below the seating plane (or not more than 2 mm above it).
If its temperature is below 300 °C it must not be in contact for more than 10 seconds; if between
300 °C and 400 °C, for not more than 5 seconds.
2. By dip or wave
The maximum permissible temperature of the solder is 260 °C; this temperature must not be in
contact with the joint for more than 5 seconds. The total contact time of successive solder waves
must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must
not exceed the specified storage maximum. If the printed-circuit board has been preheated, forced
cooling may be necessary immediately after soldering to keep the temperature within the permis-
sible limit.
3. Repairing soldered joints
The same precautions and limits apply as in (1 ) above.
18 March 1983~\r
16-LEAD DUAL IN-LINE; PLASTIC (SOT-38A)
;vPACKAGEOUTLINES
j^lj±uMli^AA16 15 14 13 12 11 10 9
1 2 3 4 5 6 7
^n;rtjnjnprTp=
T^TjT"top view
Dimensions in mm
^ft- Positional accuracy.
(ivj) Maximum Material Condition.
(1) Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
SOLDERING
1. By hand
Apply the soldering iron below the seating plane (or not more than 2 mm above it).
If its temperature is below 300 °C it must not be in contact for more than 10 seconds; if between
300 °C and 400 °C, for not more than 5 seconds.
2. By dip or wave
The maximum permissible temperature of the solder is 260 °C; this temperature must not be in
contact with the joint for more than 5 seconds. The total contact time of successive solder waves
must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must
not exceed the specified storage maximum. If the printed-circuit board has been preheated, forced
cooling may be necessary immediately after soldering to keep the temperature within the permis-
sible limit.
3. Repairing soldered joints
The same precautions and limits apply as in (1 ) above.
^rMarch 1983 19
PACKAGEOUTLINES
16-LEAD DUAL IN-LINE; PLASTIC (SOT-38Z)
t
3,43
3,05
19,5 max -
W---V/
t4>
A^0,53max
0,51
min |
*-|-0-|o,254@| '
0,76max
.0,32max
-\]M !10
8,3
AonnnnnA
j/zrxjTjjjTjxjxjxflead 1 indication (either index or sign)
Dimensions in mm
top view
{j} Positional accuracy.
(m) Maximum Material Condition.
(1) Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
SOLDERING
1. By hand
Apply the soldering iron below the seating plane (or not more than 2 mm above it).
If its temperature is below 300 °C it must not be in contact for more than 10 seconds; if between
300 °C and 400 °C, for not more than 5 seconds.
2. By dip or wave
The maximum permissible temperature of the solder is 260 °C; this temperature must not be in
contact with the joint for more than 5 seconds. The total contact time of successive solder waves
must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must
not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced
cooling may be necessary immediately after soldering to keep the temperature within the permis-
sible limit.
3. Repairing soldered joints
The same precautions and limits apply as in ( 1 ) above.
20 March 1983
PACKAGEOUTLINES
16-LEAD DUAL IN-LINE; CERAMIC (CERDIP)(SOT-74,B)
-*-] 1,5 I-*-
h r"i r"i r"i r"i H r"i fl
top view
^) Positional accuracy.
(m) Maximum Material Condition.
(1
)
Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
Dimensions in mm
~^rMarch 1 983 21
PACKAGEOUTLINES
8-LEAD MINI-PACK; PLASTIC (SO-8; SOT-96A.AC1)
0,7
5,0"4,8
l
6°
^0,7 max
0,49
0,36
41,45
1.25
t
"*• 1,27 '—
t
1,75
1,35
*f»j 0.25 @]
top view
Dimensions in mm
^- Positional accuracy.
@ Maximum Material Condition.
22
SOLDERING
The reflow solder technique
The preferred technique for mounting miniature components on hybrid thick or thin-film circuits is
reflow soldering. Solder is applied to the required areas on the substrate by dipping in a solder bath or,
more usually, by screen printing a solder paste. Components are put in place and the solder is reflowed
by heating.
Solder pastes consist of very finely powdered solder and flux suspended in an organic liquid binder.
They are available in various forms depending on the specification of the solder and the type of binder
used. For hybrid circuit use, a tin-lead solder with 2 to 4% silver is recommended. The working tern
perature of this paste is about 220 to 230 °C when a mild flux is used.
For printing the paste onto the substrate a stainless steel screen with a mesh of 80 to 105 jum is used
for which the emulsion thickness should be about 50 |iim. To ensure that sufficient solder paste is
applied to the substrate, the screen aperture should be slightly larger than the corresponding contact
area.
The contact pins are positioned on the substrate, the slight adhesive force of the solder paste being
sufficient to keep them in place. The substrate is heated to the solder working temperature preferably
by means of a controlled hot plate. The soldering process should be kept as short as possible: 10 to
15 seconds is sufficient to ensure good solder joints and evaporation of the binder fluid.
After soldering, the substrate must be cleaned of any remaining flux.
March 1983r
8-LEAD DUAL IN-LINE; PLASTIC (SOT-97A.C2)
J VPACKAGEOUTLINES
- 10 max -8,25 max
jl f lj|
'3-il|l^^^^ ' 1 '
1,73 max
A^ulA>
top view
vwvDimensions in mm
X^j- Positional accuracy.
(m) Maximum Material Condition.
(1) Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
SOLDERING
1. By hand
Apply the soldering iron below the seating plane (or not more than 2 mm above it).
If its temperature is below 300 °C it must not be in contact for more than 10 seconds; if between300 °C and 400 °C, for not more than 5 seconds.
2. By dip or wave
The maximum permissible temperature of the solder is 260 °C; this temperature must not be in
contact with the joint for more than 5 seconds. The total contact time of successive solder wavesmust not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body mustnot exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced
cooling may be necessary immediately after soldering to keep the temperature within the permis-
sible limit.
3. Repairing soldered joints
The same precautions and limits apply as in (1 ) above.
^rMarch 1983 23
PACKAGEOUTLINES
24-LEAD DUAL IN-LINE; PLASTIC (SOT-101A)
3,9
3,4
4
uu.y.i/Aiiiuy —t 0.51
5.1
max
0,76 l21
22
[H3
t
»H<Ho.;5i(m)1
'"
^/L/YAA/V'LrVwirv24 23 22 21 20 19 18 17 16 15 14 13
>
12 3 4 5 6 7 9 10 11 12
top view
^ Positional accuracy.
© Maximum Material Condition.
(1) Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
(3) Index may be horizontal as shown,
or vertical.
Dimensions in mm
SOLDERING
See page 1 7 of this chapter (SOT-27K, M, T).
24 March 1983^\r
18-LEAD DUAL IN-LINE; PLASTIC (SOT-102A)
J VPACKAGEOUTLINES
23,5 max
t3,9
3,4
\
\J-u-xJ--xJ-.xJ-XJ-
liJ y LJ l|j
1,75 L_max
16x
2,54
0,53max
Hi hj
4,7I
max- 0,51 I
min f
0,76 l:
-*-|-»|o,?5zn
^^^^^u^top view
XnjVVVTJTAAT
side view
<J}^ Positional accuracy.
© Maximum Material Condition.
(1) Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
(3) Index may be horizontal as shown,or vertical.
Dimensions in mm
SOLDERING
See page 17 of this chapter (SOT-27K, M,T).
^rMarch 1983 25
PACKAGEOUTLINES
18-LEAD DUAL IN-LINE; PLASTIC (SOT-102HE)
22 max
3,93,4
f
li
0,85 _^max
-XJ--KJ AJ w -XJ-
16x
0,53
max
4,7max
0,9
\ / \[ |
.
mm |
0,76l2)
-^<j>|o,254~(M)1 nl
18 T7 16 15 14 13 12 11 To[ to P view
8 9
Tn^^T^T^^^TX^T
8,25 max
^J^ Positional accuracy.
© Maximum Material Condition.
(1) Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
Dimensions in mm
SOLDERING
See page 17 of this chapter (SOT-27K, M,T).
26 March 1983~\r
J V14-LEAD MINI-PACK; PLASTIC (SO-14; SOT-108A)
PACKAGEOUTLINES
l[i^7]l*
7 6 5 4 3 2 1
8 9 10 11 12 13 14
Dimensions in mm
(J)-Positional accuracy.
© Maximum Material Condition.
SOLDERING
The reflow solder technique
The preferred technique for mounting miniature components on hybrid thick or thin-film circuits is
reflow soldering. Solder is applied to the required areas on the substrate by dipping in a solder bath or,
more usually, by screen printing a solder paste. Components are put in place and the solder is reflowed
by heating.
Solder pastes consist of very finely powdered solder and flux suspended in an organic liquid binder.
They are available in various forms depending on the specification of the solder and the type of binder
used. For hybrid circuit use, a tin-lead solder with 2 to 4% silver is recommended. The working tem-
perature of this paste is about 220 to 230 °C when a mild flux is used.
For printing the paste onto the substrate a stainless steel screen with a mesh of 80 to 105 /im is used
for which the emulsion thickness should be about 50 jim. To ensure that sufficient solder paste is
applied to the substrate, the screen aperture should be slightly larger than the corresponding contact
area.
The contact pins are positioned on the substrate, the slight adhesive force of the solder paste being
sufficient to keep them in place. The substrate is heated to the solder working temperature preferably
by means of a controlled hot plate. The soldering process should be kept as short as possible: 10 to
1 5 seconds is sufficient to ensure good solder joints and evaporation of the binder fluid.
After soldering, the substrate must be cleaned of any remaining flux.
~\rMarch 1983 27
PACKAGEOUTLINES
16-LEAD MINI-PACK; PLASTIC (SO-16; SOT-109A)
0,70,6
10,0
9,8
149 I0,490,36
- E27]>~
1,45 ,5 5
-[^fo, ?5~"©j
c: :::::: F
9 10 11 12 13 1fc 15 16m Q u f fit
Dimensions in mm
t]7 Positional accuracy.
© Maximum Material Condition.
SOLDERING
The reflow solder technique
The preferred technique for mounting miniature components on hybrid thick or thin-film circuits is
reflow soldering. Solder is applied to the required areas on the substrate by dipping in a solder bath or,more usually, by screen printing a solder paste. Components are put in place and the solder is reflowedby heating.
Solder pastes consist of very finely powdered solder and flux suspended in an organic liquid binder.They are available in various forms depending on the specification of the solder and the type of binderused. For hybrid circuit use, a tin-lead solder with 2 to 4% silver is recommended. The working tem-perature of this paste is about 220 to 230 °C when a mild flux is used.
For printing the paste onto the substrate a stainless steel screen with a mesh of 80 to 105 Mm is usedfor which the emulsion thickness should be about 50 pm. To ensure that sufficient solder paste is
applied to the substrate, the screen aperture should be slightly larger than the corresponding contactarea.
The contact pins are positioned on the substrate, the slight adhesive force of the solder paste beingsufficient to keep them in place. The substrate is heated to the solder working temperature preferablyby means of a controlled hot plate. The soldering process should be kept as short as possible: 10 to15 seconds is sufficient to ensure good solder joints and evaporation of the binder fluid.After soldering, the substrate must be cleaned of any remaining flux.
28 March 1983^r
9-LEAD SINGLE IN-LINE; PLASTIC (SOT-110B)
7VPACKAGEOUTLINES
-»• 1,65 »-
}-£
| top view
Dimensions in mm
tjj) Positional accuracy.
© Maximum Material Condition.
A Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±0,254 mm.
B Lead spacing tolerances apply
from seating plane to the line
indicated.
March 1983 29
PACKAGEOUTLINES
18-LEAD DUAL IN-LINE; CERAMIC (CERDIP) (SOT-133)
23,6 max
~**l1-5 I*
h^^^i^^n^n
LTTOVWTO^
top view
{+) Positional accuracy.
(m) Maximum Material Condition.
(1) Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
±0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
Dimensions in mm
30 March 1983^r
PACKAGEOUTLINES
28-LEAD DUAL IN-LINE; CERAMIC (CERDIP) (SOT-135A)
I
2,54 !^_max
flflflfl aflQaflflaaaa28 27 26 25 24 23 22 21 20 19 18 17 16 15
-;
gggg^yyyyyyyyy-
— 1 5,9 max —•.
- GM3
-q3" Positional accuracy.
® Maximum Material Condition.
(1) Centre-lines of all leads are
within ±0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by±0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
Dimensions in mm
^rMarch 1983 31
PACKAGEOUTLINES
24-LEAD DUAL IN-LINE; CERAMIC (CERDIP) (SOT-149)
*
3,432,92
2,0 ,.».
unu ^
5,3
max
— mm j
-t 0,76"
H^|0,25®|'"
QQQQflflflflaflflfl24 23 22 21 20 19 18 17 16 15 14 13
)
1 2 3 4 5 6 7 8 9 10 11 12i^yyygyyygyyg top view
- 11,3 ma(+) Positional accuracy.
(m) Maximum Material Condition.
(1) Centre-lines of all leads are
within +0,127 mm of the nominal
position shown; in the worst case,
the spacing between any two leads
may deviate from nominal by
+0,254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
Dimensions in mm
32 March 1983^\r
OPERATIONAL AMPLIFIERS
TCA220
TRIPLE OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
The TCA220 is a bipolar integrated circuit consisting of three identical high-gain amplifiers. The
amplifiers have differential inputs and an emitter-follower output which can deliver up to 100 mAoutput current. The unity-gain frequency with 6 dB/octave compensation is at least 5 MHz. No latch-up
will occur when the input voltage range is exceeded.
QUICK REFERENCE DATA
Supply voltages
positive
negative
Supply current, unloaded
Large-signal voltage amplification
Slew rate
Input voltage range
Input offset voltage
Input offset current
Common-mode rejection ratio
Supply voltage rejection ratio
Operating ambient temperature range
vCc nom. 6 V
-v E e nom. 6 V
'CC + 'RX typ. 1,4 mA
AVD typ. 4000
sVOAV typ. 0,4 V/ms
V| -4,3 to + 5,6 V
V|0 typ. 2 mV
'10 typ. 0,2 MkCMR typ. 90 dB
kSVR typ. 75 dB
Tamb -55 to + 125 °C
PACKAGE OUTLINES
16-lead DIL; plastic (SOT-38).
^rFebruary 1983 35
TCA220
36 February 1983~~\r
Triple operational amplifier TCA220
„-[T uTeT] vEE ,
11+ [T H] FC1
rx QT m"| Q1
I2+ [jT
TCA220~kT| Q2
77] FC2
vcc [T TT| 03
13+ [T To] FC3
13- [IT T] VEE2
Fig. 2 Pinning diagram.
PINNING
1 11-
2 11 +
3 RX
4 12 +
5 12-
6 vCc7 13 +
8 13-
9 V E E2
10 FC3
11 Q3
12 FC2
13 Q2
14 Q1
15 FC1
16 VEE1
inverting input, amplifier 1
non-inverting input, amplifier 2
external resistor
non-inverting input, amplifier 2
inverting input, amplifier 2
positive supply
non-inverting input, amplifier 3
inverting input, amplifier 3
negative supply,
amplifier 3
frequency compensation,
amplifier 3
output, amplifier 3
frequency compensation,
amplifier 2
output, amplifier 2
output, amplifier 1
frequency compensation,
amplifier 1
negative supply, amplifiers 1
and 2
FUNCTIONAL DESCRIPTION
Supply
The TCA220 requires a positive and a negative supply. Vrjc is the common positive supply to the three
amplifiers. VEE iis the common negative supply to amplifiers 1 and 2, which always has to be connect-
ed to the negative supply. V EE2 is a separate negative supply for amplifier 3, which should be left open
when this amplifier is not used.
External resistor; RX
The current level in the amplifiers is determined by current sources. These current sources need a
minimum current into RX of 200 ^A. This current is usually derived from the positive supply via
an external resistor.
Frequency compensation; FC1, FC2 and FC3
Each amplifier may be frequency compensated by connecting an RC network from its FC to its V EE(see Fig. 4).
Outputs Q1.Q2 and Q3
The outputs are emitter followers with open-emitter outputs which require an external load resistor.
*\r.February 1983 37
TCA220
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage, d.c.VCC -VEE
Input voltage range vl
Differential-mode input d.c. voltage ± V ID
Input current 'l
Current into RX 'RX
Output current— 'Q
Storage temperature range
Operating ambient temperature range (see also Fig. 3)
stg
amb
max. 18 V
VEE toV CC v
max. 5 V
max. 0,5 tnA
max. 5 mAmax. 100 mA-55 to +125 °C
-55 to +125 °C
T[.%717 ?.1
750 —Ptot
ImW)
— —
500
—
250
-100 -50 50 Tamb(°C) 100
Fig. 3 Power derating curve.
38 February 1983
Triple operational amplifier TCA220
CHARACTERISTICS
VCC = 6 v ;
~VEE = 6 V; Tamb = 25 °C unless otherwise specified
parameter
Supply
Supply voltage range
Supply current, Vq = OV; unloaded
Supply-voltage rejection ratio*
at R s = 2kft
External resistor; RX
Voltage with respect to negative supply
Current into RX
Inputs I + and I-
Input voltage range
Input bias current
Differential input impedance
Input offset voltage at Fig = 200 ft max.
Input offset current
Common-mode rejection ratio
at Rs = 2 kfi;f = 1 kHz
Outputs Q1, Q2and Q3
Output voltage range
Large-signal differential-mode voltage
amplification at VQ(p .p )
= 7 V
variation with temperature at
Tamb = -20to + 70°C
Slew rate at unity gain
Gain-bandwidth product at 6 dB/octavecompensation
Broadband noise figure at Rg = 2 kS2;
f = 10 Hz to 10 kHz
Channel separation at Rg = 2 kft;
f = 10 kHz (see Fig. 5)
from amplifier 1 to amplifier 2
from amplifier 1 to amplifier 3
from amplifier 2 to amplifier 1
from amplifier 2 to amplifier 3
from amplifier 3 to amplifier 1
from amplifier 3 to amplifier 2
symbol
Vcc-vEE
'cc
kSVR
V RX-EE
'RX
V|
'IB
l*idl
V|0
'IO
kCMR
Vq
AVD
AAV DsVOAV
fl
FAV
min. typ.
200
-4,3
25
12
1,2
75
1,5
2
0,2
90
2000 4000
8
0,4
94
130
94
110
130
110
max.
16
3
+ 5,6
2
10
+ 3,5
unit
V
mA
dB
V
mA
V
MA
kn
mV
MA
dB
dB
V/Ms
MHz
dB
dB
dB
dB
dB
dB
dB
The supply-voltage rejection ratio is the ratio of the change in input offset voltage to the change insupply voltages producing it.
~\fFebruary 1983 39
TCA220
Fig. 4 Test circuit for channel separation. Channel separation from amplifier A to amplifier B is defined
as:
VQA20 log xAclB .
VQB
Ac ib being the closed-loop gain of amplifier B; in this case Ac ib = 100.
APPLICATION INFORMATION
Fig. 5 Frequency compensation circuit.
40 February 1983^r
TCA520BTCA520D
OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
TheTCA520 is a bipolar integrated operational amplifier primarily intended for low-power, low-voltageapplications and as a comparator in digital systems.
Features
• wide supply voltage range
• low supply voltage operation
• low power consumption
• low input bias current
• offset compensation facility
• frequency compensation facility
• high slew rate
• large output voltage swing
• TTL compatible output
QUICK REFERENCE DATA
Supply voltage range vCc 2 to 20 VSupply current
!CC typ. 0,8 mAInput bias current
>IB typ. 60 nAOutput voltage range VQ 0,1 to Vcc-0,1 VD.C. differential voltage amplification AVD typ. 15 000Slew rate sVOAV typ. 25 V/msOperating ambient temperature range Tamb -25 to + 85 °C
PACKAGE OUTLINES
TCA520B : 8-lead DIL; plastic (SOT-97A).TCA520D: 8-lead mini-pack; plastic (SO-8; SOT-96A).
^rJanuary 1983 41
TCA520BTCA520D
FC Vc
I +— |TR2 TR5J—i—
I— TR1 TR4x:
TR7
r— TR9
.-3
TR6J—
l~tjR8
TR3
R1
I
R2 R3 Rh
I I-I
1
0F1
R5
I
<D1
TR11
0F2 VEE
Fig. 1 Circuit diagram.
0F1 1 8
I- 2TCA520B
7
l + 3TCA520D
6
VEE 4 5
0F2
VCC
Q
FC
7Z86760
Fig. 2 Pinning diagram.
PINNING
1 0F1 offset compensation connection
2 I— inverting input
3 l+ non-inverting input
4 Vf££ ground connection
5 FC frequency compensation connection
6 Q output
7 Vrjc positive supply connection
8 OF2 offset compensation connection
42 January 1983~\f
Operational amplifier TCA520BTCA520D
RATINGS
Limiting values in accordance with the
Supply voltage, d.c.
Input voltage
Differential input voltage
Power dissipation at Tamb= 85 °C
Storage temperature range
Operating ambient temperature range
CHARACTERISTICS
VCC = 5 V; VEE = V; Tamb = 25 °C;
Absolute Maximum System (IEC 134)
VCCV|
-V,
±V| Dptot
Tstg
Tamb
max.
max.
22 V
VCC VV
max.
max.
7 V
200 mW55to + 125 °C
-25 to + 85 °C
R|_ from Q to Vqq unless otherwise specified
parameter symbol min. typ. max. unit
Supply Vcc.'Pin ^
Supply current, unloaded 'cc 0,5 0,8 1,2 mA
Inputs 1+ and I-; pins 3 and 2
Input voltage V| 0,9 - Vcc-0,5 VInput bias current
'IB- 60 250 nA
Input offset voltage V|0 -1 6 mV
Variation with temperature AV| - 5 — MV/KInput offset current l|0 - 10 75 nACommon-mode rejection ratio kCMR 70 100 — dBInput noise voltage at f = 1 kHz Vn(rms) - 15 - nVVHzInput noise current at f = 1 kHz 'n(rms)
- 0,4 - pAA/ Hz
Output Q; pin 6
Output voltage range at R L = 5 kJ2 Vq 0,1 -Vcc-0,1 V
Output current
HIGH at Vq = Vcc - 0,4 V -'oh 100 200 _ MALOW at Vq = 0,4 V 'OL 6 12 _ mA
D.C. voltage amplification
at R L = 5kfi AVD 10 000 15 000 —A.C. voltage amplification
at f = 1 kHz;CFC = 100 pF Avd - 58 — dBSlew rate (average rate of change of
the output voltage) at R L = 1 \<Sl
CFC = 0pF sVOAV - 25 - V/jus
CFC = 100pF sVOAV - 500 - mV/p
~\rJanuary 1983 43
TCA520BTCA520D
7Z67242.2
cFC" 00 p 10 pF )
10
1 j | ji
Fig. 3 Typical values of the open-loop voltage amplification as a function of frequency.
(dB)
90
—10 kit.
1 <SJ^
Fig. 4 Typical values of the open-loop voltage amplification as a function of supply voltage.
44 January 1983~\r
Operational amplifier TCA520BTCA520D
10" 7Z67 441.1
-LiT
ztI
10 3
C FC svo25 V
"i
—
I-
ii ' I
10 21 P
I
15 V!
//JS
~fr
—
4 :^ _j .
1
i
J
|| \
10lOpF
:tL:r-:.:J5 V T— - ^ i
-I --V- -'- -- '"T t
-"- \\ —j
JT ~f
i
1 __i tr\
it31 — T|
\i
1
100
\\W—
I
PF 0,5 V /^s
1V"^+^ -L-
\ i— -
i i i
1 "T
t
\ \
TJ ._.
! 1 1 I
1-1 j10 J 10' 10 = 10°
f (Hz)
Fig. 5 Typical frequency response and slew rate for various closed-loop gains.
7Z67444 2 A „ 7Z67443.2
'OL
OtiA)
10 7
-
f
I
~^'1 T
VCC = 20V
1
10V
\r
_5\/ 1—"""
2V
Fig. 6 Typical values of the input bias current
as a function of supply voltage, with ambient
temperature as a parameter.
Fig. 7 Output current LOW as a function of
output voltage, with supply voltage as a
parameter.
A/"January 1983 45
TCA520BTCA520D yv
'OH
ImAIVCC~
~^
|\
^10
~~~ >5V/
1sv
Vo(p-p)
(VI
miny
Fig. 8 Output current HIGH as a function of
output voltage, with supply voltage as a
parameter.
Fig. 9 Minimum values of the output
voltage swing as a function of supply
voltage for R|_ = 1 kfi.
£TCA520BTCA520D
1
TCA520BTCA520D
Fig. 10 Typical arrangement of the TCA520with frequency and offset compensation.
Fig. 11 Typical application of the TCA520
as a comparator.
46 January 1983-\r
DEVELOPMENT SAMPLE DATAThis information is derived from development samples
made available for evaluation. It does not necessarily
imply that the device will go into regular production.
TEA1016
DUAL OP-AMP AND COMPARATOR
GENERAL DESCRIPTION
The TEA1016 is a bipolar integrated circuit containing two operational amplifiers and a high-speed
comparator. The circuit requires a single 5 V supply, this makes it especially suited for digital applica-
tions. The comparator has a level-shifted output for driving an external switching transistor. With this
transistor the circuit is TTL compatible; the transistor may also drive a transmission line.
QUICK REFERENCE DATA
Supply voltage range
Supply current
Open-loop differential voltage amplification
amplifiers
comparator
Input offset voltage
Input offset current
amplifiers
comparator
Comparator total response time
Operating ambient temperature range
VCC1; VCC2 4,75 to 5,25 V
'CCI + 'CC2 tVP- 28 mA
Avd
Avd
V|0
typ. 43,5 dB
min. 47 dB
max. 5 mV
1 10 max - 5 ,uA
1 10 rnax. 6 /.'.A
ttotlr). ttot(f) max-
60 nS
-40 to +105 °CTamb
PACKAGE OUTLINE
16-lead DIL; plastic (SOT-38).
~\rFebruary 1983 47
TEA1016
VCC1 °' VCC2
vEEl°rv EE2
(a)
«CC1
1
6
VCC2
5
1
7
>9
8 10
1
1
3+ +
>1
4 2
1
1
13 COMP+ n/# +
— +
15
14 16
D-
1
16-C TEA10
" 12 7Z8S7SO
VEE1 V EE2
Fig. 2 Block diagram.
(b)
Fig. 1 Circuit diagram.
(a) one amplifier.
(b) comparator.
48 February 1983
<<
<GO
Dual op-amp and comparator
Q2+ ("JTu
7tT[ Q4
Q2- [1~_ Tjf] Q3
12+ [T U]l3-
12- [T^
'CC2 f_T
TEA1016Ul 13+
^0 VEE2
•'cci []£_TT]vEE1
11+|~7~
To] Q1-
n-(T j[] cn +
Fig. 3 Pinning diagram.
PINNING
1 Q2 +
2 Q2-
3 12 +
4 12-
5 VCC2
6 VCC17 11 +
8 11-
9 Q1 +
10 Q1-
11 V E E1
12 VEE2
13 13 +
14 13-
15 Q3
16 Q4
TEA1016
non-inverting output, amplifier 2
inverting output, amplifier 2
non-inverting input, amplifier 2
inverting input, amplifier 2
positive supply, amplifier 2 andcomparator
positive supply, amplifier 1
non-inverting input, amplifier 1
inverting input, amplifier 1
non-inverting output, amplifier 1
inverting output, amplifier 1
ground, amplifier 1
ground, amplifier 2 and
comparator
non-inverting input, comparator
inverting input, comparator
direct comparator output
level-shifted comparator output
>Q
FUNCTIONAL DESCRIPTION
Supply
The TEA1016 requires a single 5 V supply. The first operational amplifier has separate supply andground pins. If only one operational amplifier is to be used, than VCC1 may be left open.
Amplifier outputs Q1 +, Q1-, Q2+ and 0.2-
The amplifiers have complementary outputs. The outputs are emitter followers with current sources toground.
Comparator outputs Q3 and Q4
The comparator has a single emitter follower output stage with a resistor to ground. Q3 is the emitteroutput, Q4 is a tap on the resistor which provides a level shift. This output is intended to drive anexternal transistor directly. This transistor will produce a TTL compatible signal; it may even drive atransmission line.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage, d.c. VCC1 ,VCC2 maxInput voltage, all inputs V| maxOutput current, all outputs _l„ maxTotal power dissipation p^ ^ __ vr tot max.
Storage temperature range
Operating ambient temperature range
'stg
Tamb
6 V
VCC v
10 mA250 mW
-40 to + 1 25 °C
-40 to +105 °C
~^\rFebruary 1983 49
TEA1016
CHARACTERISTICS
VCCI = VCC2 = 4,75 to 5,25 V; VEE1 = VEE2 = V; Tamb =
specified
-40 to + 105 °C unless otherwise
parameter symbol min. typ. max. unit
Supply: Vqqi and Vfjc2' Pms ^ anc' 6
Supply current l CC1 + l CC2 15 28 40 mA
Amplifier inputs 11+, 11-, 12+ and I2-;
pins 7, 8, 3 and 4
Input voltage V| 1,5 _. 3,7 V
Input bias current >IB 10 80 MA
Input impedance at f = 1 kHzl
zisl
3 - 30 kS2
Input offset voltage V|0 -5 5 mV
Input offset current iio -5 5 liA
Amplifier outputs Q1+, Q1-, Q2+ and Q2-;
pins 9, 10, 1 and 2
Open-loop differential voltage amplification Avd 39 43,5 48 dB
Output voltage at Tam b= 25 °C
HIGH V H 2,2 2,8 3,6 V
LOW vol 0,9 1,6 2,4 V
Output voltage swing v O(p-p) 0,35 - 1,5 V
at Tamb = 25 °C V 0(p-p) 0,7 0,95 1,3 V
Comparator inputs 13+ and 13—; pins 13 and 14
Input voltage V| 1,5 - 3,5 V
Input bias current I IB 10 40 jjA
Input offset voltage VlO -5 5 mV
Input offset current iio -6 6 HA
Comparator outputs Q3 and Q4; pins 15 and 16
Open-loop differential voltage amplification to Q3 Avd 47 - - dB
Output voltage Q4HIGH V H 0,95 - 1,7 V
LOW vol - - 250 mV
Output voltage ratio VQ4/VQ3 0,53 - 0,6
Output short-circuit current, Q4at V| 3+ = 3 V; V| 3^ = 2 V; VQ4 = V ! OS 3 6,5 12 mA
Comparator total response time
rising edge ttot(r)- 30 60 ns
falling edge ttotff)— 30 60 ns
50 February 1983^r
Dual op-amp and comparator TEA1016
1"90%
\-Vio%^ I
(-0.3V
0V
-0,3 V
Fig. 4 Timing diagram of the comparator showing the total response times.
<t-<
s<
I-z
>LU
Q
7Z86776
. i.O- - ^ ^OH_Vcc = 5,25 V
3 h — 1- - - -
. 5,0 V
r i
t
|. L. .
4.75 V
i
IV) .-Uty i - output
2—t —— swing
h J Vni
|~~ VCC ="
t 5,25V.
— U~
|
—— —7"
_—Jt—
-^— 4,75V
i-i -.
^~_~
—1 _
Tamb CO
Fig. 5 Amplifier HIGH and LOW output voltage as a function of ambient temperature with the supply
voltage Vrjc as a parameter.
^r.February 1983 51
TEA1016
52
VQ3(V)
^^j V0HvCc
=
5.25 V
— 5.0 V
4,75 V
V0L
-40 -20 20 40 60 80 100 120
Tamb I°C1
Fig. 6 Comparator output level at direct output Q3 as a function of ambient temperature with the
supply voltage Vrjc as a parameter.
46
AvdIdBI
44
" vcc-^— 5,25V
_-_^
OV
j
i
-40 -20 20 40 60 80 100 120
Tamb l°CI
Fig. 7 Amplifier open-loop differential voltage amplification as a function of ambient temperature
with the supply voltage Vqq as a parameter.
7Z8S775
12 cc
75V4
10
\— 5,0 V-
5,25 V
Tamb |0ci
Fig. 8 Amplifier input impedance as a function of ambient temperature with the supply voltage Vrjcas a parameter.
February 1983^r
Dual op-amp and comparator TEA1016
<Q
<CO
a.
O
>WQ
2g<scc
o
2o
5 o n^- *j X— '".-»
^ ro OS i: CO
S. =• "
"° s z«S|J3 •= ™
S "°CD f tN
5 o 'I
< o E
Si*"c ~ II
f">
M C II
ra '.- O.« ra Oa. *_ >>• o ^r- ai ra
o> g*Di in J:,— -Q .—
> > >£ E E
05 *- £\J
~° E5 °
oto
aj tu a. a a. a a.c e'- > > > > >
en XS2 Oo —c X lt_-^ 0} <ro — -a
< < -<
o>
e e r
.eiE ,-
c nCD
rr <QJ
H~8
oa 1
t- o< DC
E E
I I> >
8- =
oI
o
rea
5 a g
c »- i-
o o oo *- *-
m- aj a;
r-n ^ ^ r-
<
^rFebruary 1983 53
TEA1016
286782
iAvd
(dB)
fj
-8
/-12
/\^ A »d
i
/-16
/'
\
-20
I \
\-24\
N-28 1
i i
R
210
180
150
120
90
60
30
- 30
-60
-90
120
-150
Fig. 10 Gain and phase characteristics of the arrangement of Fig. 9.
54 February 1983
TELECOMMUNICATIONS
RING MODULATOR FOR TELEPHONYAND INDUSTRIAL EQUIPMENT
TBA673
GENERAL DESCRIPTION
The TBA673 is a bipolar integrated circuit comprising a 4-transistor modulator or demodulator circuitThe excellent matching and temperature tracking of the four transistors in the circuit makes it suitablefor applications that are not possible with discrete components.
B3,4 B1 B2
h£
AFig. 1 Circuit diagram.
QUICK REFERENCE DATA
Collector-emitter voltage
Collector current
Base-emitter voltage di fference betweentransistors at -l E = 150 /xA
D.C. current gain difference betweentransistors at - 1 £ = 1 50 ,uA
Transition frequency at \q = 1 mACo I lector-base capacitance at Vqb = 5 V
Conversion loss at fc= 34 kHz
Carrier output power at fc= 34 kHz
Operating ambient temperature range
VCE max.
max.
,AV BEi
17,5 V
20 mA
5 mV
|AhFB imax. 0,008
fT typ. 320 MHz
ccb typ. 0,4 pF
-Ac typ. 0,75 dB
°oc typ. 3 nW
Tamb -25 to + 125 °C
PACKAGE OUTLINE
10-lead cylindrical; metal (TO-74; reduced height; SOT-14).
^rJanuary 1983 57
TBA673
Fig. 2 Pinning diagram,
bottom view.
PINNING
1 C1,4 collectors of TR1 and TR4
2 B1 base of TR1
3 E1,3 emitters of TR1 and TR3
4 B3, 4 bases of TR3 and TR4
5 C2, 3 collectors of TR2 and TR3
6 B2 base of TR2
7 E2, 4 emitters of TR2 and TR4
8 n.c. not connected
9 n.c. not connected
10 S substrate
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Collector-emitter voltage, open base VcEOEmitter-base voltage, open collector VeBOCollector-substrate voltage Vcg
Collector current, each transistor \q
Emitter cut-off current lEBO
Total power dissipation*
Storage temperature range
Operating ambient temperature range*
rtot
Tstg
Tamb
max. 17,5 V
max. 6,2 V
max. 65 V
max. 20 mAmax. 10 fiA
max. 250 mW-55 to + 125 °C
-25 to + 125 °C
Ptot
Imw} ,-r r ,
I
l\
l
I \
100
Tamb ("CI
Fig. 3 Power derating curve.
58
See derating curve, Fig. 3.
January 1983
Ring modulator for telephony
and industrial equipment
TBA673
CHARACTERISTICS
Tarn |-,= 25 °C unless otherwise specified
parameter
Collector-base breakdown voltage
at l E= 0; l c = 50 mA
Collector-emitter breakdown voltage
at l B = 0; lc = 200 mA
Collector substrate breakdown voltage
at —Is = 50/uA
Emitter-base breakdown voltage
at l c = 0; l E = 10 (/A
D.C. current gain at Vrjg = 5 V;
IC= 150mA
IC= 10mA
D.C. current gain difference between
transistors TR1 and TR2 or TR3 and TR4 at
VCB = 5 V;-I E = 150,uA
Base-emitter voltage difference between
transistors TR1 and TR2 orTR3 and TR4 at
VCB = 5 V; -l E = 150 nA
Collector cut-off current
at l E = 0;VCB = 5 V
Collector-substrate leakage current
at Vcs = 5 V
Emitter cut-off current
at l c --= 0; VEB = 1 V
Transition frequency at VqB = 5 V;
l c = 150nA
Ir; = 1 mA
Collector-base capacitance
atVCB = 5 V; l E =
Collector-substrate capacitance
at Vcs = 5 V; l E =0
symbol
v (BR)CBO
v (BR)CEO
V (BR)CS
v (BR)EBO
hFE
hFE
|Ah FB |
;avbe i
'CBO
f CS
'EBO
fT
fT
ccb
Cor
mm. typ.
45
17,5
65
6,2
35
35
90
75
0,002 0,008
2 5 mV
5 100 nA
5 100 nA
5 100 nA
140 — MHz
320 - MHz
0,4 - pF
2,8 — pF
V
V
V
V
^rJanuary 1983 59
TBA673
APPLICATION INFORMATION
VCC = 9V
Fig. 4 Typical application of the TBA673 as a telephony carrier ring modulator.
Performance at Tam b= 25 °C:
Conversion loss —
A
c= typical 0,75 dB
at fm = 1 kHz; Vm , rms)= 0,4 V; fc
= 34 kHz.
Carrier output power (leakage) Poc = 3 nW typ. at fc= 34 kHz;
Vc(rms) - 0,28 V.
PACKAGE OUTLINE
10-lead cylindrical; metal (TO-74; reduced height; SOT-14).
0.86 max
8,5max
max 12,7min
3r-' 0,51
bottom view
60 January 1983^r
TBA915G
AUDIO AMPLIFIER
TheTBA915G is a bipolar integrated a.f. amplifier intended for small communication receivers, where
low battery drain is of paramount importance. The maximum output power is 850 mW and the zero-
signal supply current is only 2 mA (typ.). The circuit can be squelched to a stand-by current of typ.
0,4 mA.
QUICK REFERENCE DATA
Supply voltage range
Supply current at Vqq = 12 Vsquelched
no signal
Input signal for P = 500 mWInput impedance, single-ended
Output power at dtot = 2,5%
Operating ambient temperature range
v Cc 3,5 to 15 V
'cc typ 0,4 mA
'cc typ 2 mA
'cc typ 72 mA
Vi(rms) typ 10 mV
lzisl typ 9 ktt
Po typ 500 mW20 to +80 °C
PACKAGE OUTLINE
9-lead SI L; plastic (SOT-110B).
^\rOctober 1982 61
TBA915G
J V.
62 October 1982^r
Audio amplifier TBA915G
I
i i i—
i
or~i
1 ?. 3
TBA915G
-1^67 8 9
ili u U u U IICX l+ I- HX SQ Q VCC
VEE1 vEE2
Fig. 2 Pinning diagram.
PINNING
1 CX external capacitor
2 l + non-inverting input
3 I- inverting input
4 RX external resistor
5 V E E1 ground
6 SQ squelch input
7 V E E2 ground
8 Q output
9 vCc positive supply
FUNCTIONAL DESCRIPTION
Supply Vcc and RX (pins 9 and 4)
The TBA915G has been designed primarily for use in pocket-size portable communication receivers, with alow supply current as its main feature. The supply current is mainly determined by the output current.The current into the RX connection sets an internal current source.
The circuit may be used over a wide range of supply voltages, viz. 3,5 to 15 V. At 12 V the circuit is
capable of delivering a power of 500 mW into a load of 20 SI. The maximum output power may beincreased to 850 mW by increasing the supply voltage to 1 4 V and reducing the load impedance to 1 5 n.
Inputs 1+ and I- (pins 2 and 3)
Inputs l+and I- are differential inputs. 1+ is the non inverting input, I- the inverting input. Thecircuit may be driven asymmetrically, as is done in the test circuit of Fig. 4, where I- is used as afeedback input. The circuit has an open-loop gain of 60 dB.
Squelch input SQ (pin 6)
A current into the SQ input squelches the amplifier, it brings the circuit in a stand-by state with a sub-stantially reduced supply current.
Output Q (pin 8)
The circuit has a quasi-complementary class-B output stage.
^rOctober 1982 63
TBA915G
RATINGS
Limiting values in accordance with the Absolute Maximum System I
Supply voltage, d.c.
Supply current
Bias current into RX
Input voltage, differential, I + and I- inputs
Input current, I + and I- inputs
Input current, SQ input
Output voltage
Output current
Total power dissipation
Storage temperature range
Operating ambient temperature range
CHARACTERISTICS
VCC = 12 V; V E e =0V; Tamb = 25 °C; measured in test circuit F
64
IEC 134)
VCC max. 17 V
ice max. 350 mA
|rx max. 5 mA
|V| D i
max. 5 V
llmax. 0,5 mA
!SQ max. 1 mA
-'SQ max. 10 mA
VQ max. 17 V
±'Q max. 350 mA
ptot max. 900 mW
Tstg-55 to + 125 °C
-20 to + 80 °C
g. 3; unless otherwise specified
parameter
Supply VccSupply current
squelched
quiescent
P = 500 mWVariation of quiescent supply current
with supply voltage
Thermal resistance
RX
Bias current into RX
Inputs I + and I—
Input voltage for P = 500 mW
Input impedance, single-ended
Open-loop differential voltage amplification
Squelch input SQ
Input current HIGH (circuit squelched)
at Irx = 25 to 75 hA
Input voltage HIGH at Isqh = 10 //A
Input voltage LOW (circuit on)
Output Q
Total distortion at P = 500 mWSignal-to-noise ratio at P = 500 mW;
Rs = 600 n, f = 300 Hz to 6 kHz
symbol
! CC'ccl CC
AI CC/AVCC
R th j-a
'RX
typ.
0,4
2
72
0,06
50
0,6
3,7
25
v i(rms)- 10 15 mV
Izisl- 9 - ka
Avd— 60 dB
'SQH 10 _ — liA
VSQH- 0,65 - V
VSQL- — 0,4 V
dtot- 2,5 5 %
S/N - 72 - dB
75
mAmAmA
mA/V
K/W
MA
October 1982
Audio amplifier TBA915G
Fig. 3 Test circuit.
APPLICATION INFORMATION
R54,7D
R2330O
"]~6^8^F
i+ TBA915G
CX V£E1 V EE2
1
7ZZ
47pF
rflh-
10M R3 /! T son rY
7ZB02B2 755
Fig. 4 Typical application of the TBA915G. The frequency range is 185 Hz to 5,2 kHz; the lower
frequency limit is determined by the time constants |zjs |
x C1 , R2 x C2 and R3 x C3 and the upper
frequency limit by R4x C4. The closed-loop gain is 39,5 dB with a stability margin greater than 18 dBwhich is determined by R5 x C5 and R6 x C6. The arrangement produces an output voltage and
output power at 1 kHz which are (typical):
vo(rms) = 1-24 v -
po = 30 mW at VCC = 5 V and dtot = 5%
vo(rms)=
1.7 V, P = 56 mW at Vqc = 6,8 V and dtot = 0,25%
V (rms) = 1 .9 V, PQ = 72 mW at Vcc = 6,8 V and dtot = 5%
~\rOctober 1982 65
TCA210TCA210T
AUDIO AMPLIFIER
GENERAL DESCRIPTION
The TCA210 is a bipolar integrated circuit comprising an amplifier for use in intercoms and other audio
systems. The amplifier is split into two parts. The first part is a high-gain preamplifier with differential
inputs and a class-A output stage which can deliver 2,5 mW into an 800 12 load. The second part is a
power amplifier with a class-B output stage capable of delivering 500 mW into a 25 SI load and up to
800 mW into 15 J2 for short periods.
Without signal the supply current is typ. 8 mA. Both amplifiers may be squelched to extend battery
life in battery-operated equipment.
QUICK REFERENCE DATA
Supply voltage range
Supply current, no signal
Preamplifier
Open-loop voltage amplification
Output power at R[_ = 800 fl
Noise figure
(R s = 500 $2; B = 300 to 4000 Hz)
Unity-gain bandwidth (compensated)
Power amplifier
Open-loop voltage amplification
Output power at dtot = 5%;
R L = 25fi
R L = 1512
Operating ambient temperature range
vCc 8 to 16 V
'cc typ. 8 mA
Avd typ. 10 000
Po typ. 2,5 mW
F max. 6 dB
f| min. 10 MHz
Avd typ. 500
Po typ. 500 mW
Po typ. 800 mWTamb -55to+ 125 °C
PACKAGE OUTLINE
TCA21 0: 16-lead Dl L; plastic (SOT-38).
TCA210T: 14-lead mini-pack; plastic (SO-14; SOT-108A).
February 1983 67
TCA210TCA210T
-M-
-M—J—
I * W
-w- -w-
A
68 February 1983^r
Audio amplifier TCA210TCA210T
PINNING TCA210
1 11-
2 RX1
3 Q1
Tj] VEE1
4
5
FC
,,-rr u12-
RX1 []T 7T]m + 6 i.c.
Q1 [T
FC \T_
TCA210
IT] VCC1
77] 12+
77], c
7
8
9
RX2
VEE2
Q2
i.e. [jT TTJ i.e. 10 VCC2
RX2 [T_ To] VCC2 11 i.e.
VEE2 [7£ T] Q212
13
14
i.e.
12+7Z80293
VCC1
15 11 +
16 VEE1
preamplifier inverting input
external resistor, preamplifier
preamplifier output
frequency compensation
power amplifier inverting input
internally connected
external resistor, power amplifier
ground connection, output stage
of power amplifier
power amplifier output
positive supply, power amplifier
internally connected
internally connected
power amplifier non-inverting input
positive supply, preamplifier
preamplifier non-inverting input
ground (except for output stage
power amplifier)
PINNING TCA210T
I1-| ! |
RX1 I 2|
Q1|3
|
FC 1 4
12- | 5
RX2|6 [
EE2|
7|
j
12|
VCC1
TCA210T
13|
11+
j11
|12 +
|9 |
VCC2
Fig. 2 Pinning diagrams.
1 11-
2 RX1
3 Q1
4 FC
5 12-
6 RX2
7 VEE2
8 Q2
9 VCC210 i.e.
11 12+
12 V CC113 11 +
14 V E E1
preamplifier inverting input
external resistor, preamplifier
preamplifier output
frequency compensation
power amplifier inverting input
external resistor, power amplifier
ground connection, output stage of power
amplifier
power amplifier output
positive supply, power amplifier
internally connected
power amplifier non-inverting input
positive supply,preamplifier
preamplifier non-inverting input
ground (except for output stage
power amplifier)
~\rFebruary 1983 69
TCA210TCA210T
FUNCTIONAL DESCRIPTION
Supply
The preamplifier and the power amplifier have separate supply pins. When one of the amplifiers is not
used the corresponding Vqq P'n mav De left open to save supply current.
The ground pin VEgi is common for both amplifiers except for the output stage of the power amplifier
which has a separate ground pin Vf£E2- This minimizes undesirable feedback to the rest of the circuit.
External resistor pins RX1 and RX2
The current in the amplifiers is determined by current sources. These current sources need a minimumcurrent into their RX pins of 200 mA. This current is usually derived from the positive supply via an
external resistor.
The preamplifier and the power amplifier may be switched off (squelched) by applying a LOW level to
RX1 and RX2 respectively.
Preamplifier inputs 11+ and 11—
The preamplifier has differential inputs 11+ and 11-, 11 + being the non-inverting input and 11- the
inverting input. The circuit may be driven asymmetrically, e.g. 11— may be used for negative feedback.
Frequency compensation pin FC
Frequency compensation of the preamplifier may be obtained by connecting an external RC networkbetween FC and ground (see Fig. 4).
Preamplifier output Q1
The preamplifier has a class-A output consisting of an emitter follower with a current source from the
emitter to ground.
Power amplifier inputs 12+ and 12—
The power amplifier has differential inputs 12+ and 12-, 12+ being the non-inverting input and 12- the
inverting input. The circuit may be driven asymmetrically, e.g. 12— may be used for negative feedback.
Power amplifier output Q2
The power amplifier has a class-B output stage. This output stage is current-driven, which guarantees
negligible crossover distortion even at small output signals.
70 February 1983
Audio amplifier
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage, d.c.
Supply current
Input voltage, all inputs
Differential input voltage
Input current, 11+, 11-, 12+and 12-
Output voltage, Q1 and Q2
Output current
Q1
Q2
Storage temperature range
Operating ambient temperature range*
TCA210TCA210T
vcci; vcc2 max. 17 V
>CC1 max. 20 mA
'CC2 max. 550 mA1 rx 1 ; !rX2 max. 5 mAV| max. vCc v
iv H + -V|i- max. 5 V
|V|2 + -V,2_ max. 5 V
"l max. 0,5 mAvQi;vQ2 max. 17 V
I'Qll max. 20 mAllQ2i max. 550 mATstg -55 to + 125 °C
Tamb -55 to + 125 °C
1000 7Z62294.1
- —-
Ptot
(mW) — -- - -
- -
;
500 i
-
; i i
-i j
i -
-H ~i - -!
i
n 1
100 100 TQmb (°C) 200
Fig. 3 Power derating curve.
'' See Fig. 3.
"^rFebruary 1983 71
TCA210TCA210T
CHARACTERISTICS
VCC = 12 V; Tam b= 25 °C unless otherwise specified
parameter symbol min. typ. max. unit
Supply VCC1 and VCc2Supply current (d.c), no signal 'CC1 4 mA
'CC2 4 - mA
External resistor pins RX1 and RX2
Voltage at RX: ON VRXH 1,1 1,35 1,6 V
Voltage at RX: squelched V RXL 250 mVCurrent into RX: ON !rXH 200 MA
Preamplifier inputs 11+ and 11—
Average input current | n+; 'n- 2,5 ma
Preamplifier output Q1
Quiescent current in output stage 'c 2,5 mA
Open-loop voltage amplification Avd 65 80 dB
Unity-gain bandwidth with
6 dB/octave compensation f| 10 MHz
Noise figure at Rg = 5 kS7;
B = 300 to 4000 Hz F 4 - dB
Power amplifier inputs 12+ and 12—
Average input current !|2+; ! I2- 2 - MA
Power amplifier output Q2
Open-loop voltage amplification Avd 54 dB
Output power at R |_= 25 S2;
dtot = 5% Po 450 mWTotal distortion at f = 1 kHz;
Po = 50mW; R L = 25 ft dtot 1,5 %
72 February 1983^\r
Audio amplifier TCA210TCA210T
>E
g gE E se .* E
O
r-<o_iQ.a.<
<HI
"- g 8 8 "- * 'cs; id oo """
a a a a a o a> > > >• >• £ >-
_ E
oa.
o ou
CMOo
s =
in ca
_c3 o O
Q. I
cCD
C .2
aE
0)ucCO-oajaF
o0)
CO
O
DCO
5 ">o ™a.
II
GIX)
u
CD
Co
o
>oc0)3o-cu
3*->
ca;i_k_
3U
ECO
c<T3 o
CM D j|~ >~09
soa.
3ac
3ac
_J
GC 3oh-
93o
aa3e/3
CO
oCM<( !
(-
cu > g I <-C a b E E
o 8 lf>_ if)
cm"
"d- Tf
ocaoa
Q. n a n a.CO
oUoIf)
> > > ;»• >
> CM b ,_r— II ^. o* f2
ECO
_N > a.o O
o>r-
> >CM o Ct
II ou a o cao 3 u> o CO
<2cc
O£ & ai.i§E 3 ^
S ~
k- 0)» 35 tro £a it
3 *=
a ?
O O co
"A^"February 1983 73
TCA240TCA240D
DUAL LONG-TAILED PAIR/DOUBLE-BALANCED MODULATOR
GENERAL DESCRIPTION
The TCA240 is a bipolar integrated circuit comprising two long-tailed pairs with current sources. The
circuit may be connected to form a double-balanced modulator. It features great flexibility and the
excellent matching and temperature tracking of the transistors in the circuit makes it suitable for
applications that are not possible with discrete components.
The circuit is especially suited for the following applications:
• modulator
• mixer
• switch or chopper
• AM synchronous demodulator
• FM quadrature demodulator
• phase comparator
• differential amplifier
QUICK REFERENCE DATA
Supply voltage at C1, C2, C5 and C6
Emitter current (each transistor)
D.C. current gain at — If = 750 (jA
Base-emitter voltage difference between
transistors at Itail=
1 ,5 mA
Cut-off frequency (3 dB point)
Noise figure at f = 100 MHz; lc = 1 mAOperating ambient temperature range
vc max. 16 V
-'E max. 10 mA
hFE min. 23
AVBE |
max. 2,5 mV
xo typ. 34 MHz
F max. 3,7 dB
Tamb -20 to + 70 °C
PACKAGE OUTLINE
TCA240: 16-lead DIL; plastic (SOT-38).
TCA240D: 16-lead mini-pack; plastic (SO-16; SOT-109A).
^rJanuary 1983 75
TCA240TCA240D
Jk.C1 C2 C5 C6
13 11
>ir<TR1 TR2 I—i i 1 TR5 TR6
<TR3 TR7>
TTTR4 TR6
R1 R2 R3 R4
150O 150O 150Q 150O
-n lh
Fig. 1 Circuit diagram.
Pins 9 and 16 are both connected to the substrate. When both long-tailed pairs are used these pins
should be interconnected externally.
E3 [~r u TtTj VEE1
B3 QT Tj] B4
bi [jr 14] CI
B2 [jF
B5 [ITTCA240
Tj] C5
TJJ C2
B6 [J£ TTJ C6
B7 \T~ To] Be
E7 [J£~9~[ VEE2
E3FT"
B3 [ 2|
B1| 3
B2|4
|
B5| 5
|
B6 | 6[
B7 | 7|
E7 | 8[
TCA240D
1
16I
1
15I
1
14I
13|
I
12I
I
11I
I
10I
I
9I
VEE2
76
Fig. 2 Pinning diagrams.
January 1983^\r
Dual long-tailed pair/double-balanced modulator TCA240TCA240D
FUNCTIONAL DESCRIPTION
The TCA240 contains two long-tailed pairs, each with a current source and a series transistor in the tail.
The current sources contain a current mirror. The tail current will be equal to the current flowing into
pin 15 (10) with a deviation of less than 5%.
The TCA240 may be used as two long-tailed pairs or as a single double-balanced modulator. When used
as two long-tailed pairs the tail currents may be adjusted separately. V^ei and Vgf£2 (pins 9 and 16)
should be interconnected and E3 and E7 (pins 1 and 8) should be left open. Transistors TR3 and TR7reduce the influence of the long-tailed pair on the tail current.
When the circuit is used as a single double-balanced modulator only one current source is required.
E3 and E7 (pins 1 and 8) should be interconnected and B8 and Vr:E2, pins 10 and 9 (or B4 and Vf£f£i,
pins 15 and 16) should be left open. TR3 and TR7 form a long-tailed pair now, each with a long-tailed
pair at its collector.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Collector-substrate voltage (open base and emitter) Vrx;o
Collector-base voltage (open emitter) V(;go
Collector-emitter voltage (open base) VqeoBase-emitter voltage (open collector) —VgEOEmitter current (each transistor) — lg
Base current (each transistor) lg
Total power dissipation (see also Fig. 3) Pt,
Storage temperature range
Operating ambient temperature range
rtot
r stg
fan-ib
max. 16 V
max. 16 V
max. 12 V
max. 5 V
max. 10 mAmax. 10 mA
max. 500 mW-55to+ 125 °C
-20 to + 70 °C
10001 hi [
r t
- —r
\!
i
\~-X-p.. ..rtot 'ill r^ ++-
(mW) !
. '_.,._.j"7 1 f"
1
! :
500: 1
i
t t"~— -t—p • -—
r~^_ ~T~r 1
jl
]
rr i--!
- r~i
—
r i
—
rf--tl""1 "
J-r-r_-
*^w ! .u, .\-' *.,
»>,
~m r-
k.
:!
j j^ !
j
i
xk .i !
50 100 Tamb (°C) 150
Fig. 3 Power derating curve.
January 1983 77
TCA240TCA240D
CHARACTERISTICS
atVc1 =VC2 = VC5 = Vc6=12V;V b1 =Vb2 = Vb5 = V B6 = 6V;
VB3 = V B7 = 4 V; VEE1 = VEE2 = V;
Tamb = 25 °C; unless otherwise specified
parameter symbol min. typ. max. unit
Transistors TR1, TR2, TR5 and TR6
D.C. current gain, each transistor,
at — l E = 750juA "FE 23 - 190
Relative d.c. current gain difference
of transistors TR1 and TR2at I E 1 + l E 2
= -1,5 mAhc E i— hc Eo
x200h FE1 +hFE2
-60 + 60 %
Relative d.c. current gain difference
of transistors TR5 and TR6at l E 5 + l Ee
= -1,5 mAnFE5—
n
FE6htb^ x200
hFE5 +nFE6-60 + 60 %
Base-emitter voltage difference
between TR1 and TR2 (TR5 and TR6)
at l ta j|= 1,5 mA |AVBE
|
_ _ 2,5 mV
D.C. current gain of the parallel
connection of TR1 and TR6 (TR2 and TR5)
at lta j|= 3 mA hFE1+6. n FE2 + 5 23 - 190
Relative d.c. current gain difference of
the parallel connection of TR1, TR6and TR2, TR5 at l ta j|
= 3 mAhFE1 + 6-hFE2 + 5
x200nFE1+6 + hFE2 + 5
-60 + 60 %
Base-emitter voltage difference
between the parallel connection of
TR1, TR5 and TR2, TR6 at ltaU = 3 mA |AVBE|
_ — 2,1 mV
Transistors TR3 and TR7
D.C. current gain, each transistor,
at lta j|= 3 mA "FE 23 - 190
Relative d.c. current gain difference
of transistors TR3 and TR7at l ta j|
= 3 mAhccT— hc E7ttJ
x200nFE3 +hFE7
-60 + 60 %
Base-emitter voltage at —l E = 1 mA V B E 690 - 770 mV
Transistors TR4 and TR8
Collector current difference
at Ig4 =I B8
= 1>5 mA AI C 0,07 mA
78 January 1983
~^
Dual long-tailed pair/double-balanced modulator TCA240TCA240D
parameter
Cut-off frequency
3 dB point at l tai |
= 5 mA; Rq = 600 Q,;
see test circuit Fig. 4
Noise figure
at f = 100 MHzG
s= 3,7 mA/V
atf = 100 MHz
l c = 1 mA; VCB = 5 V;
-B s= 2,5 mA/V
-l E = 2,5mA;VCB = 5 V;
-Bs= 2,5 mA/V
symbol min. typ. max. unit
34
3,7
4,2
MHz
dB
dB
y parameters
at VCE = 5 V;f = 100 MHz
Input conductance
Input susceptance
Feedback admittance
Phase angle of feedback admittance
Transfer admittance
Phase angle of transfer admittance
Output conductance
Output susceptance
Switching times
(See test circuit, Fig. 5)
Rise time
Fall time
Rise propagation delay time
Fall propagation delay time
tail
t~n_H typ-
tTHL typ.
tpLH typ-
tPHL typ.
-I E = 1 5 mA
9ie typ. 4,4 13,6 mA/V
t>ie typ. 7,6 9 mA/V
lYre! typ- 0,4 0,4 mA/V
-<pre typ. 100° 100°
ivfel typ- 22 55 mA/V
-ffe typ- 45° 96°
9oe typ. 0,4 0,5 mA/V
i-;oe typ 1,8 18 mA/V
^\rJanuary 1983 79
TCA240TCA240D J V
Fig. 4 Test circuit for the frequency response, shown for one half of the circuit.
80
J- i°°r (h fk
Fig. 5 Test circuit for the switching times, shown for one half of the circuit.
January 1983-^r
Dual long-tailed pair/double-balanced modulator TCA240TCA240D
Cl C2
PI'
C5 C6
TCA240TCA240D
X
Fig. 6 Typical application of the TCA240 as a double-balanced AM modulator with suppressed carrier.
C5 C6
TCA240TCA240D
XFig. 7 Typical application of the TCA240 as an AM modulator.
ArJanuary 1983 81
TCA240TCA240D
VCC = 6V
tko ikn
I10uF 7=,
V, (^) 1,5kQ
¥
JLl
TCA240TCA240D
TFig. 8 Typical application of the TCA240 as a differential amplifier.
3,6kfi
VCC = 6V
_l_
r—llhr
t
C> C2
TCA240TCA240D
"X
Fig. 9 Typical application of the TCA240 as a cascode amplifier.
82 January 1983^r
Dual long-tailed pair/double-balanced modulator TCA240TCA240D
4,7kn Ikfi ikn
3,3kn
3,3kn
IF
Cl C2 C5 C6
TCA240TCA240D
TFig. 10 Typical application of the TCA240 as a differential amplifier with gain control.
VCC = 6V
F
I
22nF(2x
3!H
kn iko
LXC5 C6
TCA240TCA240D
X
Fig. 1 1 Typical application of the TCA240 as a 10,7 MHz double-balanced FM demodulator.
^January 1983 83
TCA770ATCA770D
I.F. LIMITING AMPLIFIER, FM DETECTOR & AUDIO PREAMPLIFIER
with low supply current
GENERAL DESCRIPTION
The TCA770 is a bipolar integrated circuit comprising a limiting amplifier, a balanced FM detector andan audio preamplifier. It is intended for a frequency range of 100 to 500 kHz with narrow-band FM.The circuit is especially suited for use in portophone sets, where low supply current and high sensitivityare of paramount importance.
QUICK REFERENCE DATA
Supply voltage range
Supply current
I.F. frequency
Input voltage at onset of limiting
AM rejection at Af = ± 3,5 kHz; m = 0,3;
fm = 1 kHz;V L | (rms)= 1 mV
A.F. output voltage at Af = ± 3,5 kHz
Audio preamplifier open-loop voltage amplification
Operating ambient temperature range
vCc 5 to 10 V
'cc typ. 450 /jA
fif typ. 100 kHz
v Lllim(rms) typ. 30 /jV
kAMR typ. 50 dB
vQA(rms) typ. 90 mV
Avd typ. 600
Tamb -30 to +70 °C
PACKAGE-OUTLINES
TCA770A: 16-lead DIL; plastic (SOT-38).
TCA770D: 14-lead mini-pack; plastic (SO-14; SOT-108A).
^rJanuary 1983 85
TCA770ATCA770D
86 January 1983~\r
I.F. limiting amplifier, FM detector
and audio preamplifier
L,M uj3 vEE2
REF [IT2i] *cc
,c.[T TT| n c
BIAS [T|
VEE1 \YTCA770A
T3] QA
T7| IA +
CX1 [IT TT[ ia-
CX2 [T~ U)] OD
LCX1 [IT "j~| LCX2
TCA770ATCA770D
PINNING TCA770A
1 LI limiting amplifier input
2 REF reference input, limiting amplifier
3 n.c. not connected
4 BIAS input biasing output
5 Vgr£i ground
6 CX1 external capacitor
7 CX2 external capacitor
8 LCX1 external tank circuit
9 LCX2 external tank circuit
10 QD detector output
11 IA— audio preamplifier out-of-phase input
12 IA+ audio preamplifier in-phase input
13 QA audio preamplifier output
14 n.c. not connected
15 VrjQ positive supply
16 Vg£2 ground
liHT"
REF|2
[
BIAS[3
|
VE E1[
4|
CXI j5
J
CX2[6 |
LCX1 | 7|
TCA770D
I'3
|vcc
9 |QD
|8
|LCX2
Fig. 2 Pinning diagrams.
PINNING TCA770D
1 LI limiting amplifier input
2 REF reference input, limiting amplifier
3 BIAS input biasing output
4 Vf££i ground
5 CX1 external capacitor
6 CX2 external capacitor
7 LCX1 external tank circuit
8 LCX2 external tank circuit
9 QD detector output
10 IA— audio amplifier out-of-phase input
11 IA+ audio preamplifier in-phase input
12 QA audio preamplifier output
13 Vcc positive supply
14 Vf£E2 ground
^\rJanuary 1983 87
TCA770ATCA770D
FUNCTIONAL DESCRIPTION
The TCA770 consists of two parts that may be used independently; a limiting amplifier with balanced
detector, and an audio preamplifier.
Supply
The TCA770 has two ground connections V^ei and VgE2 which are internally interconnected. For
minimum interference it is recommended that both Vgg connections be grounded.
The circuit is built on the basis of long-tailed pairs with current sources in their tails. Thanks to these
current sources the supply current varies little with the supply voltage. This allows the circuit to be
used over a wide supply voltage range (5 to 10 V) without resulting in an excessive battery drain.
When the audio preamplifier is not used, its output QA should be connected to VrjC'
Limiting amplifier
The limiting amplifier has differential inputs LI and REF. One of the outputs provides a bias voltage
for these inputs via the BIAS connection; this gives a feedback adjustment of the working point.
The onset of limiting is specified by the input voltage giving 3 dB gain reduction. This input voltage
varies with frequency (see Fig. 3).
Balanced FM detector
The outputs of the limiting amplifier are connected internally to the balanced detector. A tank circuit
has to be connected to this detector via CX1.CX2, LCX1 and LCX2 (see Fig. 5).
The balanced detector has a single output QD. Its output voltage varies with temperature (see Fig. 4).
Audio preamplifier
The audio preamplifier has differential inputs IA+ and IA-. IA+ is the in-phase input, IA— the
out-of-phase input.
The output QA is an emitter follower with a current source to ground which sinks typ. 56 AiA. The
output is suited to drive an output stage with an input impedance of approx. 10 kf2.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage (d.c.)
Storage temperature range
Operating ambient temperature range
vCc max. 15 V
Tstg -55 to +125 °C
Tamb -30 to + 70 °C
88 January 1983
I.F. limiting amplifier, FM detector
and audio preamplifier
TCA770ATCA770D
CHARACTERISTICS
VCC = 7,5 V; TamD = 25 °C; fjf = 100 kHz; measured in test circuit of Fig. 6; unless otherwise specified
parameter symbol min. typ. max. unit
I Supply VccSupply voltage vCc 5 7,5 10 V
Supply current 'cc 300 450 600 MA
Limiting amplifier input LI
Input impedance IZliI 10 kaInput voltage for onset of limiting
(3 dB gain reduction) v Lllim(rms) 30 Mv
AM rejection
FM signal: Af = ±3,5 kHz; fm = 70 HzAM signal: m = 0,3; fm = 1 kHz
atV L | (rms) = 300jiV kAMR 40 dB
atV LI(rms) = 1 mV kAMR 50 dB
atV LI(rms) = 10 mV kAMR 60 dB
Detector output QD
A.F. output voltage at
R ioad= 10° k"; Af = ±3
.5 kHz
;
fm =1 kHz;V L | (rms) = 10mV vQD(rms) 90 mV
variation with temperatureAVQD(rms)
AT0,062 - dB/K
Distortion at Af = ± 5 kHz; fm = 1 kHz dtot - 2 3 %
Audio preamplifier inputs IA+ and IA-
Input bias current"I 270 nA
Audio preamplifier output OA
Sink current in output stage'sink 56 MA
Open-loop voltage amplification (unloaded) Avd 600
ArJanuary 1983 89
TCA770ATCA770D
40
Vli lim (rms)
(MV)
30
400 1000
fif
(kHz)
AVqd (rms)
(tJB)
Tamb <°C>
Fig. 3 Variation of input voltage at onset
of limiting with frequency.
Fig. 4 Variation of detector output voltage
with temperature.
m m
(1) The input limiting voltage depends on the capacitance values. Suggested type: solid aluminium
capacitor, 2222 122 56687; 0,68 mF/25 V.
Fig. 5 Test circuit and typical application of the TCA770. The output voltage
isVQA = (R1 +R2)/R2x V|A+ .
90 January 1983
TCA980G
MICROPHONE AMPLIFIER
GENERAL DESCRIPTION
The TCA980G is a bipolar integrated microphone amplifier. It is primarily intended for use with low-
impedance microphones in telephone systems. The output of the amplifier is 210 V/kPa when used
with a microphone having an impedance of 200 £2 and a sensitivity of 10 mV/kPa.
A capsule assembly containing the TCA980G, a low-impedance microphone and a 220 nF capacitor
can directly replace a carbon microphone. The circuit is intended to be supplied from the telephone
line, the line current may be of either polarity.
QUICK REFERENCE DATA
Supply current range
Supply voltage drop at ± l|_|\|2 = 10 mAVoltage amplification at ± ! l_N2
= 30 mAat ± l|_|\|2 = 10 mA
Output impedance at ± I |_n2= 30 mA
Operating ambient temperature range
± 'LN2 10 to 100 mA
IV|_N1--V LN2 I typ. 4,75 V
Avd typ. 220
Avd min. 160
lz odl typ. 150 a
Tamb -35 to + 75 °C
PACKAGE OUTLINE
9-lead SI L; plastic (SOT-110B).
^rFebruary 1983 91
TCA980G
92 February 1983^r
Microphone amplifier TCA980G
o o-TZ\ rn m
__J TCA980G1234 56 7 89
LNi n.c. LN2 n.c. n.c. n.c. MIC n.c. Vee
7Z80283
PINNING
1 LNI line terminal 1
2 n.c. not connected
3 LN2 line terminal 2
4 n.c. not connected
5 n.c. not connected
6 n.c. not connected
7 MIC microphone input
8 n.c. not connected
9 Vee reference
Fig. 2 Pinning diagram.
FUNCTIONAL DESCRIPTION
At its line terminals LN1 and LN2 the TCA980G is compatible with a classical carbon microphone.
The circuit then is supplied from the telephone line and produces its own supply voltage, irrespective of
the direction of line current flow. The output voltage is produced across the same line terminals
LN1 and LN2. The circuit is well stabilized with the result that circuit properties such as gain and d.c.
voltage drop vary little with line current.
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply current, LN1 and LN2
d.c. ±I LNnon-repetitive peak ± 'LN(SM)
Input current, d.c.
Total power dissipation
Storage temperature range
Operating ambient temperature range
'MIC
stg
Tamb
max. 100 mAmax. 100 mA a.c. super-
imposed on 100 mA d.c.
max. 100 fiA
see Fig. 3
-55 to +125 °C
-35 to +75 °C
^\rFebruary 1983 93
TCA980G
yvCHARACTERISTICS
± I |_N2= 10 to 60 mA; Tamrj = 25 °C unless otherwise specified.
parameter symbol min. typ. max. unit
Supply
Supply voltage drop
at± l|_M2 = 10 mA lv LN1 ~V|_N2l 3,5 4,75 5,75 V
at± li_N2 = 30mA iV L |\|1-V LN 2l 4,45 - 6,75 V
at± li_N2 = 60mA>V LN1 - v LN2l 5,0 - 7,8 V
Gain
Voltage amplification at f = 2 kHz;
Tamb = 25°C;seeFig.4;
at± I LN2 = 10 mA Avd 160 260
at± Iln2 =3° mA Avd 190 220 260
Variation of voltage amplification with
temperature for Tamb = —20 to + 55 °C AAvd/Avd— _ 10 %
Variation of voltage amplification with
frequency for f = 0,3 to 2 kHz AAvd -1 3 dB
Output
Output voltage swing, clipped,
at± Iln2 = 1° mA v LN1-LN2(p-p) 2,6 - — V
at ± I i_N2= 3° mA v LN1-LN2(p-p) 3,5 - - V
at ± l[_|\|2 = 60 mA VlN1-LN2( P -p) 2,6 - - V
A.C. output voltage at f = 2 kHz;
dtot = 5%;
at ± IlN2 = 10 mA v LN1-LN2(rms) 1 V
at ± li_N2 = 30mA v LN1-LN2(rms) 1,35 - - V
at ± l LN2 = 60mA v LN1-LN2(rms)- 1,5 - V
Noise output voltage at B = 0,3 to 4 kHz V n (rms)- - 1,3 mV
Output impedance at f = 2 kHz;
± l[_N2 = 30mAlzodl
- 150 - n
94 February 1983^r
Microphone amplifier
J VTCA980G
mnn 7Z80284
I— -I- -ihot(mW) i
j ,
'1
: r^!
j
i
r
* Hi i
- !
I^\ —
i
. j. _..i. ....
i
_± _Ll.]-40 40 80 120
Tamb ' c '
Fig. 3 Power derating curve.
Fig. 4 Test circuit for voltage gain.
cradle
contact T
DIALLERUNIT
'
<^*^K~*U '
telephone
line
1 MIC LN1r MIC LN
jQ TCA980G
1 V EE LN
Fig. 5 Typical application of the TCA980G.At pins LN1 and LN2, the IC is compatible with
a carbon microphone in a classical subscriber set.
February 1983 95
TDB1080
I.F. LIMITING AMPLIFIER, FM DETECTOR & AUDIO AMPLIFIER
GENERAL DESCRIPTION
The TDB1080 is a bipolar integrated circuit comprising a limiting amplifier, a balanced FM detector
and a class-B audio amplifier. It is intended for frequencies up to 500 kHz with either narrow-band or
wide-band FM. The circuit is especially suited for use in portophone sets, where a low supply voltage, a
low supply current and a high sensitivity are of paramount importance.
QUICK REFERENCE DATA
Supply voltage range
I.F. part
A.F. part
Supply current at Vrjci = VrjC2 = 2>5 v - no signal
Input voltage at onset of limiting
AM rejection at Vj = 1 mVOpen-loop voltage amplification of audio amplifier
Output power of audio amplifier at V(X2 = 9 V
Operating ambient temperature range
VCC1 2,3 to 3,5 V
VCC2 2,3 to 1 V
"CC1 + I CC2 typ. 3 mA
v l1lim(rms) typ. 30 mV
kAMR typ. 50 dB
Avd typ. 200
Po typ. 65 mW
Tan-ib -20to+ 70 °C
PACKAGE OUTLINE
)16-lead DIL; plastic (SOT-38S).
^rFebruary 1983 97
TDB1080
98 February 1983^\r
I.F. limiting amplifier, FM detector & audio amplifier TDB1080
PINNING
1 VCC12 11
3 REF
4 BIAS
5 RCX1
6 RCX2
7 RCX3
8 RCX4
9 QD
10 12-
11 12 +
12 CX
13 BS
14 V E E
15 QA
16 VCC2
VCC1 [T uTi"] V<X2
MfT TT] qa
REF [JT TJJ vee
BIAS [T^
RCX1 [7TTDB1080
Til Bs
TT| ex
RCX2 [J£ TT| 12+
RCX3 [~7~_ To] 12-
RCX4 [IT ~9~| QD
Fig. 2 Pinning diagram.
positive supply, limiting amplifier
limiting amplifier input
reference input, limiting amplifier
input biasing output
external RC network
external RC network
external RC network
external RC network
FM detector output
out-of-phase input, audio amplifier
in-phase input, audio amplifier
external capacitor
bootstrap
ground
audio amplifier output
positive supply, audio amplifier
FUNCTIONAL DESCRIPTION
The TDB1080 consists of two parts that may be used independently, viz. a limiting i.f. amplifier with
balanced FM detector, and a class-B audio amplifier.
Supply
The two parts of the circuit have a common-ground pin V^g but separate supply pins Vqci and V(jc2-
The limiting amplifier and detector may be used with a supply voltage up to 3,5 V, the audio amplifier
up to 10 V. The circuit is built to a large extent on the basis of long-tailed pairs with current sources in
their tails. Thanks to the stabilizer diodes (D7, D8 and D9) the supply current of the audio amplifier
varies little with the supply voltage. This permits the circuit to be used over a wide supply voltage range
without an excessive battery drain as a result.
Limiting amplifier inputs 11 and REF and biasing output BIAS (pins 2, 3 and 4)
The limiting amplifier has differential inputs 11 and REF. 11 is intended to be used as an input; it
should be biased externally by connecting it to the input biasing output BIAS via a resistor or an
inductor. The reference input REF is biased internally; it should be decoupled by connecting a
capacitor from REF to ground.
The onset of limiting is specified as the input voltage giving 3 dB gain reduction.
External RC network pins RCX1 to RCX4 (pins 4 to 8)
The TDB1080 contains a quadrature detector which requires an RC phase shifting network. This has to
be connected to RCX1, RCX2, RCX3 and RCX4as shown in Fig. 4. The component values have to be
chosen in accordance with the i.f. centre frequency.
Audio amplifier inputs 12 + and 12— (pins 1 1 and 10)
The audio amplifier has differential inputs 12 + and 12— which are biased internally.
~^rFebruary 1983 99
TDB1080
FUNCTIONAL DESCRIPTION (continued)
External capacitor pin CX (pin 12)
The internal biasing network for input 12 + should be decoupled by connecting an external capacitor
between CX and ground.
Audio amplifier output QA and bootstrap pin BS (pins 15 and 13)
The audio amplifier has a class-B output stage. The maximum output voltage swing is obtained by
connecting a capacitor between the bootstrap pin BS and the output QA and the load from
BSto VrjC2 < see F >9- 4 )-
The maximum output power varies from typ. 1 5 mW at VrjC2 = 2>5 v t0 tvP- ^5 mW at VCC2 = 9 v -
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltages, d.c. Vqqi max.
VCC2 max -
Supply current lfX1 + 'CC2 max -
Total power dissipation P^ot see Fig. 3
Storage temperature range
Operating ambient temperature range
'stg
'amb
-55 to
-20 to
5 V
10 V
50 mA
125 °C
4- 70 °C
inn
-40
Fig. 3 Power derating curve.
100 February 1983~\r
I.F. limiting amplifier, FM detector & audio amplifier TDB1080
CHARACTERISTICS
vcci = vcc2 = 2-5 v
;f
i= 95 kHz ; Af =
specified
: 50 kHz; fm = 1 kHz; Tamb = 25 °C unless otherwise
parameter symbol min. typ. max. unit
Supplies Vfxi and Vqc2 'P' ns 1 anc' ^6)
Supply voltages VCC1 2,3 2,5 3,5 V
VCC2 2,3 2,5 10 V
Supply currents
atV cc1 =2,5V 'cci- 1,5 2 mA
at Vr_;C2= 2,5 V, no signal 'CC2
- 1,5 2 mA
at VcC2 = 9 V, no signal !CC2- 3,5 mA
Limiting amplifier input 11 (pin 2)
Input impedance Izidl 15 - kft
Input voltage for onset of limiting
(3 dB gain reduction) v l1lim(rms)- 30 MV
Source impedance (between 11 and REF) |ZS I
- 5 k£2
A.M. suppression
at Afj = 70 Hz; fm = 1 kHz; m = 0,3;
R S = 50£2
atV| 1(rms) =300MV kAMR - 40 dB
atV|i (rms )
= 1 mV kAMR - 50 dB
atV| 1(rrns)= 10mV kAMR - 50 dB
R s =5knatV| 1(rms) =300MV kAMR - 30 dB
at V|i (rms) = 1 mV kAMR - 40 dB
atV| 1(rms) = 10mV kAMR - 50 dB
FM Detector output QD (pin 9)
Output voltage at dtot = 0,5%;
atfj= 95 kHz; Af = + 50 kHz vQD(rms) 100 - mVatf| = 250kHz; Af=±50kHz vQD(rms) 100 - mV
Signal-to-noise ratio
atfj= 95kHz;Af = ± 50 kHz S/N 70 - dB
atfj = 250kHz; Af = ± 50 kHz S/N 70 - dB
^rFebruary 1983 101
TDB1080
CHARACTERISTICS (continued)
parameter symbol min. typ. max. unit
Audio amplifier
Open-loop voltage amplification Avd - 200 -
variation with frequency,
f = 50 Hz to 15 kHz AAvd -1,5 — + 1,5 dB
Load resistance Rl 24 - 600 a
Output voltage at R|_ = 24 S7;
dtot =1% v QA(rms) - 600 - mV
Total distortion at R[_ = 24 f2;
VQA(rms) = 500 mV dtot- 0,5 1 %
Output power at Vcc2 = 9 V;
R L = 115 S2;d tot = 5% PQA - 65 - mW
Signal-to-noise ratio at R|_ = 1 15 12;
Vo = 600mV;f = 0,5 to 11 kHz;
80 dB/octave cut-off filter S/N 70 - - dB
?a to 600O
(1) If V(X2 isequal to Vqc1 P in 16 can be connected to pin 1 and the capacitor to pin 16 can be omitted.
102
Fig. 4 Test circuit and typical application of the TDB1080. For fj = 95 kHz R = 100 kSl and
C = 82 pF, for f, = 250 kHz R = 33 kS2 and C = 47 pF.
February 1983~\r
TEA1021
DTMF GENERATOR FOR TELEPHONE DIALLING
This integrated circuit is a dual-tone multi-frequency (DTMF) generator, supplying frequency
combinations (in accordance with CCITT recommendations) for use in pushbutton telephones, with a
common contact on the keyboard for muting.
The various frequencies are derived from a crystal-controlled oscillator followed by a sinewave
synthesizer.
I
2 L technology allows digital and analogue functions to be implemented on the same chip. The built-in
current/voltage regulator and active output amplifier substantially reduce the number of external
components. Only a quartz crystal of 4,78 MHz and a few resistors and capacitors are required.
The circuit features:
— wide operating line current range
— operating voltage down to 1,3 volt
— no individual tone level adjustment required
— temperature stabilized signal levels
— line current independent signal levels
— output stage and line regulator included
— all pins protected against electrostatic discharges
— two key roll-over provided
— operates with a low cost quartz crystal
— few external components required
OSCIL-
LATOR
CURRENTSTABILIZER
LINE
REGULATOR
-"TPROGRAMMABLE
DIVIDER
1209 . . . 1633Hz
PROGRAMMABLEDIVIDER
697 . . 941 Hz
DIGITAL TOANALOGUECONVERTER
DIGITAL TOANALOGUECONVERTER
KEYBOARD LOGIC
6 3 4 5 11 12 14 13
r> ACTIVE
OUTPUT STAGE
X X, X 2 X 3 Y Y, Y2
Y3 DAC Fj F V
Fig. 1 Block diagram (dotted lines are stabilized supply rails)
PACKAGE OUTLINES
TEA1021P: 16-lead DIL, plastic (SOT-38).
TEA1021D: 16-lead DIL, ceramic (SOT-74B)
^rMay 1982 103
TEA1021
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply current lp
Surge current (tp < 250 ais) 'S
Input series resistance
Operating ambient temperature range
Storage temperature range
Junction temperature
"s
Tamb
Tstg
Ti
max. 150 mAmax. 850 mAmin. 18 fi
-25 to +70 °C
-55 to + 125 °C
max. 125 °C
CHARACTERISTICS
V|\j = V; TamD = —25 to + 70 °C unless otherwise specified.
symbol min. typ. max. unit conditions
operating voltage
d.c; —11_= 10 mA V|_ 2,8 3,3 3,8 V
I
j
line current
level — 7 dBm 'L 10 8 120 mA I
level - 2 dBm 'L 12 9 120 mA
internal impedance Zi 640 900 1150 n 300 - 3400 Hz
tone frequencies
low fx0- 697 - Hz
fx1- 770 - Hz
fx2fx3
_ 852 - „ Hz- 941 - Hz
frequency
quartz crystal
high fy0— 1209 — Hz 4 782 720 Hz
fy1- 1336 - Hz
fy2- 1477 - Hz
fy3- 1633 - Hz
dividing error - - 0,11 %
nom. output level
lower frequency V LG- - -6 dBm adjustable
higher frequency v Hg - - -4 dBm adjustable
tolerance
on output level AV 2 - 2 dB
pre-emphasis 1,3 2 2,7 dB without filter components
distortion with respect to
total level d tot— -34 -24 dB maximum tone level and
with first-order filter
start up time *s- 5 — ms with recommended
external components
switch bounce
elimination tsb 1 1,5 2 ms
required keyboard
resistance
contact on R k on - - 10 kfi
contact off.
R koff 500 - - kn
104 May 1982T
DTMF generator for telephone dialling TEA1021
vn[T u l6]Vp
* 2l|v F
x,|T u]y 2
x2 [T
X3[TTEA1021
jE Y3
x o[T jj]y
F^ lo] osc
DAC [T] ~9~| OSC/NS
Fig. 2 Pin designation.
PINNING
1 v N negative supply
2 Fo filter output
3 X1 row keyboard input 1
4 X2 row keyboard input 2
5 X3 row keyboard input 3
6 XO row keyboard input
7 Fi filter input/input audio amplifier
8 DAC output DAC/DTMF tones
9 OSC/NS oscillator/noise suppression output
10 OSC oscillator input
11 YO column keyboard input
12 Y1 column keyboard input 1
13 Y3 column keyboard input 3
14 Y2 column keyboard input 2
15 v F input low-pass filter
16 VP positive supply
keyboard
Fig. 3 Application diagram with first-order filter.
R1 metal film resistor
R2 metal film resistor
R3 metal film resistor
R5 metal film resistor
C1 metallized polyester film capacitor
C2 solid aluminium electrolytic capacitor
D1 polarity guard and
transient suppressor bridge (see Fig. 6)
X1 quartz crystal
MR16 1% see Fig. 7
SFR16 5% 3,3 Win
SFR16 5% 18ft
SFR16 5% 2700 ft (for Z = 600 ft;
no resistor for Z = 900 £
see Fig. 7
6,3 V 4,7 mF
2x BAS11 and 2x BZW03-.
4,783 MHz
^rMay 1982 105
TEA1021
J V
1>
13 14 12 11
Xah 612 6/3
TnThbh6/ 6/o 6/ 61
n 6
/si/is A/
7
Fig. 4 Application diagram with second-order filter to minimize harmonic distortion (meets CEPT
CS203 requirements).
R1 metal film resistor
R2 metal film resistor
R3 metal film resistor
R4 metal film resistor
C1 metallized polyester film capacitor
C2 solid aluminium electrolytic capacitor
C3 miniature ceramic plate capacitor
C4 metallized polyester film capacitor
C5 solid aluminium electrolytic capacitor
D1 transient suppressor bridge (see Fig. 6)
X1 quartz crystal
r = r,= r2= t
3-
1209 1336 1477 1633Hz Hz Hz Hz
,HZ^A^>G
X,«941 Hz
4 5 6 B
7 8 9 c
* # D
106 May 1982 I |
MR16 1% see Fig. 7
SFR16 5% 3,3 win
SFR16 5% 18 £7
SFR16 5% 270 kfi
see Fig. 7
6,3 V 4,7 /iF
180 pF
22 nF
6,3 V 4,7 mF
2x BAS11 and2x BZW03-..
a
4,783 MHz
-
b
7Z89610.A
7Z86486.1
Fig. 5 Allocation of dialling tones to keyboard
functions.
Fig. 6 Polarity-guard and line-transient
suppression bridge D1.
Diodes 2 x BAS11.
Voltage regulators 2 x BZW03-..
DTMF generator for telephone dialling
Vrms ImV)
750 500
;vCl
Rl 1s'
I order
250
20
roups
;i\*
\I V
J
-r 1—
J
filter
(nF)
(k£i) t,5
151,8
2,2
10 2,7 4-4,7
3,3-~ 5 '
6
3,9-4,7--8,25,6 "-TO
8,2 -'-]b
-2 -4 -6 -8 -12
total tone output level fdBm) 7Z86485
Fig. 7 Level adjustment (see Figs 3 and 4).
2nd
order
filter
(nF)
TEA1021
balance
return
loss
~i i
-- I
k_-^—Z L = "
^ t ^ 900!2//30nF
Iv^> -*
II
ir'r
H !
I
.•/,
CCITT Aj -
"f
''// '-^ /f\
A '<v/ / 7. '.
', Y 'sV / / p.b ''
r
f;
''v / /,v. '' // ^^ /v / /,'
' / •V / x/'• //
I
/ / U-< ^'7
^o /
i^
'
Y//X / k\ rV^/;/^I I
frequency (kHz)
balance return loss = 20 loq, n - - dB,0 lz-z
Fig. 8 Balance return loss measured with external components as in Fig. 4.
! '
f~\+
_L _ --
*-
[
- t
II l\ll ll
I .
III JOE II 1n i i i,i I mli III || l l l, ll . kill 1 , ,
1 T" t
1 II 1 i l l
50 f (kHz)
Fig. 9 Frequency spectrum of circuit with second-order filter (see Fig. 4).
-\rMay 1982 107
TEA1021
J VAPPLICATION (see Fig. 4)
Line matching
If there is an impedance match between the lines and the dialling circuit, the balance return loss will be
high and reflections on the line will be highly damped. Figure 8 shows that the balance return loss
when using the application diagram as shown in Fig. 4 is more than 14 dB. The variation of balance
return loss with the frequency is largely caused by an impedance variation due to the low-pass filter
capacitor (C2) and the radio-frequency interference filter capacitor C4. Since the highest line impedance
that is likely to be encountered is 900 ft the internal impedance of the dialling circuit is set at this level
and can be reduced to match lower impedance lines by adding an external resistor between pins 1 and
16. If direct current must be eliminated a capacitor must be connected in series with the resistor.
- internal impedance Zj = 900 ft; no external resistor between pins 1 and 16.
- internal impedance Zj = 600 ft; external resistor between pins 1 and 16 = 2700 ft.
Output level adjustment
The tone output levels are subject to some spread due to manufacturing tolerances and can be adjusted
by selection of the value of the resistor connected to pin 8.
The level of the higher-frequency tone however is always 2 + 0,7 dBabove that of the lower-frequency
tone. The total production of the circuits is therefore divided into groups. The group to which any of
the integrated circuits belongs is identified by dots on the body of the circuit, the number of dots
corresponding with the group number. The combined tone output level is shown as a function of
resistor value with group number as a parameter in Fig. 7. After the resistor value has been selected to
obtain the required tone output level, the value of the filter capacitor connected to the same pin must
be determined. For passive first-order filters (Fig. 4) the time-constant (RC) must be 26 MS. For active
second-order filters it must be 46 ms. These values accommodate the different attenuation levels for
the various tone frequencies due to the 0,3 dB hump at the breakpoint of the filters.
i
(VI
7,5
R
y'
3-
/ '
>-
18
sA!---y
X- y --- -
...._(......
•'-
"T <•
t t Y-R3- Ot-
!
; L>-^ '
: -
' L^" -
125 150!p ImA)
Fig. 10 D.C. characteristics.
108 May 1982^r
DEVELOPMENT SAMPLE DATAThis information is derived from development samples
made available for evaluation. It does not necessarily
imply that the device will go into regular production.
TEA1042
TELEPHONE TRANSMISSION CIRCUIT
FOR HANDSFREE LOUDSPEAKING
GENERAL DESCRIPTION
The TEA1042 is a bipolar integrated circuit performing all speech and line interface functions in
electronic telephone sets. It is especially designed for handsfree loudspeaking equipment.
Its features are:
• Supplied from telephone line current
• Voltage regulator with adjustable d.c. voltage drop and d.c. resistance
• High and low-impedance handset microphone inputs
• High-impedance base microphone input
• Handset/base selection input
• Muting input for pulse or DTMF dialling
• Gain setting facility on all amplifiers
• Line current dependent gain control facility with corrections for the exchange supply voltage and
its feeding bridge resistance
• Supply output for additional circuits.
QUICK REFERENCE DATA
Line voltage at l|j ne = 15 mALine current operating range
Telephone line impedance
Supply current
Voltage gain, transmitting amplifier
MIC1 input
MIC2 input
MIC3 input
DTMF input
Voltage gain, receiving amplifier
Gain adjustment range
transmitting amplifier
receiving amplifier
Range of gain control with line current,
all amplifiers
Exchange supply voltage range
Exchange feeding bridge resistance
Operating ambient temperature range
v line typ. 4,2 V
'line 10 to 140 mA
lz linel nom 600 n
'cc typ. 1 mA
A„d typ. 44,1 dB
Avd typ. 20 dB
Avd typ. 20 dB
Avd typ. 25,6 dB
Avd typ. 27 dB
AAvd typ- + 6 dB
AAvd typ. ± 8 dB
AAvd typ. 6 dB
^exch 24 to 60 V
°exch 400 or 800 fi
-25 to + 70 °C
PACKAGE OUTLINE
24-lead DIL; plastic (SOT-101A).
^rJanuary 1983 109
TEA1042
vcc RX
I 21 I 14
BRDG CX2
I 15 I 13
GAT1 GAT2 RCX
MIC1
REF
MMUTE
CURRENTREFERENCE
CONTROLCURRENT
INTERNALREFERENCE
O
a-.o
~S
Gt>
<
TEA1042
QTEL
QLSP
VEE GAL GAP
23
GALN
Fig. 1 Block diagram. The blocks marked dB are attenuators. The M and MUTE inputs operate
analogue switches that activate or inhibit the inputs and outputs as required by their function.
110 January 1983^r
Telephone transmission circuit for handsfree loudspeaking TEA1042
<Q
UJ
>
LN 1u
24
GAT1 2 23
GAT2 3 22
VEE 4 21
QTEL 5 20
CX1 6 19
TEA1042GAP 7 18
QLSP 8 17
GAL 9 16
MIC1 10 15
REF 11 14
IR 12 13
7288486
Fig. 2 Pinning diagram.
M
BRDG
RX
CX2
PINNING
1 LN positive line terminal
2 GAT1 gain adjustment; transmitting
amplifier
3 GAT2 gain adjustment; transmitting
amplifier
4 Vf£f£ negative line terminal
5 QTEL handset telephone output
6 CX1 reference decoupling
7 GAP gain adjustment; telephone
amplifier
8 QLSP loudspeaker preamplifier output
9 GAL gain adjustment; loudspeaker
preamplifier
low-impedance handset microphone input
reference voltage
receiving amplifier input
external stabilizing capacitor
14 RX external resistor
15 BRDG selection input for gain control adaptation
to feeding bridge impedance
16 M mode (handset/base selection) input
17 MUTE mute input
18 MIC2 high-impedance handset microphone input
19 MIC3 base microphone input
20 DTMF dual-tone multi-frequency input
21 Vqc positive supply
22 RCX line voltage adjustment and voiiage
regulator decoupling
23 GALN gain control with line current,
all amplifiers
24 RA d.c. resistance adjustment
RA
GALN
RCX
VCC
DTMF
MIC3
M,C21 ° MIC1
11 REF
MUTE 12 IR
13 CX2
~\rJanuary 1983 111
TEA1042
FUNCTIONAL DESCRIPTION
The TEA1042 contains two receiving amplifiers, a transmitting amplifier, means to switch the inputs
and the outputs, means to adjust the gain of al I amplifiers individually, means to vary the gain with the
line current and means to adjust the d.c. voltage drop and d.c. resistance. See the block diagram, Fig. 1.
Supply: LN, Vcc , VEE , RA, CX1 and CX2 (pins 1, 21,4, 24,6 and 13)
The circuit is supplied from the line current, the arrangement is shown in Fig. 3. The circuit develops
its own supply voltage at Vqq (pin 21 ). This supply voltage may also be used to supply an external
circuit, e.g. a CMOS pulse or DTMF dialler or an electret microphone amplifier stage. The current
available for this circuit depends on external components, see Fig. 4.
All line current has to flow through the circuit. If the line current exceeds the current required by the
circuit itself via Vcc (pin 21), i.e. about 1 mA, plus the current required by the peripheral circuits
connected to this pin, then the excess current is diverted via LN, the positive line terminal (pin 1 ),
to RA (d.c. resistance adjustment; pin 24).
The minimum line voltage may be chosen by external resistor R5 and the variation with line current
by external resistor R10. The circuit regulates the line voltage at TamD = 25 °C to:
V| ine = V LN = ^j^x 0,62 + l LN x RIO,
1 1_|\|being the current diverted via LN.
A regulator decoupling capacitor has to be connected between RCX (pin 22)and Vgg, the negative
line terminal (pin 4), a smoothing capacitor has to be connected between Vcc (pin 21)and Vg^, anda stabilizing capacitor between CX2 (pin 13) and V^E- Further a decoupling capacitor has to be
connected between CXI (reference decoupling; pin 6) and Vgg (pin 4).
The dynamic impedance that the circuit presents to the line in the speech band is determined primarily
by resistor R1 connected between LN (pin 1) and Vcc (P' n 21).
Mode (handset/base selection) input M (pin 16)
The mode input permits selection of operation via the handset or via the base. A HIGH level on the Minput or an open circuit selects handset operation, i.e. it activates the microphone inputs MIC1 andIV1IC2 and the handset telephone output QTEL. A LOW level on M selects the base microphone input
MIC3 and the loudspeaker preamplifier output QLSP.
Microphone inputs MIC1, MIC2and MIC3 (pins 10, 18 and 19)
Handset and base may be equipped with a sensitive microphone, e.g. an electret microphone with pre-
amplifier. This has to be connected to the MIC2 or MIC3 input respectively. The available gain fromthese inputs is typ. 20 dB.
The handset may also be equipped with an insensitive low-impedance microphone, e.g. a dynamic or
magnetic microphone. This has to be connected between MIC1 (pin 10) and (REF (pin 11). The available
gain from this input is typ. 44,1 dB.
Dual-tone multi-frequency input DTMF and mute input MUTE (pins 20 and 17)
A HIGH level on the MUTE input inhibits all microphone inputs and the telephone and loudspeaker
outputs QTEL and QLSP and enables the DTMF input, a LOW level does the reverse. Switching the
MUTE input will not produce any clicks on the line or in the telephone or loudspeaker. The available
gain from the DTMF input is typ. 25,6 dB.
112 January 1983
Telephone transmission circuit for handsfree loudspeaking TEA1042
Telephone output QTEL and loudspeaker preamplifier output QLSP (pins 5 and 8)
As described before, the M input determines which of the outputs QTEL and QLSP will beactivated. The receiving amplifier input I R (pin 1 2) is the input for both outputs. For both outputs theavailable gain is typ. 27 dB. The output QTEL is intended for telephone capsules with an impedance of150 Q. or more. The QLSP output is intended to drive a power amplifier. Its output impedance is less
than 1 kn.
<Qw_iQ.
S<I-zLU
a.
O_iLU
>UJ
Q
Gain adjustment: GAT1, GAT2, GAP and GAL (pins 2, 3, 7 and 9)
The gain of the transmitting amplifier may be adjusted by an external resistor R2 connected betweenGAT1 and GAT2 (pins 2 and 3; see Fig. 9). This adjustment influences the sensitivity of the inputsMIC1, MIC2, MIC3and DTMF to the same amount. The gain is proportional to R2and inverselyproportional to R10and R12.
The gain of the telephone amplifier may be adjusted by an external resistor R14 between GAP (pin 7)and CX1 (pin 6). The gain is proportional to R 74 and inversely proportional to R12.
The gain of the loudspeaker preamplifier may be adjusted by an external resistor R13 between GAL(pin 9) and CX1 (pin 6). The gain is proportional to R13and inversely proportional to R12.
Gain control with line current: GALN (pin 23)
The circuit offers a facility to automatically vary the gain of all its amplifiers with the line current. In
this way the circuit compensates for differences in line attenuation. The variation is accomplished byconnecting an external resistor R11 between GALN (pin 23)andVEE (pin 4). The value of this resistorshould be chosen in accordance with the supply voltage of the exchange (see Figs 5 and 6).
If no gain variation with line current is required the GALN connection may be left open. All amplifiershave their maximum gain then.
Selection input for gain control adaptation to feeding bridge impedance: BRDG (pin 15)
A LOW level at the BRDG input optimizes the gain control characteristics of the circuit for a 400 £1feeding bridge in the exchange, a HIGH level for 800 n.
Side tone suppression
In the circuit diagram shown in Fig. 9 side tone suppression is obtained with components C2, R3, R4,R7 and R8. Their component values have to be chosen to suit the cable type used. This networkattenuates the signal from the telephone line to the I R input of the receiving amplifier. This attenuationmay be adjusted by choosing the value of R7 without affecting the side tone suppression.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply current
'lined.c.
non-repetitive (t < 100 h)
Storage temperature range
Operating ambient temperature range
Junction temperature
'line
Tstg
Tamb
max. 140 mAmax. 250 mA-40 to +125 °C
-25 to +70 °C
max. 150 °C
January 1983 113
TEA1042
CHARACTERISTICS
l| ine= 10 to 140 mA; f = 1000 Hz; TamD = 25 °C, unless otherwise specified.
parameter symbol min. typ. max. unit
Supply: LN and Vqc (pins 1 and 21)
Line voltage
l|ine= 15mAl|j ne = 50 mAl| ine
= 100 mA
v line
v line
v line
4 4,2 4,4
5,8
7,3
VVV
Variation with temperature -AV| ine/AT 8 10 12 mV/K
Line current operating rage 'line10 - 140 mA
Supply current at Vqq = 2 V 'cc— — 1 mA
Mode (handset/base selection) input M (pin 16)
Input voltage
HIGH level
LOW level
V|HV| L
1- vCc
0,2
VV
Input current -he - 8 20 HA
Attenuation of non-selected signals -AAvd 45 — ~ dB
Low-impedance handset microphone input MIC1 and reference voltage pin REF (pins 10and 1 1)
Input impedance l
z 10-1ll - 3 - kn
Voltage gain, see Fig. 7 Avd 43,1 44,1 45,1 dB
High-impedance handset microphone input MIC2 (pin 18)
Input impedance IZ18-4I 40 48 - kH
Voltage gain, see Fig. 7 Avd 19 20 21 dB
Base microphone input MIC3 (pin 19)
Input impedance |Z 19-41 40 48 - kf2
Voltage gain, see Fig. 7 Avd 19 20 21 dB
DTMF input (pin 20)
Input impedancel
z 20-4l 10 15 - kil
Voltage gain, see Fig. 7 Avd 24,6 25,6 26,6 dB
Gain adjustment pins; transmitting amplifier: GAT1 and GAT2 (pins 2 and 3)
Gain adjustment range AAvd- ±6 - dB
Gain variation with frequency,
f = 300 to 4000 Hz AAvd- ±0,5 — dB
Gain variation with temperature at
l| ine= 50 mA; Tarnb = -5 to +45 °C AAvd ±0,5 dB
114 January 1983~\r
Telephone transmission circuit for handsfree loudspeaking TEA1042
CHARACTERISTICS (continued)
parameter
<t-
<Q
5<HZUJ
5
>UJQ
Transmitting amplifier output Ll\l (pin 1)
Output voltage at l|jne = 1 5 mA; R|
j
ne = 600 fi; d = 2%
Psophometrically weighted* noise output
voltage at l|j ne = 15 mA; R|j ne = 600 fi
MUTE input (pin 17)
Input voltage
HIGH level
LOW level
Input current
Attenuation of non-selected signals
Receiving amplifier input IR (pin 12)
Input impedance
Telephone output QTEL (pin 5)
Voltage gain at l|j ne = 15 mA;R load =150n ; R 13= 15kJ2;see Fig. 8
Gain variation with frequency,
f = 300 to 4000 Hz
Gain variation with temperature at
I
|jne = 50 mA; Tamb = -5 to +45 °C
Maximum output voltage at l|j ne = 15 mA;
R|oad= 150fi;d = 2%
Psophometrically weighted* noise output
voltage at l|j ne= 15 mA
Gain adjustment pin; telephone amplifier: GAP (pin 7
Gain adjustment range
Loudspeaker preamplifier output QLSP (pin 8)
Voltage gain at l|; ne = 15 mA;R load = 10 kft; R14 = 15 kI2; see Fig. 8
Gain variation with frequency,
f = 300 to 4000 Hz
Gain variation with temperature
Psophometrically weighted* noise output
voltage at l|jne = 15 mAOutput impedance
symbol
v LI\l(rms)
v LN(rms)
VlHV|L
-1 17
-AAvd
iZ 12-4l
Avd
AAvd
AAvd
vO(rms)
vO(rms)
AAvd
Avd
AAvd
AAvd
vO(rms)
IZ8-4I
Gain adjustment pin; loudspeaker preamplifier: GAL (pin 9)
Gain adjustment range I AAvd
typ.
1,4
245
45
26
350
0,2
20
10
27 28
±0,5
±0,5
40
27
±0,5
±0,5
40
V
MV
VV
MdB
dB
dB
dB
mV
KV
dB
dB
dB
dB
kn
dB
^rJanuary 1983 115
TEA1042
CHARACTERISTICS (continued)
parameter symbol min. typ. max. unit
Selection input for gain control adaptation to feeding bridge impedance BRDG (pin 15)
Input voltage
HIGH level
LOW level
V| HV| L
1 - vCc0,2
VV
Input current —lis - 8 20 MA
Gain control with line current pin GALIM (pin 23)
Gain control range AAvd- 6 - dB
Highest line current for maximum gain,
R11 = 105 kJ2;
BRDG = HIGH (R exch = 800 £2)
BRDG=LOW (R exch = 400£2)'line
'line
22,5
31,5
25
35
27,5
38,5
mAmA
Lowest line current for minimum gain,
R11 = 105 kfi;
BRDG = HIGH (R exch = 800 S2)
BRDG = LOW (R excn = 400i2)'line
'line
49,5
81
55
90
60,5
99
mAmA
* P53 curve.
116 January 1983^r
Telephone transmission circuit for handsfree loudspeaking
<Q
2<
ui
5
TEA1042
'line R1I 1
'p
R5
R9
1 21
+
' * 1
RCX CX1
LN VCC
RA CX2 VEE A
jphone
line
22
+
6
2C6
24
R10
r
13
:C5
4 peripheral
circuit
] C4S 2C9
1 ,_ _j
7Z88493
Fig. 3 Supply arrangement.
'P
(mA)
1-
R5= 11
Tamb = 55°CR9 = 20k£2
on5 to 120mA
Okfl
1
7Z88492
Fig. 4 Maximum current l
pavailable from VqC for external (peripheral) circuits.
2 3 4
VCC (V)
^rJanuary 1983 117
TEA1042
(dB)
7Z88501
R11 = ==
'
*|
\2 \
4
exch )24V 1 36 V \48V v60V
-6
=111 - 147 k a \75kSJ^
,105kS2 ,140 kSJ
-24V
36V
48 V
60V
10
543 2
20 30 40
1 line length (km)
5 4 3 2 1
5 4 3 2
Fig. 5 Gain variation with line current, with R1 1 as a parameter, and with the BRDG input HIGH, i.e.
the circuit optimized for 800 H. The values chosen for P1 1 suit the usual values for the supply voltage
of the exchange. The curves are valid for 0,5 mm twisted-pair cables with an attenuation of 1,2 dB/km
and a d.c. resistance of 176 H/km.
&A VC
(dB)
7288502
R11 ==°
2
4
ve xch
124V 36V 48V .60 V
6
R11V kn \75 kS2 \1C 5kS2 140kn
20 40 60 80
54 3 2 1 line length (km),= 24V i . . i
i i
5 4 3 2 1
36 V ,_. i i i i
48 V
60V
5 4 3 1
Fig. 6 Gain variation with line current, with R11 as a parameter, and with the BRDG input LOW, i.e.
the circuit optimized for 400 Q. The values chosen for R11 suit the usual values for the supply voltage
of the exchange. The curves are valid for 0,5 mm twisted-pair cables with an attenuation of 1 ,2 dB/km
and a d.c. resistance of 176 fi/km.
118 January 1983~\r
Telephone transmission circuit for handsfree loudspeaking TEA1042
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<V)
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£ c ™
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CN _i 5p- ii 4^ *j
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January 1983 119
TEA1042
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120 January 1983^r
Telephone transmission circuit for handsfree loudspeaking TEA1042
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ArJanuary 1983 121
TEA1043
DTMF GENERATOR FOR TELEPHONE DIALLING
This integrated circuit is a dual-tone multi-frequency (DTMF) generator, supplying frequency combina-tions (in accordance with CCITT recommendations) for use in pushbutton telephones, with a single
contact keyboard.
The various frequencies are derived from a crystal-controlled oscillator followed by a sinewave
synthesizer.
I
2 L technology allows digital and analogue functions to be implemented on the same chip. The built
in current/voltage regulator and active output amplifier substantially reduce the number of external
components. Only a quartz crystal of 4,78 MHz and a few resistors and capacitors are required.
The circuit features:
- wide operating line current range
- operating voltage down to 1,3 volt (standby 0,7 volt)
- no individual tone level adjustment required
- temperature stabilized signal levels
- line current independent signal levels
- output stage and line regulator included
- all pins protected against electrostatic discharges
- two key roll-over provided
- operates with a low cost quartz crystal
- few external components required
- electronic mute facility
- low power consumption in standby mode
OSCIL-
LATORCURRENTSTABILIZER
TEA1043 LINE
REGULATOR
1L
-4
,56
z
- Jt
L - ' 1 ~V
PROGRAMMABLEDIVIDER
1209. . 1633Hz
PROGRAMMABLEDIVIDER
697 .941 Hz
COUNTER
COUNTER
DIGITAL TOANALOGUECONVERTER
DIGITAL TOANALOGUECONVERTER
KEYBOARD LOGIC >
X X, X 2 X 3 Y Y, Y2 Y3 DAC
PACKAGE OUTLINES
TEA1043P: 16-lead DIL, plastic (SOT-38).
TEA1043D: 16-lead DIL, ceramic (SOT-74B).
ACTIVE
OUTPUT STAGE
Fig. 1 Block diagram (dotted
lines are stabilized supply rails).
~\rMay 1982 123
TEA1043
RATINGSLimiting values in accordance with the Absolute Maximum System (IEC 134)
Supply current lp max. 150 mA
Surge current (tp< 250 us)
l s max. 850 mA
Input series resistance Rs
min. 18 a
Operating ambient temperature range Tamb -25 to +70 oc
Storage temperature range Tstg-55 to +125 °C
Junction temperature Tj max. 125 °C
CHARACTERISTICS
Vm = V; Tamb = -25 to +70 °C unless otherwise speci fied,
symbol min. typ. max. unit conditions
operating voltage
d.c.;-l|_ = 10 mA v L 2,8 3,3 3,8 V
line current
level - 7 dBm lL 10 8 120 mAlevel - 2 dBm lL 12 9 120 mAstandby mode 'L
- 50 - MA
internal impedance A 640 900 1150 a 300 - 3400 Hz
tone frequencies
low fx0- 697 - Hz
fx1— 770 — Hz
fx2— 852 - Hz frequency
fx3 - 941 - Hz quartz crystal 4 782 720 Hz
high fy0- 1209 - Hz
fyify2fY3
— 1336 — Hz
- 1477 - Hz
- 1633 - Hz=dividing error
- - 0,11 %^^mh;^^ nom. output level^~~
lower freq. V LG- - -6 dBm adjustable
higher freq. vH g- - -4 dBm adjustable
tolerance on output level AV 2 - 2 dB
pre-emphasis 1,3 2 2,7 dB without filter components
distortion with respect to
total level dtot— -34 -24 dB maximum tone level and
with first-order filter
start up time ts- 5 - ms with recommended
external components
mute output sink current 'MS- - 0,5 mA
switch bounce elimination tsb 1 1,5 2 ms
required keyboard
resistance
contact on R k on- - 10 kSl
contact off R koff 500 k&
124 May 1982^\r
DTMF generator for telephone dialling TEA1043
;v
vn[T u TjT] vp
Fo[I jj]vF
Xi[T h]y 2
x2 [T
MUTE [~iT
TEA10432U Y
3
XaQTil]
Yo
xo[Z To] osc
F>[Z T] DAC
PINNING
1
2
3
FoX1
4 X25 MUTE6 X37 XO8 Fi
9 DAC10 OSC11 Y012 Y1
13 Y314 Y215 v F
Fig. 2 Pin designation. 16 Vp
negative supply
filter output
row keyboard input 1
row keyboard input 2
mute output
row keyboard input 3
row keyboard input
filter input/ input audio
amplifier
output DAC/DTMF tones
oscillator input
column keyboard input
column keyboard input 1
column keyboard input 3
column keyboard input 2
input low-pass filter
positive supply
Fig. 3 Application diagram with first order filter.
R1 metal film resistor
R2 metal film resistor
R3 metal film resistor
R5 metal film resistor
C1 metallized polyester film capacitor
C2 solid aluminium electrolytic capacitors
D1 polarity guard and transient suppressor
bridge (see Fig. 6)
X1 quartz crystal
th first or<ier filter. keyboard 7ZS4835.1
MR16 1% see Fig. 7
SFR16 5% 3,3 Mf2
SFR16 5% 18fi
SFR16 5% 2700 a (for Z = 600 fi;
no resistor for Z = 900 i
see Fig. 7
6,3 V 4,7 /jF
2x BAS11 and 2 x BZW03-4,783 MHz
May 1982 125
TEA1043
line =±=C4
tf
i>P i/i
tr
A/4 A/S A/6 A
Mr
MrMr
keyboard 7Z84B36.1
Fig. 4 Application diagram with electronic mute switch and second-order filter.
R1
R2R3R4R6R7
R8CI
C2C3C4D1
D2
metal film resistor
metal film resistor
metal film resistor
metal film resistor
metal film resistor
metal film resistor
metal film resistor
metallized polyester film capacitor
solid aluminium electrolytic capacitor
miniature ceramic plate capacitor
metallized polyester film capacitor
MR16 1%
SFR16 5%SFR16 5%SFR16 5%SFR16 5%
SFR16 5%SFR16 5%
6,3 V
see Fig. 7
3,3 win
39 kQ, (depends on audio voltage)
270 kft
330 kH820 kSi
470 kJ2
see Fig. 7
4,7 mF
180 pF
22 nF
transient suppressor bridge (see Fig. 6) 2 x BAS1 1 and 2 x BZW03
diode BAW62
TR1 transistor BC338
TR2 transistor BC548
TR3 transistor BC558
TR4 transistor BC328
X1 quartz crystal 4,783 MHz
lfTR1/TR2=BSR50andTR3/TR4 = BSR60then R6 = 39 kJ2, R7 = 120kfland R8 = 33 k«.
An additional choke of 1 5 mH in series with the circuit is required to meet the CEPT CS203
distortion requirements.
126 May 1982
\^
DTMF generator for telephone dialling TEA1043
Y0" Y.= Y2= Y
3=
1209 1336 1477 1633Hz Hz Hz Hz
1|
X Q = 697 Hz 1 -hh 3 4.4X, = 77QH7 4 5 6 B
7 8 9 C
* # D
7Z86486 1
Fig. 5 Allocation of dialling tones to
keyboard functions.
ci
Vrms Ml (
" J --
750 500 2501
. II"
s ^1' _[~
-,
1 V'—
.... -X-
-A 1
(nF20
(kill ,, 5
151.8
2,2
10 2.;
3,3-
order
filter
(nF)
-2 -4 -6 -8 -12
total tone output level idBm)
Fig. 6 Polarity-guard and line-transient
suppression bridge D1. Diodes 2 x BASILVoltage regulators 2 x BZW03-.
30
balance
fdB)
20
! | i
!
j
1
'
ji
; "
' i~ \ ~ --
1i i
u__i
[i
-^"^ 7-L-iW 900S2//30nF
r^ L 1'
!
\
£N
600 n// CCITT
. ///,'XffiA
v^V/4w,>
O''
'
X A/vyxAA/ / i"< Av y ,
//Vx/.xV\/ /// A/////// X YX XX'X V vX X X'.Xy y/x //X//-/\-\
/y'/ %//
iX/ / 'X '
'
X \
frequency (kHz)
balance return loss = 20 [og..z + z
Fig. 7 Level adjustment
(see Figs 3 and 4).
Fig. 8 Balance return loss measured
with externa! components as in Fig. 4.
m1 j
i
!
;l
I
i
|
-
j
'
:
!
!
|
'
! II:
i j
i
j
: ..j-i:
_'
:
!i
1 !
-40 :
1
; _^ j
1 ill'__: i
i i
fjjl Jii
ill '
;
titty i
i
t|
;
-80i Ititi Ililifl 1 jLlill, 111 i il
.^
t
, .llill 1 , .1 !
: \
inn 1 M !M
[i ! | T
1i
1 1 1
Fig. 9 Frequency spectrum of circuit with second order filter (see Fig. 4).
May 1982 127
TEA1043
APPLICATION (see Fig. 4)
Line matching
If there is an impedance match between the lines and the dialling circuit, the balance return loss will be
high and reflections on the line will be highly damped. Figure 8 shows that the balance return loss when
using the application diagram as shown in Fig. 4 is more than 14 dB. The variation of balance return
loss with the frequency is largely caused by an impedance variation due to the low-pass filter capacitor
(C2) and the radio-frequency interference filter capacitor C4. Since the highest line impedance that is
likely to be encountered is 900 £2 the internal impedance of the dialling circuit is set at this level and
can be reduced to match lower impedance lines by adding an external resistor between pins 1 and 16.
If direct current must be eliminated a capacitor must be connected in series with; the resistor.
- internal impedance Zj = 900 12; no external resistor between pins 1 and 16.
- internal impedance Zj = 600 £2; external resistor between pins 1 and 16 = 2700 12.
Output level adjustment
The tone output levels are subject to some spread due to manufacturing tolerances and can be adjusted
by selection of the value of the resistor connected to pin 8.
The level of the higher-frequency tone however is always 2 ± 0,7 dB above that of the lower-frequency
tone. The total production of the circuits is therefore divided into groups. The group to which any of
the integrated circuits belongs is identified by dots on the body of the circuit, the number of dots
corresponding with the group number. The combined tone output level is shown as a function of
resistor value with group number as a parameter in Fig. 7. After the resistor value has been selected to
obtain the required tone output level, the value of the filter capacitor connected to the same pin must
be determined. For passive first-order filters (Fig. 4) the time-constant (RC) must be 26 ms. For active
second-order filters it must be 46 us. These values accommodate the different attenuation levels for the
various tone frequencies due to the 0,3 dB hump at the breakpoint of the filters.
7ZB4839 1
1!
1
;
1
S| -'r*
s '
Sip
^T(V) '
'
.. X—*--1!
ii
:
\ i^_J___i
i
'f\ ;
-4 -I < ^R3 = V-— '
s
;
-^ "
\
t ,
' —f-—
Lj^ !,
- --1-—
^TTT- i i !I
Fig. 10 D.C. characteristics.
128 May 1982~\r
TEA1044
DTMF GENERATOR FOR TELEPHONE DIALLING
This integrated circuit is a dual-tone multi-frequency (DTMF) generator, supplying frequency
combinations (in accordance with CCITT recommendations) for use in pushbutton telephones, with a
single contact keyboard.
The various frequencies are derived from a crystal-controlled oscillator followed by a sinewave
synthesizer.
I
2 L technology allows digital and analogue functions to be implemented on the same chip. The built
in current/voltage regulator and active output amplifier substantially reduce the number of external
components. Only a quartz crystal of 4,78 MHz and a few resistors and capacitors are required.
The circuit features:
— wide operating line current range
— operating voltage down to 1 ,3 volt (standby 0,7 volt)
— no individual tone level adjustment required
— temperature stabilized signal levels
— line current independent signal levels
— output stage and line regulator included
— all pins protected against electrostatic discharges
— two key roll-over provided
— operates with a low cost quartz crystal
— few external components required
— electronic mute facility
— adjustable impedance— low power consumption in standby mode
OSCIL-
LATORCURRENTSTABILIZER
TEA1044 LINE
REGULATOR
398,56
kHz
_L_PROGRAMMABLE
DIVIDER
1209 . 1633Hz
PROGRAMMABLEDIVIDER
697 . 941 Hz
DIGITAL TOANALOGUECONVERTER
DIGITAL TOANALOGUECONVERTER
KEYBOARD LOGIC
13 14 16 15
An A 1 An A o
> ACTIVE
OUTPUT STAGE
Fig. 1 Block diagram (dotted lines are stabilized supply rails).
PACKAGE OUTLINES
TEA1044P: 18-lead DIL, plastic (SOT-102A).
TEA1044D: 18-lead DIL, ceramic (SOT-133).
~^r May 1982 129
TEA1044
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply current 'P
Surge current (tp< 250 us) 'S
Input series resistance "s
Operating ambient temperature range
Storage temperature range
Junction temperature
CHARACTERISTICS
VN =0V; Tam b= -25 to + 70 °C unless otherwise specified.
Tamb
Tstg
max. 150 mA
max. 850 mAmin. 18 fi
-25 to +70 °C
-55 to + 125 °C
max. 125 °C
symbol min. typ. max. unit conditions
operating voltage d.c;
-l L = 10mA v L 2,8 3,3 3,8 V
i
line current
level — 7 dBmlevel - 2 dBm l|_
10
12
8
9
120
120
mAmA
standby current "LS- 50 iuA
internal impedance Zi 640 900 1150 n 300 - 3400 Hz
tone frequencies
low fx0fx1
- 697
770
Hz
Hz
I
high
fx2
fx3
fyO
Jy1fy2fy3
"852
941
1209
1336
1477
1633
— Hz i
Hz
Hz
Hz
Hz
Hz
frequency
quartz crystal
4 782 720-Hz
H^^dividing error - - 0,11 %
nom. output level
lower frequency
higher frequency
vlgvhg
- -6-4
dBmdBm
adjustable
adjustable
tolerance on output level av 2 - 2 dB
pre-emphasU 1,3 2 2,7 dB without filter component.:
distortion with respect to
total level dtot- -34 -24 dB maximum tone level and
with first-order filter
start up time u - 5 - ms with recommended
external components
mute output sink current 'ms- - 0,5 mA
switch bounce elimination tsb 1 1,5 2 ms
required keyboard
resistance
contact on
contact off
R konR koff 500
- 10 kil
ktt
130 May 1982~\r
DTMF generator for telephone dialling TEA1044
V»E uJ8]Vp
F
°S77] v F
x,[TJ6]
Y2
x2 nr 13 ^3
MUTE [T" TEA1044 77] V.
zsQ[ J£]Yo
X 3 [I Ti~[ osc
XoQT 77) OSC/tvS
f,|T 77j DAC
Fig. 2 Pin designation.
PINNING
1 vN negative supply
2 Fo filter output
3 X1 row keyboard input 1
4 X2 row keyboard input 2
5 MUTE mute output
6 zs impedance setting
7 X3 row keyboard input 3
8 XO row keyboard input
9 Fi filter input/input audio amplifier
10 DAC output DAC/DTMF tones
11 OSC/IMS oscillator/noise suppression output
12 OSC oscillator input
13 Y0 column keyboard input
14 Y1 column keyboard input 1
15 Y3 column keyboard input 3
16 Y2 column keyboard input 2
17 v F input low-pass filter
18 V P positive supply
941 Hz
keyboard
Fig. 3 Application diagram with first-order filter.
R1 metal film resistor
R2 metal film resistor
R3 metal film resistor
R5 metal film resistor
C1 metallized polyester film capacitor
C2 solid aluminium electrolytic capacitor
D1 polarity quard and
transient suppressor bridge (see Fig. 6)
X1 quartz crystal
MR16 1% see Fig. 7
SFR16 5% 3,3 w\n
SFR16 5% 18 fi
SFR16 5% 240 il (for Z = 600 fi)
no resistor for Z = 900 12
see Fig. 7
6,3 V 4,7 aiF
2x BAS11 and2x BZW034,783 MHz
^rMay 1982 131
TEA1044
Fig. 4 Application diagram with electronic mute switch and second order filter (meets CEPT CS203
requirements).
R1
R2R3
R4R5
C1
C2
C3
C4
C5
D1
D2TR1/TR2TR3/TR4X1
metal film resistor
metal film resistor
metal film resistor
metal film resistor
metal film resistor
MR16SFR16SFR16
SFR16SFR16
metallized polyester film capacitor
solid aluminium electrolytic capacitor
miniature ceramic plate capacitor
metallized polyester film capacitor
solid aluminium electrolytic capacitor
transient suppressor bridge (see Fig. 6)
diode BAW62transistors BC338/BC548
transistors BC558/BC328
quartz crystal
1% see Fig. 7
5% 3,3 Mn5% 39 kQ (depends on audio
voltage)
5% 270 ktt
5% 240 n (for Z = 600 S2;
no resistor for Z = 900 £2)
see Fig. 7
6,3 V 4,7 mF180 pF
22 nF
6,3 V 4,7 a;F
2x BAS11 and 2 x BZW03-.
4,783 MHz
If TR1/TR2 = BSR50 and TR3/TR4 = BSR60 then R6 = 39 kfi, R7 = 120kftand R8 = 33 kn
132 May 1982r
DTMF generator for telephone dialling TEA1044
'0- r1= Y 2 = Y3
=
1209 1336 1477 1633Hz Hz Hz Hz
X = 697 Hz 1
X,-852Hz
7Z86486.'
Fig. 5 Allocation of dialling tones
to keyboard functions.
Fig. 6 Polarity-guard and line-transient
suppression bridge D1. Diodes 2 x BAS11.Voltage regulators 2 x BZW03-..
Vrm . (mVI
750 500 250
^,s
S>
sS luui
. IM
I V>
-
-2 -4 -6 -8 -12
lotdl lone output level (dBm]
R1 1"
4ordei
filter
(nFI20
kUI , 5
2nd
order
filter
(nF)
-8,2
5.6 — 10
frequency (kHz)
balance return loss = 20log10 Z-Z ;
Fig. 7 Level adjustment (see Figs 3 and 4). Fig. 8 Balance return loss measured with
external components as in Fig. 4.
m *-' 4i
i
!
! !
i
i|
<
i
i
i.
"
4J ^T -L 1.1
r
t
'
.'_
1 l l ^~
111i_|lf jL
iii,
1'i
iJiii Mill 1 ill III III i.il it. j . J ,,..,.., i ill I
inn I i ! i !
50 f (kHz)
Fig. 9 Frequency spectrum of circuit with second-order filter (see Fig. 4).
^rMay 1982 133
TEA1044
APPLICATION (see Fig. 4)
Line matching
If there is an impedance match between the lines and the dialling circuit, the balance return loss will be
high and reflections on the line will be highly damped. Figure 8 shows that the balance return loss when
using the application diagram as shown in Fig. 4 is more than 14 dB. The variation of balance return
loss with the frequency is largely caused by an impedance variation due to the low-pass filter capacitor
(C2) and the radio-frequency interference filter capacitor C4. Since the highest line impedance that is
likely to be encountered is 900 Q the internal impedance of the dialling circuit is set at this level and
can be reduced to match lower impedance lines by adding an external resistor between pins 1 and 6.
— internal impedance Z\ = 900 H; no external resistor between pins 1 and 6.
- internal impedance Zj = 600 £2; external resistor between pins 1 and 6 = 240 Q..
Output level adjustment
The tone output levels are subject to some spread due to manufacturing tolerances and can be adjusted
by selection of the value of the resistor connected to pin 8.
The level of the higher-frequency tone however is always 2 ± 0,7 dB above that of the lower-frequency
tone. The total production of the circuits is therefore divided into groups. The group to which any of
the integrated circuits belongs is identified by dots on the body of the circuit, the number of dots
corresponding with the group number. The combined tone output level is shown as a function of
resistor value with group number as a parameter in Fig. 7. After the resistor value has been selected to
obtain the required tone output level, the value of the filter capacitor connected to the same pin must
be determined. For passive first-order filters (Fig. 4) the time-constant (RC) must be 26 ms. For active
second-order filters it must be 46 ;us. These values accommodate the different attenuation levels for the
various tone frequencies due to the 0,3 dB hump at the breakpoint of the filters.
Vp
(V)
j
" !
[ !' '
- 4- - — ,»•^LVL-
R j= s
H-*-i 18 s>
/'
---!-* k-
J^U-?usr-
^j ^><^r","
> *^\ I irt *
j
+ ~
1
*^ _..
-y't
Mi i
125 150IplmAI
Fig. 10 D.C. characteristics.
134 May 1982~\r
DEVELOPMENT SAMPLE DATAThis information is derived from development samples
made available for evaluation. It does not necessarily
imply that the device will go into regular production.
TEA1046
DTMF/SPEECH TRANSMISSION INTEGRATED CIRCUIT
FOR TELEPHONE APPLICATIONS
This integrated circuit is a dual-tone multi-frequency (DTMF) generator and a speech transmissioncircuit on a single chip. It supplies frequency combinations in accordance with CCITT recommendationsfor use in pushbutton telephones. It can be operated with a single contact keyboard or via a directinterface with a microcomputer. I
2 L technology allows digital and analogue functions to be implement-ed on the same chip.
The speech-transmission part incorporates microphone and telephone amplifiers, anti-side tone and line
adaption. The microphone inputs, suitable for different types of transducers, are purely symmetricalto allow long cable connections with good immunity against radio-frequency interferences.The logic inputs contain an interface circuit to guarantee well-defined states and on and off resistanceof the keyboard.
The circuit features:
- stabilized DTMF levels to be set externally
- wide operating range of line current and temperature- no individual DTMF level adjustments required
— microcomputer compatible logic inputs
— gain setting for microphone and receiver amplifiers
- internally generated electronic muting— low spreads on amplifier gains
— low number of external components
QUICK REFERENCE DATA
Line voltage
Line current
Adjustable dynamic resistance
Microphone signal amplification
Telephone signal amplification
DTMF tone levels (adjustable)
lower frequency
higher frequency
Operating temperature range
v L typ. 4,8 V
"l 10 to 140 mA
Ri 600 to 900 n
am typ. 50 dB
at typ. 20 dB
Vlq max. -6 dBV^|q max. —4 dB
Tamb -25 to + 85 °C
PACKAGE OUTLINES
TEA1046P: 24-lead DIL, plastic (SOT-101).
TEA1046D: 24-lead DIL, ceramic (SOT-149)
^rFebruary 1983 135
TEA1046
C0L2
C0L1
OSCIL-LATOR
MICROPHONEAMPLIFIER
>V-fvH<
TEA1046
*" 14
SCALERDAC
|
DTMFREF.
ACTIVEBUFFER OUTPUT STAGE [J-
> ~ >£D~D> Ti
REGULATOR
9^
3 6
TELEPHONEAMPLIFIER
vs
2
Fig. 1 Functional block diagram.
136 February 1983
DEVELOPMENT SAMPLE DATAThis information is derived from development samples
made available for evaluation, ft does not necessarily
imply. that the device will go into regular production.
TEA1053TEA1054
TELEPHONE TRANSMISSION CIRCUIT
GENERAL DESCRIPTION
The TEA1053 and TEA1054 are bipolar integrated circuits performing all speech and line interfacefunctions in electronic telephone sets.
Their features are:
• Supplied from telephone line current
• Voltage regulator with adjustable d.c. voltage drop and d.c. resistance
• Low-impedance microphone input
• Muting input for pulse or DTMF dialling
• Gain setting facility on all amplifiers
• Line current dependent gain control facility with corrections for the exchange supply voltage• Supply output for additional circuits
QUICK REFERENCE DATA
Line voltage at li: 15 mA
Line current operating range
Telephone line impedance
Supply current
Voltage gain, transmitting amplifier
MIC input
DTMF input
Voltage gain, receiving amplifier
Gain adjustment range
transmitting amplifier
receiving amplifier
Range of gain control with line current,
all amplifiers
Exchange supply voltage range
Exchange feeding bridge resistance
TEA1053
TEA1054
Operating ambient temperature range
v line typ. 4,2 V
'line 10 to 140 mA
l
z line! nom. 600 a
'cc typ. 1 mA
Avd typ. 44,1 dB
Avd typ. 25,6 dB
Avd typ. 27 dB
4Avd typ. ±6 dB
AAvd typ. ± 8 dB
AAvd typ. 6 dB
Vexch 24 to 60 V
°exch 800 n
^exch 400 a
^amb -25 to + 70 °c
PACKAGE OUTLINE
TEA1053;TEA1054: 18-lead DIL; plastic (SOT-102A).
October 1982 137
TEA1053TEA1054
MIC
REF
Avcc
|15
CX2
11
CURRENTREFERENCE
GAT1
2
CONTROLCURRENT
a-.o
GAT2 RCX
3 16
Gl>
TEA1053TEA1054
INTERNALREFERENCE
I
6
CX1 VEE
<
Fig. 1 Block diagram. The blocks marked dB are attenuators. The MUTE input operates analogue
switches that activate or inhibit the inputs and outputs as required by the function of the MUTE input.
138 October 1982
Telephone transmission circuit TEA1053TEA1054
<<
UJ
LN 1u 18
GAT1 2 17
GAT2 3 16
VEE 4 15
QTEL 5TEA1053
TEA105414
CX1 6 13
GAR 7 12
MIC 8 11
REF 9 10
RA
GALN
RCX
VCC
DTMF
MUTE
RX
CX2
IR
Fig. 2
7Z88487
Pinning diagram.
PINNING
1 LN2 GAT1
3 GAT2
V E EQTELCX1GAR
8 MIC9 REF10 IR
11 CX212 RX13 MUTE14 DTMF15 VCC16 RCX
17 GALN
18 RA
positive line connection
gain adjustment connection, transmitting
amplifier
gain adjustment connection, transmitting
amplifier
negative line connection
telephone output
reference decoupling connection
gain adjustment connection, receiving
amplifier
microphone input
reference voltage connection
receiving amplifier input
external stabilizing capacitor connection
external resistor connection
mute input
dual-tone multi-frequency input
positive supply connection
line voltage adjustment and voltage regulator
decoupling connection
gain control with line current connection,
all amplifiers
d.c. resistance adjustment connection
^\rOctober 1982 139
TEA1053TEA1054
FUNCTIONAL DESCRIPTION
The TEA1053 and TEA1054 contain a receiving amplifier, a transmitting amplifier, means to switch
the inputs, means to adjust the gain of the amplifiers individually, means to vary the gain with the line
current and means to adjust the d.c. voltage drop and d.c. resistance. See the block diagram, Fig. 1
.
Supply: LN, Vcc , VEE , RA, CX1 and CX2 (pins 1, 15, 4, 18, 6 and 11)
The circuit is supplied from the line current, the arrangement is shown in Fig. 3. The circuit develops
its own supply voltage at Vcc. the positive supply connection, pin 1 5. This supply voltage may also be
used to supply an external circuit, e.g. a CMOS pulse or DTMF dialler. The current available for this
circuit depends on external components, see Fig. 4.
All line current has to flow through the circuit. If the line current exceeds the current required by the
circuit itself via Vcc, P in 15 > '- e - about 1 mA- P lus the current required by the peripheral circuits
connected to this pin, then the excess current is diverted via LN, the positive line connection, pin 1
,
to RA, the d.c. resistance adjustment connection, pin 18.
The minimum line voltage may be chosen by external resistor R5 and the variation with line current by
external resistor R10. The circuit regulates the line current at 25 °C to:
R5+R9Vline = V LN = —Rjf"
x °.62 + 'LN x RIO,
l|_N being the current diverted via LN, the positive line connection.
A regulator decoupling capacitor has to be connected between RCX, pin 16, and V^g, the negative
line connection, pin 4, a smoothing capacitor has to be connected between Vqq, pin 15, and Vr££, and
a stabilizing capacitor between CX2, pin 1 1 and V EE ,pin 4. Further a decoupling capacitor has to be
connected between CXI, the reference decoupling connection, pin 6, and Vgg, pin 4.
The dynamic impedance that the circuit presents to the line in the speech band is determined primarily
by resistor R1 connected between LN, pin 1, and Vcc. P in 15 -
Microphone input MIC (pin 8)
The MIC input has a low input impedance, especially suited for a dynamic or magnetic microphone.
This has to be connected between MIC, pin 8, and REF, pin 9. The available gain is typ. 44,1 dB.
Dual-tone multi-frequency input DTMF and mute input MUTE (pins 14 and 13)
A HIGH level on the MUTE input inhibits the microphone input MIC and the telephone outputs QTELand enables the DTMF input, a LOW level does the reverse. Switching the MUTE input will not produce
any clicks on the line or in the telephone. The available gain from the DTMF input is typ. 25,6 dB.
Receiving amplifier input IR and telephone output QTEL (pins 10 and 5)
The available gain from input IR to output QTEL is typ. 27 dB. The output QTEL is intended for
telephone capsules with an impedance of 1 50 Q. or more.
\r140 October 1982
Telephone transmission circuit
<
TEA1053TEA1054
Gain adjustment connections GAT1, GAT2, and GAR (pins 2, 3 and 7)
The gain of the transmitting amplifier may be adjusted by an external resistor R2 connected betweenGAT1 and GAT2, pins 2 and 3 (see Fig. 9). This adjustment influences the sensitivity of the inputs
MIC and DTMF to the same amount. The gain is proportional to R2 and inversely proportional to
R10and R12.
The gain of the receiving amplifier may be adjusted by an external resistor R14 between GAR, pin 7,
and CX1, pin 6. The gain is proportional to R14 and inversely proportional to R12.
Gain control with line current, GALN connection (pin 17)
The circuit offers a facility to automatically vary the gain of all its amplifiers with the line current. In
this way the circuit compensates for differences in line attenuation. The variation is accomplished byconnecting an external resistor R11 between GALN, pin 17, and Vgr;, pin 4. The value of this resistor
should be chosen in accordance with the supply voltage of the exchange (see Figs 5 and 6).
If no gain variation with line current is required the GALN connection may be left open. All amplifiershave their maximum gain then.
Side tone suppression
In the circuit diagram shown in Fig. 9 side tone suppression is obtained with components C2, R3, R4,R7 and R8. Their component values have to be chosen to suit the cable type used. This networkattenuates the signal from the telephone line to the I R input of the receiving amplifier. This attenuationmay be adjusted by choosing the value of R7 without affecting the side tone suppression.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
Supply current
d.c.
surge, t < 100 h
Storage temperature range
Operating temperature range
Junction temperature
'line max. 140 mA'line max. 250 mATstg -40 to +125 °C
Tamb -25 to +70 °C
Ti
max. 150 °C
~\rOctober 1982 141
TEA1053TEA1054
CHARACTERISTICS
l| ine= 10 to 140 mA; f = 1 kHz; Tamb = 25 °C unless otherwise specified.
Supply, LN and Vgc (Pins 1 and 15 *
Line voltage
l| ine= 15 mA
l|ine= 50mA
l| ine= 100 mA
Variation with temperature
Line current operating range
Supply current at Vcc = 2 V
symbol
v line
Vline
v line
-AV| ine/AT
'line
'CC
typ.
4,2
10
10
Microphone input MIC and reference voltage connection REF (pins 8 and 9)
Input impedance
Voltage gain, see Fig. 7
Gain variation with frequency,
f = 300 to 4000 Hz
Gain variation with temperature at
l| ine= 50mA;Tamb = ~5to+45°C
DTMF input (pin 14)
Input impedance
Voltage gain, see Fig. 7
Gain variation with frequency,
f = 300 to 4000 Hz
Gain variation with temperature at
l| ine= 50mA;Tamb =-5to+45°C
1*8-91
Avd
AAvd
AAvd
1*14-41
Avd
AAvd
AAvd
43,1
10
24,6
3
44,1
±0,5
±0,5
15
25,6
±0,5
±0,5
4,4
5,8
7,3
12
140
1
45,1
26,6
Gain adjustment connections, transmitting amplifier, GAT1 and GAT2 (pins 2 and 3)
Gain adjustment range
Transmitting amplifier output LN (pin 1)
Output voltage at l|; ne = 15 mA; R|j ne = 600 Q.
d = 2%
Psophometrically weighted * noise
output voltage at l|j ne = 15 mA;
R line= 600ft
AAvd
v LN(rms)
v LN(rms)
±6
1.4
V
V
V
mV/K
mA
mA
dB
dB
dB
dB
dB
dB
dB
245 MV
142 October 1982~\r
Telephone transmission circuit TEA1053TEA1054
<
<(/3
>Q
MUTE input (pin 13)
Input voltage
HIGH level
LOW level
Input current
Attenuation of non-selected signals
Receiving amplifier input IR (pin 10)
Input impedance
Telephone output QTEL (pin 5)
Voltage gain at l|j ne = 15 mA;R load
= 150 n; R14 = 7,5k£2;
see Fig. 8
Gain variation with frequency,
f = 300 to 4000 Hz
Gain variation with temperature at
l| ine = 50 mA; Tamb = -5 to +45 °C
Maximum output voltage at l|j ne = 15 mA;R| oad
= 150f2;d = 2%
Psophometrically weighted * noise
output voltage at l|j ne = 15 mA
Gain adjustment connection, receiving amplifier,
Gain adjustment range I
Gain control range
Highest line current for maximum gain,
R11 = 105 kn;TEA1053
TEA1054
Lowest line current for minimum gain,
R11 = 105 kil; TEA1053
TEA1054
symbol
V|H
VlL
-'13
-AAvd
-10-41
Avd
AAvd
AAvd
vO(rms)
vO(rms)
GAR (pin 7)
^Avd
typ. max.
45
26
350
VCC
0,2
8 20
10
27
±0,5
±0,5
40
28
V
V
AiA
dB
ktt
dB
dB
dB
mV
MV
dB
connection GALhJ (pin 17)
AAvd - dB
num gain,
Mine 22,5 25 mA
line 31,5 35,5 38,5 mAum gain,
'line 49,5 55 60 e, mA
'line 81 90 99 mA
P53 curve.
~^rOctober 1982 143
TEA1053TEA1054
) \
'line R1
f' '
'p
1 15
I
LN Vcc
r><R5
R9
r
RCX CX1 RA CX2 VEE
+c
A
telephone 16i
+
6
EC6
18 11
= C5
4 peripheral
circuit
L +C45
?2C9
r
R10
T -J
7Z88494
Fig. 3 Supply arrangement.
1 amb JJ ^
R9 =20kn0J2
5to 120mA
VCC (V)
Fig. 4 Maximum current l
pavailable from Mqq for external (peripheral) circuits.
144 October 1982~\r
<Q
(-
Z
Q-
o
>LiJ
Q
Telephone transmission circuit TEA1053TEA1054
(dBI
7Z88501
R11 -oo
\
\2 \
Vexch "\ 24V Lv \48V y60V
111 =I 47 k 7 \75kJ2 U05kS2 y140kP.
v exch
10 20 30 40
5 4 3 2 1 line length (km)
5 4 3 2 1
60 70
'line (mA >
V„„h = 24V
36 V
48 V
60V
5 4 3 2
Fig. 5 Gain variation with line current for the TEA1053, with R11 as a parameter. The values chosenfor R1 1 suit the usual values for the supply voltage of the exchange. The curves are valid for 0,5 mmtwistedpair cables with an attenuation of 1,2 dB/km and ad.c. resistance of 176 fl/km.
^ Av<
(dB)
7Z88502
1
I
R11 =~
2
I
A
vexch \ 24v \
\
36 V
I,
48 V ..60V
R11 = \47 wn V kit \l( 5kn 140ka
20 40 60
54321 line length (km)
5 4 3 2 1
-24V
120 140
'line <mA >
36 V
8V5 4 1
Fig. 6 Gain variation with line current for the TEA1054, with R11 as a parameter. The values chosen
for R 1 1 suit the usual values for the supply voltage of the exchange. The curves are valid for 0,5 mmtwisted-pair cables with an attenuation of 1,2 dB/km and a d.c. resistance of 176 S2/km.
^rOctober 1982 145
TEA1053TEA1054
01
£
oo<<
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146 October 1982
/^
Telephone transmission circuit TEA1053TEA1054
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2a.
O 'aj Ocu —
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Ol 3
HC CD
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u. <
^r.October 1982 147
TEA1053TEA1054
c ~>o aOJ tr
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148 October 1982r^r
DEVELOPMENT SAMPLE DATAThis information is derived from development samplesmade available for evaluation. It does not necessarilyimply that the device will go into regular production.
TEA1055
TELEPHONE TRANSMISSION CIRCUIT
GENERAL DESCRIPTION
The TEA1055 is a bipolar integrated circuit performing the speech and line interface functions inelectronic telephone sets.
Its features are:
• Supplied from telephone line current
• Voltage regulator with adjustable d.c. voltage drop and d.c. resistance• High-impedance microphone input
• Muting input for pulse or DTMF dialling
• Gain setting facility on all amplifiers
• Line current dependent gain control facility with corrections for the exchange supply voltage andits feeding bridge resistance
• Supply output for additional circuits
QUICK REFERENCE DATA
Line voltage at l| ine= 15 mA
Line current operating range
Telephone line impedance
Supply current
Voltage gain, transmitting amplifier
MIC input
DTMF input
Voltage gain, receiving amplifier
Gain adjustment range
transmitting amplifier
receiving amplifier
Range of gain control with line current,
all amplifiers
Exchange supply voltage range
Exchange feeding bridge resistance
Operating ambient temperature range
v line typ. 4,2 V
'line 10 to 140 mAl
z linel nom. 600 n
'cc typ. 1 mA
AvdAyd
typ.
typ.
20 dB25,6 dB
Avd typ. 27 dB
AAvdAAvd
typ.
typ.
±6 dB±8 dB
AAvd typ. 6 dB
vexch 24 to 60 V
Rexch 400 or 800 nTamb -25 to + 70 °C
PACKAGE OUTLINE
TEA1055: 18-lead DIL; plastic (SOT-102A).
~^r.October 1982 149
TEA1055
vCc RX
I15 ho
CURRENTREFERENCE
INTERNALREFERENCE
BRDG CX2
11 |9
GAT1
2
CONTROLCURRENT
-^
a-.o
|4
VEE
GAT2 RCX
3 16
TEA1055
o
Fig. 1 Block diagram. The blocks marked dB are attenuators. The MUTE input operates analogue
switches that activate or inhibit the inputs and outputs as required by the function of the MUTE input.
150 October 1982~\r
Telephone transmission circuit
LU
>
TEA1055
J\.PlflJIMING
1 LN2 GAT13 GAT24 V E F
5 GTEL6 CX17 GAR8 IR
9 CX210 RX11 BRDG12 MUTE13 MIC14 DTMF15 VfX16 RCX17 GALN
< 18 RA
<
LU
_lOL
5<GO
positive line connection
gain adjustment connection, transmitting amplifiergain adjustment connection, transmitting amplifiernegative line connection
telephone output
reference decoupling connectiongain adjustment connection, receiving amplifierreceiving amplifier input
external stabilizing capacitor connectionexternal resistor connection
selection input for gain control adaption to feeding bridge impedancemute input
microphone input
dual-tone multi-frequency input
positive supply connection
line voltage adjustment and decoupling connectiongain control with line current connection, all amplifiersd.c. resistance adjustment connection
ln Elu
18 RA
GAT1 [T~ 17 GALN
GAT2 3 16 RCX
vEE [T 15 Vcc
QTEL 5 TEA1055 14 DTMF
CX1 [T_ 13 MIC
GAR 7 12 MUTE
IR 8 11 BRDG
CX2(~9~ Tb~[ RX
7Z88488
Fig. 2 Pinning diagram.
October 1982 151
TEA1055
FUNCTIONAL DESCRIPTION
The TEA1055 contains a receiving amplifier, a transmitting amplifier, means to switch the inputs,
means to adjust the gain of the amplifiers individually, means to vary the gain with the line current
and means to adjust the d.c. voltage drop and d.c. resistance. See the block diagram, Fig. 1
.
Supply: LN, Vcc , VEE , RA, CX1 and CX2 (pins 1, 15, 4, 18, 6 and 9)
The circuit is supplied from the line current, the arrangement is shown in Fig. 3. The circuit develops
its own supply voltage at Vcc. the positive supply connection, pin 1 5. This supply voltage may also be
used to supply an external circuit, e.g. an electret microphone amplifier stage or a CMOS pulse or
DTMF dialler. The current available for this circuit depends on external components, see Fig. 4.
All line current has to flow through the circuit. If the line current exceeds the current required by the
circuit itself via Vcc. P in 15 . i-e - about 1 mA, plus the current required by the peripheral circuits
connected to this pin, then the excess current is diverted via LN, the positive line connection, pin 1,
to RA, the d.c. resistance adjustment connection, pin 18.
The minimum line voltage may be chosen by external resistor R5 and the variation with line current
by external resistor R10. The circuit regulates the line voltage at Tamb = 25 °C to:
R5 + RQV|ine = VLN = -^g— -0.62 + Iln-RIO,
I |_n being the current diverted via LN, the positive line connection.
A regulator decoupling capacitor has to be connected between RCX, pin 16, and Vr£E, the negative
line connection, pin 4, a smoothing capacitor has to be connected between Vcc. P' n 15 ' and V EE. and
a stabilizing capacitor between CX2, pin 9 and Vr; e, pin 4. Further a decoupling capacitor has to be
connected between CX1, the reference decoupling connection, pin 6, and Vr£f£, pin 4.
The dynamic impedance that the circuit presents to the line in the speech band is determined primarily
by resistor R1 connected between LN, pin 1, and Vcc. P' n 15 -
Microphone input MIC (pin 13)
The circuit has a high-impedance microphone input, especially suited for a sensitive microphone, e.g.
an electret microphone with preamplifier. The available gain is typ, 20 dB.
Dual-tone multi-frequency input DTMF and mute input MUTE (pins 14 and 12)
A HIGH level on the MUTE input inhibits the microphone input and the telephone output QTEL and
enables the DTMF input, a LOW level does the reverse. Switching the MUTE input will not produce
any clicks on the line or in the telephone. The available gain from the DTMF input is typ. 25,6 dB.
Receiving amplifier input IR and telephone output QTEL (pins 8 and 5)
The output QTE L is intended for telephone capsules with an impedance of 1 50 U or more. The
available gain is typ. 27 dB.
Gain adjustment connections GAT1, GAT2 and GAR (pins 2, 3 and 7)
The gain of the transmitting amplifier may be adjusted by an external resistor R2 connected between
GAT1 and GAT2, pins 2 and 3 (see Fig. 9). This adjustment influences the sensitivity of the inputs
MIC and DTMF to the same amount. The gain is proportional to R2 and inversely proportional to
R10and R12.
The gain of the receiving amplifier may be adjusted by an external resistor R14 between GAR, pin 7,
and CX1, pin 6. The gain is proportional to R14 and inversely proportional to R12.
152 October 1982
<
2<
Telephone transmission circuit TEA1055
7vGain control with line current, GALN connection (pin 17)
The circuit offers a facility to automatically vary the gain of all its amplifiers with the line current.In this way the circuit compensates for differences in line attenuation. The variation is accomplishedby connecting an external resistor R.1 1 between GALN, pin 17, and VEE ,
pin 4. The value of thisresistor should be chosen in accordance with the supply voltage of the exchange and its feeding bridqeresistance (see Figs 5 and 6).
If no gain variation with line current is required the GALN connection may be left open. All amplifiershave their maximum gain then.
Selection input for gain control adaption to feeding bridge impedance, BRDG (pin 1 1
)
A LOW level at the BRDG input optimized the gain control characteristics of the circuit for a 400 nfeeding bridge in the exchange, a HIGH level for 800 &..
Side tone suppression
In the circuit diagram shown in Fig. 9 side tone suppression is obtained with components C2, R3, R4R7 and R8. Their component values have to be chosen to suit the cable type used. This network
'
attenuates the signal from the telephone line to the I R input of the receiving amplifier. This attenuationmay be adjusted by choosing the value of R7 without affecting the side tone suppression.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply current
'line
'line
d.c.
surge, t < 100 h
Storage temperature range
Operating temperature range
Junction temperature
maxmax
'stg
Tamb
140 mA250 mA
40 to + 1 25 °C
25 to + 70 °C
lax. 150 °C
~\rOctober 1982 153
TEA1055
CHARACTERISTICS
l Mne= 10 to 140 mA; f = 1 kHz; Tamb = 25 °C unless otherwise specified.
symbol
Supply, LN and Vcc (pins 1 and 15)
Line voltage
l line=15mA
l|j ne = 50 mAl, ine
= 100 mA
Variation with temperature
Line current operating range
Supply current at Vcc = 2 v
Microphone input MIC (pin 13)
Input impedance
Voltage gain, see Fig. 7
Gain variation with frequency,
f = 300 to 4000 Hz
Gain variation with temperature at
l| ine= 50mA;Tamb = -5to + 45°C
DTMF input (pin 14)
Input impedance
Voltage gain, see Fig. 7
Gain variation with frequency,
f = 300 to 4000 Hz
Gain variation with temperature at
l nne= 50mA;Tamb = -5to + 45°C
Gain adjustment connections, transmitting
amplifier, GAT1 and GAT2 (pins 2 and 3)
Gain adjustment range
Transmitting amplifier output LN (pin 1
)
Outputvoltageatl|j ne =15mA;R|ine:=600n
d = 2%
Psophometrically weighted* noise output
voltage at l|j ne= 15 mA; R|;ne = 600O
MUTE input (pin 12)
Input voltage
HIGH level
LOW level
Input current
Attenuation of non-selected signals
V|ine
V|ine
v line
-AV| ine/AT
'line
'CC
IZ13-4I
Avd
AAvd
AAvd
IZ144I
Avd1
I
AAvd
AAvd
AAvd
v LN(rms)
VLN(rms)
V|HV|L
—' 12
-AAvd
8
10
40
19
10
24,6
1.4
45
typ-
4,2
10
48
20
±0,5
±0,5
15
25,6
±0,5
±0,5
max.
4,4
5,8
7,3
12
140
1
21
245
26,6
VCC0,2
20
unit
VVV
mV/K
mAmA
dB
dB
dB
kfi
dB
dB
dB
dB
,jV
VV
MA
dB
154 October 1982
<h-<
<
HZLU
>LU
Q
Telephone transmission circuit
Receiving amplifier input I R (pin 8)
Input impedance
Telephone output QTEL (pin 5)
Voltage gain at l|j ne = 15 mA;R load = '50 Q; R14 = 7,5 kSl; see Fig. 8
Gain variation with frequency,
f = 300 to 4000 Hz
Gain variation with temperature at
'line ^ 50 mA; Tamb = -5 to + 45 °C
Maximum output voltage at l|j ne = 15 mA;R1 = 150 Si; d = 2%
Psophometrically weighted* noise outputvoltage at l| ine
= 15 mA
Gain adjustment connection, receiving
amplifier, GAR (pin 7)
Gain adjustment range
Selection input for gain control adaption tofeeding bridge impedance, BRDG (pin 11)
Input voltage
HIGH level
LOW level
Input current
Gain control with line current connectionGALN (pin 17)
Gain control range
Highest line current for maximum gain,
R11 = 105kS2; BRDG = HIGH (R ex
'
ch= 800 «)
BRDG = LOW (R excn = 400n)Lowest line current for minimum gain,
R11 = 105 kli; BRDG = HIGH (R exch = 800 fl)
^exch = 400 fi)
symbol
1*8-41
Avdi
26
i
AAvd I
-
AAvd J
-
vO(r
vO(rms)
l
A\d
V|HV| L
-hi
BRDG = LOW (R,
A A,'vd
Mine
'line
'line
'line
350
22,5
31,5
49,5
81
TEA1055
typ. max.
10
27 28
±0,5
±0,5
40
25
35
55
90
0,2
20
27,5
38,5
60,5
99
dB
dB
dB
mV
MV
dB
VV
MA
dB
mAmA
mAmA
P53 curve.
~^rOctober 1982 155
TEA1055
'line R1 'p
1 15
LN Vcc
r><R5 RCX CX1 RA CX2 VEE
telephone 16 6 18 9 4 F
R9 C4i
+3 c SC6 = C5
+= C9
r
i i
R10
< ii
peripheral
circuit
7Z88495
Fig. 3 Supply arrangement.
'P
ImAI
7Z88492
Tamb 55 C
R9 =20knR10 =2onl| ine = 15 to 12
R5= 110 k«\
\R5= 150 ka
3 4
VCC (V)
Fig. 4 Maximum current l
pavailable from Vcc f° r an external circuit.
156 October 1982Ar
Telephone transmission circuit
<<
5<
1
R11 =00
aA vd
(dB)
-2
-4
Ve«h=\
\
24V V36V \48V V60V
-6Rlt = \47k 2
\\75kn 1105 kO J40kn
zt±C
vexc
1<
5, «24V
20
4 3 2 1 line
2
30 40
ength (km)
50 60 7C
l Mne (mAI
36V5 4 3 1
48V5 4 3 2 1
60V 5 4 3 2
TEA1055
Fig. 5 Gam variation with line current, with R1 1 as a parameter, and with the BRDG input HIGHi.e. the circuit optimized for 800 12. The values chosen for R1 1 suit the usual values for the supplyvoltage of the exchange. The curves are valid for 0,5 mm twisted-pair cables with an attenuation of1 ,2 dB/km and a d.c. resistance of 1 76 12/km.
IdB)
7288502
R11 =00
—
•
vexch \21V \
\36V 48 V v60V
R11V kH \75kII \io 5k.Q 140ka
1
24V
20
543 2 1
40 60
ne length
1
(km)
80 100 120
I
line
36V5 4 3 2
48 V5 4 3 2 1
60V5 4 3 2 1 C
140
(mA)
Fig. 6 Gain variation with line current, with R11 as a parameter, and with the BRDG input LOWi.e. the circuit optimized for 400 12. The values chosen for R1 1 suit the usual values for the supplyvoltage of the exchange. The curves are valid for 0,5 mm twisted-pair cables with an attenuation of1,2 dB/km and a d.c. resistance of 176 12/km.
October 1982 157
TEA1055
.5 .c 2
<A a. c= .5 =
9-iu o•- H- cli.
=> ~
I- 0) c
£5ho £ x= ,, o
c 0) XI
»O) OlCD o
4-"
o3(Am LUH
b Z)c
o £*: "-
=>
.— 3ho >
U °o>£
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h- o cCM 'Z
r* " si
> <D
il < E
158 October 1982^r
Telephone transmission circuit TEA1055
<<Q
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o.
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mI o
0) .!=
S'uj~ I-
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-a
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^\rOctober 1982 159
TEA1055
en 3OJ O
LU
r CC
CD 2Qi OU QCo
co
LU
a.(3
'Z. D0)
c/)V
CO Q Oc h-
m <o
c3
><UJ O
Q'CCCD
<
160 October 1982^r
DEVELOPMENT SAMPLE DATAThis information is derived from development samples
made available for evaluation. It does not necessarily
ill go into regular production.imply that the device \
TEA1060TEA1061
VERSATILE TELEPHONE TRANSMISSION CIRCUITS
WITH DIALLER INTERFACE
GENERAL DESCRIPTION
The TEA1060 and TEA1061 are bipolar integrated circuits performing all speech and line inter-
face functions required in fully electronic telephone sets. The circuits internally perform electronic
switching between dialling and speech.
Features
• Voltage regulator with adjustable static resistance
• Provides supply for external circuitry
• Symmetrical low-impedance inputs for dynamic and magnetic microphones (TEA1060)• Symmetrical high-impedance inputs for piezoelectric microphone (TEA1061)• Asymmetrical high-impedance input for electret microphone (TEA 1061)
• DTMF signal input
• Mute input for pulse or DTMF dialling
• Power down input for pulse dial or register recall
• Receiving amplifier for magnetic, dynamic or piezoelectric earpieces
• Large amplification setting range on all amplifiers
• Line loss compensation facility, line current dependent• Gain control adaptable to exchange supply
QUICK REFERENCE DATA
Line voltage at l|j ne = 15 mALine current operating range
Supply current
power down input LOW
power down input HIGH
Voltage amplification range microphone amplifier
TEA1060
TEA1061
receiving amplifier
Amplification control range
Exchange supply voltage range
Exchange feeding bridge resistance range
Operating ambient temperature range
V LN typ- 4,5 V
'line 10 to 140 mA
'cc typ. 1 mA
'cc typ. 50 mA
Ayd 44 to 60 dB
Avd 30 to 46 dB
Ayd 17 to 39 dB
AAvd typ. 6 dB
Vexch 24 to 60 V
^exch 400 to 1000 n
"^arnb -25 to + 75 °C
PACKAGE OUTLINE
18-lead DIL; plastic (SOT-102A).
~^rNovember 1982 161
TEA1060TEA1061
MIC+ -
MIC- •
TEA1060TEA1061
£
>
SUPPLY AND
REFERENCE
'»
*>
CONTROL
CURRENT
I
10
EE
I16
REG
CURRENT
REFERENCE
•s.
"N.
AGC STAB
> <
- QR +
- QR-
7Z86758.1 SLPE
Fig. 1 Block diagram. The blocks marked "dB" are attenuators. The block marked (1 ) is only present
intheTEA1061.
162 February 1983^r
Versatile telephone transmission circuits
with dialler interfaceTEA1060TEA1061
PINNING
1 LN
2 GAS1
ln[T u~Te~| slpe
3 GAS2
GAS1 [jT T7| AGC 4 QR-GAS 2 Qj_ "l6~] REG 5 QR +
OR- [T^ iU vcc6 GAR
QR+ [IT TEA1060TEA1061
7T\ MUTE7 MIC-
GAR[j3_ 7j~| DTMF 8 MIC +
MIC-[_7_ ~!2~l PD 9 STAB
MIC+ [jT TT| IR 10 VEE
<STAB [F
illVEE
11
12
13
IR
PD1-
<Q
/Z8E5746.1
DTMFLU—
1
a.
5Fig. 2 Pinning di agram.
14
15
MUTE
vCc<CO 16 REG
ZLU
17
18
AGC
SLPE
positive line terminal
gain adjustment; transmitting
amplifier
gain adjustment; transmitting
amplifier
inverting output; receiving amplifier
non-inverting output, receiving amplifier
gain adjustment; receiving
amplifier
inverting microphone input
non-inverting microphone input
current stabilizer
negative line terminal
receiving amplifier input
power-down input
dual-tone multi-frequency input
mute input
positive supply decoupling
voltage regulator decoupling
automatic gain control input
slope (d.c. resistance) adjustment
>LU
Q FUNCTIONAL DESCRIPTION
Supply: Vcc , LN, SLPE, REG and STABThe circuit and its peripheral circuits usually are supplied from the telephone line. The circuit developsits own supply voltage at Vcc and regulates its voltage drop. The supply voltage Vcc may also be usedto supply external peripheral circuits, e.g. dialling and control circuits.
The supply has to be decoupled by connecting a smoothing capacitor between Vcc and VEE- the
internal voltage regulator has to be decoupled by a capacitor from REG to VEE . An internal currentstabilizer is set by a resistor of 3,6 kfi between STAB and VEE .
The d.c. current flowing into the set is determined by the exchange supply voltage Vexcn the feedingbridge resistance R exch ,
the d.c. resistance of the subscriber line R Mne and the d.c. voltage on thesubscriber set (see Fig. 3).
If the line current l| ine exceeds the current l cc required by the circuit itself, i.e. about 1 mA, plus thecurrent l
prequired by the peripheral circuits connected to Vcc , then the voltage regulator diverts the
excess current via LN.
The voltage regulator adjusts the average voltage on LN to:
V LN = v ref + ' LN * R 9 = V re f + (l| ine - <CC ~ lp> * R9.
v ref bein9 an internally generated temperature compensated reference voltage of 4 2 V and R9 beingan external resistor connected between SLPE and VEE . Under normal conditions I LN» l cc + |
The static behaviour of the circuit then equals a 4,2 V voltage regulator diode with an internal resist-ance R9. In the audio-frequency range the dynamic impedance equals R1.
^\rFebruary 1983 163
TEA1060TEA1061
FUNCTIONAL DESCRIPTION (continued)
The current l„ available from Vqc for supplying peripheral circuits depends on external components.
Figure 4 shows this current for Vqc = 3V min., this being the minimum supply voltage for most CMOS
circuits including a diode voltage drop for an enable diode. If MUTE is LOW the available current is
further reduced when the receiving amplifier is driven.
Microphone inputs MIC+ and MIC— and gain adjustment pins GAS1 and GAS2
The TEA1060 and TEA1061 have differential microphone inputs.
The TEA1060 is intended for low-sensitivity, low-impedance dynamic or magnetic microphones. Its
input impedance is 2 x 4 kfi and its voltage amplification is typ. 52 dB.
The TEA1061 is intended for a piezoelectric microphone or an electret microphone with built-in FET
source follower. Its input impedance is 2 x 20 kli and its voltage amplification is typ. 38 dB.
The arrangements with the microphone types mentioned are shown in Fig. 5.
The amplification of the microphone amplifier in both types can be adjusted over a range of ± 8 dB to
suit the sensitivity of the transducer used. The amplification is proportional to external resistor R7
connected between GAS1 and GAS2.
An external capacitor C6 of 100 pF between GAS1 and SLPE is required to ensure stability. A larger
value may be chosen to obtain a first-order low-pass filter. The cut off frequency corresponds with the
time constant R7 x C6.
Mute input MUTE
A HIGH level at MUTE enables the DTMF input and inhibits the microphone inputs and the receiving
amplifier, a LOW level or an open circuit does the reverse. Switching the mute input will cause negligible
clicks at the telephone outputs and on the line.
Dual-tone multi-frequency input DTMF
When the DTMF input is enabled, dialling tones may be sent onto the line. The voltage amplification
from DTMF to LN is typ. 32 dB and varies with R7 in the same way as the amplification of the
microphone amplifier. The signalling tones can be heard in the earpiece at a low level (confidence tone).
Receiving amplifier: IR, QR +, OR- and GAR
The receiving amplifier has one input IR and two complementary outputs, a non-inverting output QR +
and an inverting output QR-. These outputs may be used for single-ended or for differential drive,
depending on the sensitivity and type of earpiece used (see Fig. 6). Amplification from I R to QR + is
typ. 25 dB. This will be sufficient for low-impedance magnetic or dynamic earpieces; these are suited
for single-ended drive. By using both outputs (differential drive) the amplification is increased by 6 dB.
This makes differential drive possible, which is required for high-impedance dynamic, magnetic and
piezoelectric earpieces with load impedances exceeding 450 fi.
The output voltage of the receiving amplifier is specified for continuous-wave drive. The maximumoutput voltage will be higher under speech conditions, where the ratio of peak and r.m.s. value is higher.
The amplification of the receiving amplifier can be adjusted over a range of ±8 dB to suit the
sensitivity of the transducer used. The amplification is proportional to external resistor R4 connected
from GAR to QR +.
An external capacitor C4 of 100 pF between QR + and GAR is required to ensure stability. A larger
value may be chosen to obtain a first-order low-pass filter. The cut-off frequency corresponds with the
time constant R4 x C4.
164 November 1982
LU
>
Versatile telephone transmission circuits
with dialler interfaceTEA1060TEA1061
Automatic gain control input AGCAutomatic line loss compensation will be obtained by connecting a resistor R6 form AGC to Vrfg.This automatic gain control varies the amplification of the microphone amplifier and the receivingamplifier in accordance with the d.c, line current. The control range is 6 dB. This corresponds with aline length of 5 km for a 0,5 mm diameter copper twisted-pair cable with a d.c. resistance of 176 n/krnand an average attention of 1,2 dB/km.
Resistor R6 should be chosen in accordance with the exchange supply voltage and its feeding bridgeresistance (see Fig. 7 and Table 1). Different values of R6 give the same ratio of line currents for beginand end of the control range.
If automatic line loss compensation is not required AGC may be left open. The amplifiers then all givetheir maximum amplification as specified.
Power-down input PD
During pulse dialling or register recall (timed loop break) the telephone line is interrupted, as a conse-quence it provides no supply for the transmission circuit. These gaps have to be bridged by the chargein the smoothing capacitor C1
.The requirements on this capacitor are relaxed by applying a HIGH
level to the PD input, which reduces the supply current from typ. 1 mA to typ. 50 mA.
< A HIGH level at PD further disconnects the capacitor at REG, with the effect that the circuit'sH impedance equals a 4,2 V voltage regulator diode with an internal resistance equal to R9. This results
Q in rectangular current waveforms in pulse dialling and register recall.
^ When this facility is not required PD may be left open.
< Side-tone suppression
l- Suppression of the transmitted signal in the earpiece is obtained by the anti-side-tone network consistingof R2, R3, R8 and Z ba] (see Fig. 10). Maximum compensation is obtained when Zba i equals the lineimpedance Z|j ne as seen by the set.
In practice ZMne varies strongly with line length and cable type; consequently an average value has tobe chosen for Z ba] .
The suppression further depends on the accuracy with which Z ba i approaches theaverage line impedance.
The anti-side-tone network attenuates the signal from the line. With R8 = 620 ft and R9 = 20 ft theattenuation is 29,1 dB. The attenuation is flat over the audio-frequency range.
^\rNovember 1982 165
TEA1060TEA1061
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Positive line voltage V|_n
Line current
average 'line(AV)
non-repetitive (tmax = 100 hours) hine(S)
non-repetitive peak (tmax = 1 ms) hine(SM)
Voltage on all other pins V
-V
Total power dissipation Ptot
Storage temperature range Tstg
Operating ambient temperature range TamD
CHARACTERISTICS
l|j ne= 10 to 140 mA; Vf£E = V; f = 800 Hz; Tamb = 25 °C; unless otherwise specified.
15 V
max. 140 mA
max. 250 mA
max. 1 A
max. vCc + 0,7 V
max. 0,7 V
max. 640 mW-40 to + 125 °C
-25 to + 75 °C
parameter symbol min. typ. max. unit
Supply: LN and Vfjc (pins 1 and 15)
Voltage drop over circuit
at l|j ne = 5mA V LN— 4,3 - V
at l|jne = 15 mA v Ln 4,3 4,5 4,7 V
at l|j ne = 100 mA v Ln- 6,2 7 V
Variation with temperature AV LN/AT -2 + 2 mV/K
Supply current
PD= LOW; Vcc = 2,8 V 'cc- 0,96 1,25 mA
PD = HIGH 'cc- 50 - MA
Microphone inputs IVIIC+ and MIC—
Input impedance
TEA1060l
zisl
— 4 - k$2
TEA1061lz isl
- 20 - v.a
Standard deviation on input impedance a - 12 - %
Common-mode rejection ratio, TEA1060 kCMR - t.b.f. - dB
Voltage amplification at
l| ine= 15 mA; R7 = 68 kfi
TEA 1060 Avd 51 52 53 dB
TEA1061 Avd 37 38 39 dB
Variation with frequency
at f = 300 to 3400 Hz AAvd/Af — ±0,2 — dB
Variation with temperature at
l| ine= 50 mA; Tamb = -25 to + 75 °C AAvd/AT
- ±0,5 - dB
166 November 1982
<I-<
0.
<
UJ
>
Versatile telephone transmission circuits
with dialler interface
parameter
TEA1060TEA1061
Dual-tone multi-frequency input DTMFInput impedance
Standard deviation on input impedance
Voltage amplification
at l|j ne = 15 mA; R7 = 68 k£2
Variation with frequency
at f = 300 to 3400 Hz
Variation with temperature at
'line= 5° mA; Tamb = -25 to + 75 °C
Gain adjustment pins GAS1 and GAS2
Amplification variation with R7,
transmitting amplifier
Transmitting amplifier output LN
Output voltage at l|j ne = 15 mA;dtot = 2%
dtot =10%
Noise output voltage
at l|ine = 15 mA; R7 = 68k£2;psophometrically weighted (P53 curve)
Receiving amplifier input IR
Input impedance
Receiving amplifier outputs QR + and QR-Output impedance; single-ended
Voltage amplification
at l|;ne = 15 mA; R4 = 100 k£2;
single-ended; R L = 300 £2
differential; R(_ = 600 £2
Variation with frequency,
at f = 300 to 3400 Hz'
Variation with temperature at
I line = 50 mA; Tamb = -25 to + 75 °C
Output voltage at l
p= 0; dtot
= 2%; sine-wave drivesingle-ended; R|_ = 150 £2
single-ended; R|_= 450 £2
differential; C|_ = 47 nF; f = 3400 Hz
Noise output voltage
at l|i ne = 15 mA; R4 = 100 k£2;
psophometrically weighted (P53 curve)
single-ended; R|_ = 300 £2
differential; R(_ = 600 £2
symbol typ.
Avd
AAvd/Af
AAvd/AT
AAvd
v LN(rms)
v LN(rms)
31
1,4
AAvd/Af
AAvd/AT
vo(rms)
Vrt/rmcl
v no(rms)
vno(rms)
0,35
0,5
0,9
20
12
32 33
±0,2 -
±0,5 -
+ 8
2,4
2,7
-70
20
lz osl
— 15 -
Avd 24 25 26
Avd 30 31 32
:0,2
:0,5
0,4
0,6
1,1
50
100
unit
k£2
%
dB
dB
dB
dB
V
V
dBmp
k£2
£2
dB
dB
dB
dB
V
V
V
MV
A.V
November 1982 167
TEA1060TEA1061
CHARACTERISTICS (continued)
parameter symbol min. typ. max. unit
Gain adjustment pin GAR
Amplification variation with R4,
receiving amplifier AAvd -8 + 8 dB
MUTE input
Input voltage
HIGH V|H 1,5 vCc V
LOW V|L _ 0,3 V
Input current 'mute 8 15 MA
Reduction of voltage amplification from
M I C+ and MIC-to LN at MUTE = HIGH -AAvd 70 — dB
Voltage amplification from DTMF to QR + or QR-at MUTE = HIGH; single-ended load;
R L = 300ft Avd-12 dB
Power-down input PD
Input voltage
HIGH V|H 1,5 vCc V
LOW V| L- 0,3 V
Input current 'PD 5 10 MA
Automatic gain control input AGC
Amplification control range ~AAvd 6 - dB
Highest line current for maximumamplification at R6 = 100 kS2 'line 23 — mA
Lowest line current for minimumamplification at R6 = 100 kS2 'line 58 mA
168 February 1983^r
Versatile telephone transmission circuits
with dialler interfaceTEA1060TEA1061
"line 'line
operipheral
circuits
Fig. 3 Supply arrangement.
<Q
5<ifi
J
Fig. 4 Maximum current l
pavailable from Vcc for external (peripheral) circuitry. Curve "a" is valid
when the receiving amplifier is not driven or when MUTE = HIGH, curve "b" is valid when MUTE = LOWand the receiving amplifier is driven, V
( rms)= 1 50 mV, R L
=1 50 n.
November 1982 169
TEA1060TEA1061
(a) (b) (c)
Fig. 5 Alternative microphone arrangements, (a) magnetic or dynamic microphone, TEA1060. Theresistor marked (1) may be connected to lower the terminating impedance, (b) electret microphone,
TEA1061. (c) piezoelectric microphone, TEA1061.
(b) (d)
Fig. 6 Alternative receiver arrangements, (a) dynamic telephone with less than 450 Q, impedance,
(b) dynamic telephone with more than 450 SI impedance, (c) magnetic telephone. The resistor marked
(1) may be connected to obtain an appropriate acoustic frequency characteristic, (d) piezoelectric tele-
phone.
170 February 1983
Versatile telephone transmission circuits
with dialler interfaceTEA1060TEA1061
20 4° 60 80 100 120 140
'line l">A>
< Fig. 7 Variation of amplification with line current, with R6 as a parameter.
< Table 1. Values of resistor R6 for optimum line loss compensation, for various usual values of exchange!_
supply voltage Vexch and exchange feeding bridge resistance R excn .
>
Vexch (V)
Rexch (fi)
400 600 800 1000
55
R6 (kS2)
24 43 X X
36 91 71 60 52
48 128 100 84 71
60 X X 107 92
November 1982 171
TEA1060TEA1061 JL
R1 'line
620n
15 1
+
100 jiF S11
IR
LN
GAR _6
V, (Z
sMIC +
MIC-TEA1060
QR +
QR-
RL fl
^o
5 7
4
600 n I
+
S 100 |iF
13 TEA1061DTMF
MUTEGAS1
2
Q 10 to 140
5^. 14IOjiF^;
J^rr
ViW l
1l68knV. 12
PD GAS2 J I1 C6 :
VgE REG AGC STAB SLPE
100 pF
10
+C3 c
4,7 |iF
16
'[
17
l=l
18
S R9
7Z86755.1
Fig. 8 Test circuit for defining voltage amplification of MIC+, MIC— and DTMF inputs. Voltage ampli-
fication is defined as: Avcj= 20 log |V /Vj|. For measuring the amplification from MIC + and MIC— the
MUTE input should be LOW or open, for measuring the DTMF input MUTE should be HIGH. Inputs
not under test should be open.
"Hon
C1 = 100fjF
IR
MIC +
MIC-
DTMF
MUTE
PD
TEA1060TEA1061 QR-
GAS1
V,
GAS2
EE REG AGC STAB SLPE
C3 t
4,7 iii' (H 1)§(]
R9
20 n
R4
ioo kn'
E= 100 fjF
60OS2
C4100 pF
J_C6"lOOpF
9 10to 140mA
172
Fig. 9 Test circuit for defining voltage amplification of the receiving amplifier. Voltage amplification
is defined as: Avcj= 20 log |V /Vj|.
February 1983-\r
Versatile telephone transmission circuits
with dialler interfaceTEA1060TEA1061
<h-<QLU
V)
a.
O
>uj
Q
<
o
zq<O-Ia.a.
<
CD TJ"a «-<
5 0) r
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-fl>
< oLUH b ^o o CD
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o a ^
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a.a.
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Zgh-
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o
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<
^rFebruary 1983 173
TEA1060TEA1061
APPLICATION INFORMATION (continued)
DTMF
M PCD3310
^O
cradle
contact
telephone
line
I
(b)
W<=
DP/FL
VSS
to
Fig. 11 Typical applications of the TEA1060 or TEA1061 (simplified).
(a) DTMF set with the PCD3310 CMOS DTMF dialling circuit with redial. The dashed lines show an
optional flash (register recall by timed loop break).
(b) Pulse dial set with one of the PCD3320 family of CMOS interrupted current-loop dialling
circuits.
(c) Dual-standard (pulse and DTMF) feature phone with the PCD3340 CMOS telephone controller
and the PCD3312 CMOS DTMF generator with l
2 C bus.
174 November 1982^r
DEVELOPMENT SAMPLE DATAThis information is derived from development samplesmade available for evaluation. It does not necessarily
imply that the device will go into regular production,
TEA1062TEA1063
VERSATILE TELEPHONE TRANSMISSION CIRCUITS
GENERAL DESCRIPTION
The TEA1062 and TEA1063 are bipolar integrated circuits performing all speech and line interfacefunctions required in fully electronic telephone sets. The devices can be installed in the handset tofacilitate two-wire connection to the dial and control circuits mounted in the base of the telephone set.
Features
• Voltage regulator with adjustable static resistance
• Symmetrical low-impedance inputs for dynamic and magnetic microphones (TEA1062)• Symmetrical high-impedance inputs for piezoelectric microphone (TEA 1063)• Asymmetrical high-impedance input for electret microphone (TEA1063)• Receiving amplifier for magnetic, dynamic or piezoelectric earpieces• Large amplification setting range on all amplifiers
• Line loss compensation facility, line current dependent• Gain control adaptable to exchange supply
QUICK REFERENCE DATA
Line voltage at l|| ne = 15 mALine current operating range
Supply current
Voltage amplification range
microphone amplifier
TEA1062TEA1063
receiving amplifier
Amplification control range
Exchange supply voltage range
Exchange feeding bridge resistance range
Operating ambient temperature range
V LN typ. 3,75 V
'line 10 to 140 mA
'cc typ. 1 mA
Avd 44 to 60 dB
Avd 30 to 46 dB
Avd 17 to 39 dB
AAvd typ. 6 dB
Vexch 24 to 60 V
^exch 400 to 1000 n
^an-ib -25 to + 75 °C
PACKAGE OUTLINE
16-lead DIL; plastic (SOT-38).
^rFebruary 1983 175
TEA1062TEA1063
176
MIC +
MIC-
»SUPPLY
ANDREFERENCE
;>:
\»
CONTROLCURRENT
> X
CURRENTREFERENCE
TEA1062TEA1063
QR +
QR-
V EE REG AGC STAB n.c. SLPE
Fig. 1 Block diagram. The block marked "dB" is an attenuator which is present only in the TEA1063.
LN \T_
GAS1 [T
GAS 2 \JT_
OR- [T
QR + [7T
GAR [TT
MIC- [T£
MIC+ [IT
u
TEA1062TEA1063
16|
SLPE
Ti"| AGC
TT] REG
jU vcc
Tj~| n.c.
IT] IR
To] v EE
~9~| STAB
Fig. 2 Pinning diagram.
PINNING
1 LN
2 GAS1
3 GAS2
4 QR-
5 QR +
6 GAR
7 MIC-
8 MIC +
9 STAB
10 VEE
11 IR
12 n.c.
13 vcc14 REG
15 AGC
16 SLPE
positive line terminal
gain adjustment; transmitting amplifier
gain adjustment; transmitting amplifier
inverting output; receiving amplifier
non-inverting output; receiving amplifier
gain adjustment; receiving amplifier
inverting microphone input
non-inverting microphone input
current stabilizer
negative line terminal
receiving amplifier input
not connected
positive supply decoupling
voltage regulator decoupling
automatic gain control input
slope (d.c. resistance) adjustment
February 1983
Versatile telephone transmission circuits
<Q
TEA1062TEA1063
FUNCTIONAL DESCRIPTION
Supply: VCC , LN, SLPE, REG and STABThe circuit and its associated dial and control circuits usually are supplied from the telephone line. Thecircuit develops its own supply voltage at Vcc and regulates its voltage drop. The supply voltage Vccmay also be applied to a FET source follower to be used as an impedance converter for an electretmicrophone.
The supply has to be decoupled by connecting a smoothing capacitor between Vcc and V EE ; theinternal voltage regulator has to be decoupled by a capacitor from REG to VEE . An internal currentstabilizer is set by a resistor of 3,6 k£l between STAB and VEE .
The d.c. current flowing into the set is determined by the exchange supply voltage Vexcn , the feedingbridge resistance R exch , the d.c. resistance of the subscriber line R| ine and the d.c. voltage on thesubscriber set (see Fig. 3).
If the line current l Mne exceeds the current l cc required by the circuit itself, i.e. about 1 mA, then thevoltage regulator diverts the excess current via LN.
The voltage regulator adjusts the average voltage on LN to:
V LN = v ref + 'LN * R9 = V ref + (l Mne - l cc ) x R9,
V re fbeing an internally generated temperature compensated reference voltage of 3,45 V and R9 being
an external resistor connected between SLPE and V EE . Under normal conditions l LN > l cc . Thestatic behaviour of the circuit then equals a 3,45 V voltage regulator diode with an internal resistance
_, R9. In the audio frequency range the dynamic impedance equals R1.Q-
< Microphone inputs MIC+ and MIC- and gain adjustment pins GAS1 and GAS2
£ The TEA1062 and TEA1063 have differential microphone inputs.
| The TEA1062 is intended for low-sensitivity low-impedance dynamic or magnetic microphones. Its
g input impedance is 2 x 4 kfi and its voltage amplification is typ. 52 dB.
jjjThe TEA1063 is intended for a piezoelectric microphone or an electret microphone with built-in FET
> source follower. Its input impedance is 2 x 20 kJ2 and its voltage amplification is typ. 38 dB.
Q The arrangements with the microphone types mentioned are shown in Fig. 4.
The amplification of the microphone amplifier in both types can be adjusted over a range of ± 8 dB tosuit the sensitivity of the transducer used. The amplification is proportional to external resistor R7connected between GAS1 and GAS2.
An external capacitor C6 of 100 pF between GAS1 and SLPE is required to ensure stability. A largervalue may be chosen to obtain a first-order low-pass filter. The cut-off frequency corresponds with thetime constant R7 x C6.
Receiving amplifier: IR, QR+, QR- and GARThe receiving amplifier has one input IR and two complementary outputs, a non-inverting outputQR+ and an inverting output QR-. These outputs may be used for single-ended or for differentialdrive, depending on the sensitivity and type of earpiece used (see Fig. 5). Amplification from IR toQR+ is typ. 25 dB. This will be sufficient for low-impedance magnetic or dynamic earpieces- these aresuited for single-ended drive. By using both outputs (differential drive) the amplification is increasedby 6 dB. This makes differential drive possible for high-impedance dynamic, magnetic and piezoelectricearpieces with load impedances exceeding 180 n.
The output voltage of the receiving amplifier is specified for continuous-wave drive. The maximumoutput voltage will be higher under speech conditions, where the ratio of peak and r.m.s. value is higher.
February 1983 177
TEA1062TEA1063
FUNCTIONAL DESCRIPTION (continued)
The amplification of the receiving amplifier can be adjusted over a range of ± 8 dB to suit the sensitivity
of the transducer used. The amplification is proportional to external resistor R4 connected from GAR
toQR+.
An external capacitor C4 of 100 pF between QR+ and GAR is required to ensure stability. A larger
value may be chosen to obtain a first-order low-pass filter. The cut-off frequency corresponds w.th the
time constant R4 x C4.
Automatic gain control input AGC
Automatic line loss compensation will be obtained by connecting a resistor R6 from AGC to V EE .
This automatic gain control varies the amplification of the microphone amplifier and the receiving
amplifier in accordance with the d.c. line current. The control range is 6 dB. This corresponds with a
line length of 5 km for a 0,5 mm diameter copper twisted-pair cable with a d.c. resistanceof 1 76 Sl/km
and an average attenuation of 1,2 dB/km.
Resistor R6 should be chosen in accordance with the exchange supply voltage and its feeding bridge
resistance (see Fig. 6 and Table 1). Different values of R6 give the same ratio of line currents tor begin
and end of the control range.
If automatic line loss compensation is not required, AGC may be left open. The amplifiers then all give
their maximum amplification as specified.
Side-tone suppression
Suppression of the transmitted signal in the earpiece is obtained by the anti-side-tone network
consisting of R2, R3, R8 and Z ba |
(see Fig. 9). Maximum compensation is obtained when Zba |
equals
the line impedance Z|jne as seen by the set.
In practice Z| ine varies strongly with line length and cable type; consequently an average value has to
be chosen for Zba |. The suppression further depends on the accuracy with which Z bat approaches the
average line impedance.
The anti-side-tone network attenuates the signal from the line. With R8 = 620 ft and R9 = 20 SI, the
attenuation is 29,1 dB. The attenuation is flat over the audio frequency range.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Positive line supply voltage V LN max
Line current
average l|ine(AV) max
non-repetitive (tmax = 100 hours) l|ine(S) max
non-repetitive peak (tmax = 1 ms) 'line(SM) max
Voltage on all other pins v
-V
Total power dissipation °tot
Storage temperature range
Operating ambient temperature range
'stg
Tamb
15 V
140 mA
250 mA
1 A
max. VCc+ 0,7 V
max. 0,7 V
max. 640 mW-40to + 125 °C
-25 to +75 °C
178 February 1983
Versatile telephone transmission circuits TEA1062TEA1063
CHARACTERISTICS
l| ine = 1 to 1 40 mA; V EE = V; f = 800 Hz; TarTlb= 25 °C; unless otherwise specified
parameter symbol min. typ. max. unit
Supply: LN and Vrx (pins 1 and 15)
Voltage drop over circuit
at l|i ne = 5 mA v Ln- 3,55 - V
at t|j ne = 15 mA v Ln 3,55 3,75 3,95 V
at l|j ne = 100 mA v Ln- 5,4 6,2 V
Variation with temperature AV LN/AT -2 + 2 mV/KSupply current at Vrjc = 2,8 V 'cc
- 0,96 1,25 mA
Microphone inputs MIC+ and MIC—
Input impedance
TEA1062l*isl
- 4 - ktt
TEA1063l^isl
- 20 - kQ.
Standard deviation on input impedance a - 12 - %Common-mode rejection ratio; TEA1062 kCMR — t.b.f. - dB
Voltage amplification
at l|i ne = 15 mA; R7 = 68 k£2
TEA1062 Avd 51 52 53 dB
TEA1063 Avd 37 38 39 dB
Variation with frequency
at f = 300 to 3400 Hz AAvd/Af- ±0,2 - dB
Variation with temperature at
l|j ne = 50 mA; Tamb = -25 to + 75 °C AAvd/AT- ±0,5 - dB
Gain adjustment pins GAS1 and GAS2
Amplification variation with R7,
transmitting amplifier AAvd -8 - + 8 dB
Transmitting amplifier output LN
Output voltage at l|j ne= 15 mA;
dtot = 2% v LN(rms) 1,2 1,8 - V
dtot =10% v LN(rms)- 2,1 - V
Noise output voltage
at I |jne= 15 mA; R7 = 68 kft;
psophometrically weighted (P53 curve) ^no(rms)- -70 - dBmp
Receiving amplifier input IR
Input impedancel
z isl- 20 - kn
^rFebruary 1983 179
TEA1062TEA1063
CHARACTERISTICS (continued)
parameter
Receiving amplifier outputs QR+ and QR-
Output impedance; single-ended
Voltage amplification
at l| ine= 15 mA; R4 = 100 k£2;
si ngle-ended ; R |_= 1 50 £2
differential; R L = 450a
Variation with frequency
at f = 300 to 3400 Hz
Variation with temperature at
l| ine= 50mA;Tamb = -25to + 75°C
Output voltage
at dtot = 2%; sine-wave drive
single-ended; Rl = 150 f2
differential; R L = 450fi
differential; C L= 47 nF; f = 3400 Hz
Noise output voltage
at l| ine= 15mA;R4= 100 kSl;
psophometrically weighted (P53 curve)
single-ended; R|_= 150 £2
differential; R L = 450 fi
Gain adjustment pin GAR
Amplification variation with R4,
receiving amplifier
Automatic gain control input AGC
Amplification control range
Highest line current for maximumamplification at R6 = 100 kQ.
Lowest line current for minimum
amplification at R6 = 1 00 kfl
symbol
Avd
Avd
AAvd /Af
AAvd/AT
v o(rms|
Vo(rms)
Vo(rms)
v no(rms)
Vnnf rm<:l
AA^d
-AAvd
'line
'line
24
30
0,25
0,45
0,6
typ.
15
25
31
+ 0,2
±0,5
0,3
0,55
0,75
50
100
6
23
58
26
32
a
dB
dB
dB
dB
V
V
V
dB
dB
mA
mA
180 February 1983^r
Versatile telephone transmission circuits A TEA1062TEA1063
1j
^ vcc
DC —N K' TEA1062AC —k "V TEA1063
REG STAB 5, 1 PL" »[[
Il4 | 9 16 10
^ C3
T- 0„
i+
<Q
<to
LU
(a)
Fig. 3 Supply arrangement.
(b) (c)
Fig. 4 Alternative microphone arrangements: (a) magnetic or dynamic microphone, TEA1062 (theresistor marked (1) may be connected to lower the terminating impedance); (b) electret microphoneTEA1063; (c) piezoelectric microphone, TEA1063.
(b) (c) (d)
Fig. 5 Alternative receiver arrangements: (a) dynamic telephone with less than 180 n impedance-lb) dynamic telephone with more than 180 £2 impedance; (c) magnetic telephone (the resistor marked(1) may be connected to obtain an appropriate acoustic frequency characteristic); (d) piezoelectrictelephone.
AFebruary 1983 181
TEA1062TEA1063
Fig. 6 Variation of amplification with line current, with R6 as a parameter.
Table 1 Values of resistor R6 for optimum line loss compensation, for common values of exchange
supply voltage Vexch and exchange feeding bridge resistance R exch-
Rexch <«>
400 600 800 1000
R6 (kn)
24 55 43 X X
Vexch 36 91 71 60 52
(V) 48 128 100 84 71
60 X X 107 92
182 February 1983
Versatile telephone transmission circuits TEA1062TEA1063
<i-<a
<CO
>LU
Q
6TEA1062
GAS2
^EE REG AGC STAB SLPE
l
R
600L
fl
R7
68 kS!
C6 :
100 pF
R5 rh r 9R6
jI 3 p6
f-^ 10 to 140rr
Fig. 7 Test circuit for defining voltage amplification of MIC+, MIC— inputs. Voltage amplification is
defined as: AV[j= 20 log |V /Vj |. Inputs not under test should be open circuit.
me
TEA1062TEA1063 QR-
GAS1
GAS2VEE REG AGC STAB SLPF
100 |iF
600S1
L ur
.C6
'lOOpF
sf HN-
1 10 to 140 mA
Fig. 8 Test circuit for defining voltage amplification of the receiving amplifier. Voltage amplification
is defined as: A vcj= 20 log |V /Vj |.
A^February 1983 183
TEA1062TEA1063
APPLICATION INFORMATION
Fig. 9 Typical application of the TEA1062 or TEA1063, shown here with a piezoelectric earpiece.
Resistor R10 limits the current into the circuit during line transients. Voltage limitation resulting from
transients depends on the dialling system and is not indicated.
APPLICATION INFORMATION SUPPLIED ON REQUEST
184 February 1983^r
Versatile telephone transmission circuits TEA1062TEA1063
PULSE DIALLER CIRCUIT
<a
^i2i
©
is
RINGER CIRCUIT
©
HANDSET SPEECH CIRCUIT
4 2-wirecordTEA1062
TEA1063
-a
<C3
>UJ
DTMF DIALLER CIRCUIT
F>
AmTEA1043
TEA1044
L-O-
HANDSET SPEECH CIRCUIT
-O—TEA1062
TEA1063
-a-a
(3 BST72
RINGER CIRCUIT
© -@
Fig. 10 Typical applications (simplified) of the TEA1062 or TEA1063: (a) basic pulse dial set with oneof the PCD3320 family of C-MOS interrupted current-loop dialling circuits; (b) basic DTMF set with
TEA1043/TEA1044 bipolar DTMF dialler.
~^rFebruary 1983 185
DOMESTIC APPLIANCES
TCA280A
GENERAL-PURPOSE TRIGGERING CIRCUIT
GENERAL DESCRIPTION
The TCA280A is a bipolar integrated circuit delivering positive pulses for triggering a triac or a thyristor.
The flexibility of the circuit makes it suited for a great variety of applications, such as:
• synchronous on/off switching
• phase control
• time-proportional control
• temperature control
• motor speed control
Features
• adjustable proportional range
• adjustable hysteresis
• adjustable firing burst repetition time
• adjustable pulse width
• supplied from the mains
• provides supply for external temperature bridge
• low supply current, low dissipation
QUICK REFERENCE DATA
Supply voltage, d.c.
(derived from mains voltage)
Supply current (average value)
Output current
Output pulse width
Power dissipation, unloaded
Operating ambient temperature range
vCc typ. 14,4 V
'cc typ. 1 mA
-'oh* max. 200 mAtw typ. 190 ms
p typ. 15 mWTamb -20 to + 80 °C
Negative current is defined as conventional current flow out of a device. A negative output currentis suited for positive triac triggering.
PACKAGE OUTLINE
16 lead DIL; plastic (S0T-38).
~^rFebruary 1983 189
TCA280A
190 February 1983"^r
General-purpose triggering circuit TCA280A
pw \j2u li] vee
QZ [T uT| QS
RX1 QT ~m"| is
QC+ [T
ic+ []T
TCA280ATj] RX2
77] ENZ
ic- [IT TT] vCc
oc- [T To] qa
NHA [~8~ ~9~] IA
Fig. 2 Pinning diagram.
PINNING
1 PW
2 QZ
3 RX1
4 QC +
5 IC +
6 IC-
7 QC-
8 INHA
9 IA
10 QA11 vCc12 ENZ
13 RX2
14 IS
15 QS
16 V E E
pulse width control input
zero-crossing detector output
external resistor
comparator non-inverting output
comparator non-inverting input
comparator inverting input
comparator inverting output
output stage inhibiting input
output stage input
output stage output
positive supply
enable input, zero crossing detector
external resistor
sawtooth generator trigger input
sawtooth generator output
ground
FUNCTIONAL DESCRIPTION
The TCA280A contains four circuits that may be interconnected externally to perform the function
required, and a supply part. The four circuits are a zero-crossing detector, a differential amplifier, a
sawtooth generator and an output stage.
Supply: Vcc and RX2 (pins 1 1 and 13)
The TCA280A may be supplied by an external d.c. power supply connected to Vrjc (pin 11), butusually it is supplied directly from the mains voltage. For this purpose the circuit contains a string of
stabilizer diodes between Vqq and V^e that limit the d.c. supply voltage. An external resistor Rfj has
to be connected from the mains to RX2; Vgg is connected to the neutral line (see Figs 5 and 6). Asmoothing capacitor C1 has to be connected between Vqq and V^g. The circuit produces a positive
supply voltage at Vqq; this may be used to supply an external circuit such as a temperature sensing
bridge.
During the positive half of the mains cycles the current through external voltage dropping resistor Rjcharges the external smoothing capacitor C1 to the stabilizing voltage of the internal stabilizer diodes.
Rd should be chosen such that it can supply the current for the TCA280A itself (see Fig. 4) plus anycurrent taken up by an external (peripheral) circuit connected to Vqq, and recharge the smoothingcapacitor C1. Any excess current is bypassed by the internal stabilizer diodes. Note that the maximumrated supply current must not be exceeded.
During the negative half of the mains cycles external smoothing capacitor C1 supplies the circuit. Its
capacitance must be high enough to maintain the supply voltage above the minimum specified limit.
For values of Rjj and CI see Figs 5 and 6.
Dissipation in resistor R,j is halved by connecting a diode in series (see Figs 7 and 8). For phase control
applications this arrangement should always be used.
A suitable VDR connected across the mains provides protection of the TCA280A and of the triac
against mains-borne transients.
^\fFebruary 1983 191
TCA280A
FUNCTIONAL DESCRIPTION (continued)
Zero-crossing detector
The TCA280A contains a zero-crossing detector intended to produce pulses that coincide with the
zero crossings of the mains voltage for minimum r.f. interference and transients on the mams supply.
The pulse width control input PW (pin 1) permits adjustment of the pulse width at output QZ (pin 2)
to the value required for the triac by choosing the value of the external synchronization resistor RS
between PW and the a.c. mains. The pulse width is inversely proportional to the input current and to
the mains frequency.
The zero-crossing detector is inhibited when the ENZ input (pin 12) is HIGH, and it is enabled when
ENZ is LOW, e.g. connected to VEE .
Output QZ is an n-p-n open-collector output requiring an external collector resistor to Vcc .QZ
produces negative-going output pulses.
Comparator
IC+ and IC- (pins 5 and 6) are differential inputs of a comparator or difference amplifier, with QC+
and QC- (pins 4 and 7) as complementary outputs. QC+ and QC- are p-n-p open-collector outputs
requiring external collector resistors to VEE . QC+ will be HIGH and QC- will be LOW when IC+ is
higher than IC-.
The comparator contains a long-tailed pair with a current source in its tail. The tail current is activated
by a current into RX1 (pin 3). When an inductive load is driven with phase control the trigger pulse
may be terminated at the instant of firing of the thyristor or triac. This may be achieved by connecting
RX1 via a resistor to the anode of the thyristor or triac.
Sawtooth generator
The sawtooth generator may be used to produce bursts of trigger pulses, with the net effect that the
load is periodically switched on and off.
The heart of the sawtooth generator is a thyristor arrangement. The firing burst repetition time is
usually determined by an external resistor and capacitor connected to the sawtooth generator trigger
input IS (pin 14). The repetition time is typ. 0,7 x RC.
The output OS (pin 15) is an n-p-n open-collector output. During the flyback of the sawtooth the
transistor is ON and is capable of sinking current.
Output stage
The output stage is driven by a current drawn out of input IA (pin 9). This drive may be inhibited by
drawing a current out of inhibiting input INHA (pin 8). Hence the output will be HIGH only if
current is drawn out of IA and no current is drawn out of INHA i.e. if inhibiting input INHA (pin 8) is
HIGH and input IA (pin 9) is LOW. Both inputs may be used as a single input provided the other one is
suitably biased.
The output QA (pin 10) is an n-p-n open-emitter output capable of sourcing an output current, i.e.
conventional current flow out of the circuit.
A gate resistor R G should be connected between the output QA and the triac or thyristor gate to limit
the output current to the minimum required by the triac or thyristor. This minimizes the total supply
current and the power dissipation. Output QA is protected with a diode to V EE (pin 16) against damage
by undershoot of the output voltage, e.g. caused by an inductive load.
\r192 February 1983
General-purpose triggering circuit
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage (voltage source)
Supply current (current source)
average
repetitive peak
non-repetitive peak (t < 10 us)
Input voltage, all inputs
Differential input voltage between IC+and IC
Input current, all inputs
Output current
average
non-repetitive peak (t < 300 /js)
Total power dissipation
Storage temperature range
Operating ambient temperature range
vcc
TCA280A
17 V
!rX2(AV) max. 30 mAl RX2(RM) max. 80 mAl RX2(SM) max. 2 A
V| max. 17 V
V|D max. 7 V
l| max. 10 mA
-'QA(AV) max. 30 mA
-!qA(SM) max. 600 mAptot see Fig. 3
Tstg -55 to + 125 °C
lamb -20 to + 80 °C
1000
Ptot
(mw)
500
50 100 Tamb ( C) 150
Fig. 3 Power derating curve.
^\rFebruary 1983 193
TCA280A
CHARACTERISTICS
Vcc= 11 to 17 V;V EE = OV; I R X1 = 10 mA or —Irx1 = 30 MA; Tamb = 25 °C unless
otherwise specified.
— —' " —
parameter symbol min. typ. max. unit
Supply
Supply voltage, external vCc 11 - 17 V
Supply voltage, internally generated,
at l RX2(RMS)= 5 mA ,
unloaded vCc 11 14,3 15 V
Supply current, unloaded 'cc 0,3 - 0,75 mA
Variation with supply voltage AI CC/AVCC- - 0,03 mA/V
Pulse width control input PW (pin 1)
Input voltage
at lpw = 100 mA VpW — - 1,9 V
at -Ipw = 100 mA -Vpw - - 0,25 V
Input current at Iqz = 0,5 mA 'PWIRIVIS) 30 - 50 MA
Pulse width at Ipw(RMS) =^ mA;
f =50 Hz (at pin 2) tw — 190 - MS
Variation with supply voltage At/AV - 27 - ius/V
Zero crossing detector enable input ENZ (pin 12)
Input voltage
HIGH (inhibit) VENZH 1,2 - - V
LOW (enable) VENZL - - V
Zero crossing detector output QZ (pin 2)
Output current
HIGH !QZH — -1 MA
LOW ^ZL - - 40 mA
Comparator input IC + and IC- (pins 5 and 6)
Differential input voltage ±V| D™ - 7 V
Input bias current
at V|c+>V| C_+ 1 V hc + — 5 10 Mat V| C_> V| C + + 1 V 'IC-
- 5 10 MA
Comparator outputs QC+ and QC— (pins 4 and 7)
Output voltage at -Ioh = 0,3 mA V H Vcc--1,5 - - V
Output current
HIGH -'oh _ — 0,3 mA
LOW -lOL - — 90 nA
194 February 1 983~\r
General-purpose triggering circuit TCA280A
J \
CHARACTERISTICS (continued)
s
parameter symbol min. typ. max. unit
Sawtooth generator trigger input IS (pin 14)
Input trigger voltage V ISH 7 — 8,3 VInput trigger current Nsh - — 3 MAThyristor holding voltage VlSL 1,8 2,8 VThyristor holding current
'ISL 95 - 210 MSawtooth generator output QS (pin 15)
Output current
LOW'QSL - 5 mA
HIGH'QSH - 100 nA
Output stage inhibiting input IIMHA (pin 8)
Input current at -I|a = 100 /jA -'INHA 20 - 50 MAInput voltage at — '
IA = 100 mA V INHA vcc - 2 - V
Output stage input IA (pin 9)
Input current at -\q/\ = 200 mA -'IA 15 _ maInput voltage at -I|a = 50 mA V|A Vcc-8,3 - Vcc -7 V
Output stage output QA (pin 10)
Output voltage HIGH at -Iqah = 200 mA;Vcc= 13 V; INHAopen vQAH Vcc-2,8 - — V
Output current
HIGH-'qah - 200 mA
LOW at VQA =
— -
(QAL -1 MA
~\r.February 1983 195
TCA280A
7V20
'RX2IAV)
(mA|
15
3r
)
bVrT = 5V
4V
3V?E V2V
U
b
UT 1 in 200 [r
3UO
Fig. 4 Average supply current Irx2(AV) as a function of output current lQA with triac gate trigger
voltage Vqj as a parameter; typical performance.
196 February 1983
General-purpose triggering circuit TCA280A
i i i i i i i
7 8 9 10 11 12 13 14 15 16 17 18
! RX2(AV) lmA >
TCA280A = C1
Fig. 5 Voltage dropping resistor Rj, dissipation
p Rd in tnis resistor, and recommended minimumvalue of smoothing capacitor C1 as a functionof average supply current Irx2(AV). for the
supply arrangement without series diode. Notethat the supply current I RX2(AV) includes
the supply current of any external (peripheral)
circuit supplied from Vcc ; typical performance.
0,1}
I I
....
I
I
pnH =
^5W ...
-10 N
iANs\
-\-
\
^\
V
£N
R im
V N h VS(RMSs 1v* I ^/ 380 V
\ (~*s^ \ N *
-t£\ V ^ N
. 220V
l>\
^ h^i *^
l\\~
N_v
110V
90V
r ^ —. J \
i\\ ^J
2 *r
(
1
2 3 u 5 6 7 8 9 10 11 12 13
1r
. 1
X2{ AV)
r(m
18
A)[
Fig. 6 Voltage dropping resistor Rj and powerdissipation PRd in this resistor as a function ofsupply current I RX2(A V)- for tne supplyarrangement without series diode. Note that
'RX2(AV) includes the supply current of anyexternal (peripheral) circuit supplied from Vcc-Also shown is the r.m.s. mains supply voltage
<VS(RMS)> as a function of I RX2(AV)>' ^P' 031
performance.
=1
February 1983 197
TCA280A
1000
PRd(W)
Rd
(Ml)
C1
IxTOmF)
7Z6 999.2
t it^
-^"""T
~P><^_/ ^vi PinRdj==
/ '
—">^"~
y ^> tR <i™ -~
' /^/^
_[_1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
= C1
Fig. 7 Voltage dropping resistor Rj, dissipation
Pfjd in this resistor, and recommended minimum
value of smoothing capacitor C1 as a function of
average supply current Irx2(AV)* f° r tne su PP |v
arrangement with series diode D. IrX2(AV)-includes the supply current of any external
(peripheral) circuit supplied from VqC-
It should be noted that certain applications like
the time proportional controller require a value
of the smoothing capacitor C1 that is up to three
times higher; typical performance.
198
•®
February 1983
~\^
Fig. 8 Voltage dropping resistor Rd and power
dissipation Prj in this resistor as a function of
supply current Irx2(AV)- for tne SU PP'V arrange-
ment with series diode. Note that IrX2(AV)includes the supply current of any external
(peripheral) circuit supplied from Vrjc-
Also shown is the r.m.s mains supply voltage
(VS(RMS)> as a function ofI RX2(AV): typical
performance.
General-purpose triggering circuit TCA280A
oi-<
o
,_ >-
C T3 a.
c £ °C ™ COCD fn r-
C CC II
2 - 6t oiCD cc ^
co o uo r a;— vj _tn
a) to 3.> ^ Q.
s O >>
U)
f CMcc m II
b 1-CD (•)
ca ><r 4- *-<
CN
< C CJ
'a
ED c_) <l
O ECDIN
r CDr
m TJ H(J C CJ
a. O
.EP cS
•- > >LL en en
<O-Ia.
^rFebruary 1983 199
TCA280A
J V
oi-<
o
<u_lo.Q.<
>c
C in(0 0)
Oh Q.u h n (T
0)
CD53
0)
F
0)
c
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TO
r >03
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1- r r03 f ) <U tn r H
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2 &£ ^ a ,_0) ro O ro qj ^3 O cu O *-
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200 February 1983
General-purpose triggering circuit TCA280A
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^rFebruary 1983 201
TDA1023
PROPORTIONAL-CONTROL TRIAC TRIGGERING CIRCUIT
GENERAL DESCRIPTION
The TDA1023 is a bipolar integrated circuit for controlling triacs in the time proportional or burst
firing mode. It permits very precise temperature control of heating equipment and is especially suited
for the control of panel heaters. The circuit generates positive-going trigger pulses and complies with
the regulations on radio interference and mains distortion.
Special features are:
• adjustable proportional range width
• adjustable hysteresis
• adjustable trigger pulse width
• adjustable firing burst repetition time
• control range translation facility
• failsafe operation
• supplied from the mains
• provides supply for external temperature bridge
QUICK REFERENCE DATA
Supply voltage (derived from mains voltage)
Stabilized supply voltage
for temperature bridge
Supply current (average value)
Trigger pulse width
Firing burst repetition time at Cj = 68 ixF
Output current
Operating ambient temperature range
vCc
vz
h6(AV)
twTb
-'oh*
Tamb
typ. 13,7 V
typ.
typ.
typ.
typ.
max.
8 V
10 mA200 ms
41 s
150 mA-20 to + 75 °C
* Negative current is defined as conventional current flow out of a device. A negative output current
is suited for positive triac triggering.
PACKAGE OUTLINE
16-lead DIL; plastic (SOT-38).
^rAugust 1982 203
TDA1023
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204 August 1982~^r
Proportional-control triac triggering circuit TDA1023
PINNING
1 RpdR pd 1u
16 RX
2 n.c.
n.c. 2 15 n.c. 3 Q
Q 3 14 VCC4 HYS
5 PR
HYS [4_TDA1023
13 V EE 6 CI
7 URPR 5 12 TS 8 QR
CI 6 11 V29 BR
10 PW
UR 7 10 PW 11 Vz12 TB
QR 8 9 BR 13 VEE14 VCC15 n.c.
7Z85658
Fig 2 Pinning diagram. 16 RX
internal pull-down resistor connection
not connected
output
hysteresis control input
proportional range control input
Control input
unbuffered reference input
output of reference buffer
buffered reference input
pulse width control input
reference supply output
firing burst repetition time control input
ground connection
positive supply connection
not connected
external resistor connection
FUNCTIONAL DESCRIPTION
The TDA1023 generates pulses to trigger a triac. These trigger pulses coincide with the zero crossingsof the mains voltage. This minimizes r.f. interference and transients on the mains supply. The triggerpulses come in bursts, with the net effect that the load is periodically switched on and off. This furtherminimizes mains pollution. The average power in the load is varied by varying the duration of thetrigger pulse burst, in accordance with the voltage difference between the control input CI and thereference input, either UR or BR.
Power supply: Vcc , RX and Vz (pins 14, 16 and 1 1
)
The TDA1023 is supplied from the a.c. mains via a resistor R D to the RX connection (pin 16); theV EE connection (pin 13) is connected to the neutral line (see Fig. 4a). A smoothing capacitor Cc hasto be connected between the Vcc and V E e connections.
The circuit contains a string of stabilizer diodes between the RX and V EE connections that limit thed.c. supply voltage, and a rectifier diode between the RX and Vcc connections (see Fig. 3).
At pin 11the device provides a stabilized reference voltage Vz for an external temperature sensing
bridge.
The operation of the supply arrangement is as follows. During the positive half of the mains cycles thecurrent through external voltage dropping resistor R D charges the external smoothing capacitor Csuntil RX reaches the stabilizing voltage of the internal stabilizer diodes. R D should be chosen such thatit can supply the current l cc for the TDA1023 itself plus the average output current l3(AV )
plus thecurrent required from the Vz connection for an external temperature bridge, and recharge thesmoothing capacitor Cs (see Figs 9 to 1 2). Any excess current is bypassed by the internal stabilizerdiodes. Note that the maximum rated supply current must not be exceeded.
During the negative half of the mains cycles external smoothing capacitor Cs has to supply the sum ofthe currents mentioned above. Its capacitance must be high enough to maintain the supply voltageabove the minimum specified limit.
August 1982 205
TDA1023
FUNCTIONAL DESCRIPTION (continued)
Dissipation in resistor Rrj is halved by connecting a diode in series (see Fig. 4b and 9 to 12),
A further reduction of dissipation is possible by using a high-quality voltage dropping capacitor Cq in
series with a resistor R$d (see Figs 4c and 14). Asuitable VDR connected across the mains provides
protection of the TDA1023 and of the triac against mains-borne transients.
Control and reference inputs CI, BR and UR (pins 6, 9 and 7)
For room temperature control (5 °C to 30 °C) the best performance is obtained by using the
translation circuit. The buffered reference input BR (pin 9) is used as a reference input, and the output
of the reference buffer QR (pin 8) is connected to the unbuffered reference input UR (pin 7). In this
arrangement the translation circuit ensures that most of the potentiometer rotation can be used to
cover the room temperature range. This provides an accurate temperature setting and a linear
temperature scale.
If the translation circuit is not required, the unbuffered reference input UR (pin 7) is used as a
reference input. The buffered reference input BR (pin 9) must be connected to the reference supply
output Vz (pin 11).
For proportional power control the unbuffered reference input UR (pin 7) must be connected to the
firing burst repetition time control input TB (pin 12) and the buffered reference input BR (pin 9),
which is inactive now, must be connected to the reference supply output Vz (pin 1 1 ).
In all arrangements the train of output pulses becomes longer when the voltage at the control input
CI (pin 6) becomes lower.
Proportional range control input PR (pin 5)
With the proportional range control input PR open the output duty factor changes from 0% to 100%
by a variation of 80 mV at the control input CI (pin 6). For temperature control this corresponds with
a temperature difference of only 1 K.
This range may be increased to 400 mV, i.e. 5 K, by connecting the proportional range control input
PR (pin 5) to ground. Intermediate values are obtained by connecting the PR input to ground via a
resistor R5, see Table 1.
Hysteresis control input HYS (pin 4)
With the hysteresis control input HYS (pin 4) open the device has a built-in hysteresis of 20 mV. For
temperature control this corresponds with 0,25 K.
Hysteresis is increased to 320 mV, corresponding with 4 K, by grounding HYS (pin 4). Intermediate
values are obtained by connecting pin 4 to ground via a resistor R4. See Table 1 for a set of values for
R4 and R5 giving a fixed ratio between hysteresis and proportional range.
Trigger pulse width control input PW (pin 10)
The trigger pulse width may be adjusted to the value required for the triac by choosing the value of
the external synchronization resistor Rg between the trigger pulse width control input PW (pin 10)
and the a.c. mains. The pulse width is inversely proportional to the input current (see Fig. 13).
Output Q (pin 3)
Since the circuit has an open-emitter output, it is capable of sourcing current, i.e. supplying a current
out of the output. Therefore it is especially suited for generating positive-going trigger pulses. The
output is current-limited and protected against short-circuits. The maximum output current is 1 50 mA
and the output pulses are stabilized at 10 V for output currents up to that value.
~~^r206 August 1982
Proportional-control triac triggering circuit TDA1023
FUNCTIONAL DESCRIPTION (continued)
A gate resistor Rq must be connected between the output Q and the triac gate to limit the outputcurrent to the minimum required by the triac (see Figs 5 to 8). This minimizes the total supply current
and the power dissipation.
Pull-down resistor R pc|(pin 1)
The TDA1023 includes a 1,5 kfi pull-down resistor R pcj between pins 1 and 13 (Vgff, groundconnection), intended for use with sensitive triacs.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage, d.c. Vcc max. 16 VSupply current
average'16(AV)
repetitive peakll 6(RM)
non-repetitive peak hfi(SM)
Input voltage, all inputs V|
Input current, CI, UR, BR, PW input lg. 7. g. ^Voltage on R pcj connection V-]
Output voltage, Q, QR, Vz output V3. o. 1
1
Output current
average -"OH(AV)peak, max. 300 us — 'OHIM)
Total power dissipation
Storage temperature range
Operating ambient temperature range
Ktot
Tstg
Tamb
max. 30 mAmax. 100 mAmax. 2 A
max. 16 V
max. 10 mAmax. 16 V
max. 16 V
max. 30 mAmax. 700 mAmax. 500 mW-55 to + 150 °C
-20 to + 75 °C
^rAugust 1982 207
TDA1023
CHARACTERISTICS
Vcc =1 1 to 16 V; Tamb = -20 to + 75 °C unless otherwise specified
symbol
Supply: Vcc and RX (P'ns 14 and 16 '
Internally stabilized supply voltage
at 1 1 6= 10 mA
Variation with l*|@
Supply current at V-|6-13 = 11 to 16 V;
l 10= 1 mA;f = 50 Hz; pin 11 open;
v6-13 -> v7-13 ;pins 4 and 5 open
pins 4 and 5 grounded
Reference supply output Vz (pin 1 1
)
for external temperature bridge
Output voltage
Output current
Control and reference inputs CI, BR and UR
(pins 6, 9 and 7)
Input voltage to inhibit the output
Input current at V| = 4 V
Hysteresis control input HYS (pin 4)
Hysteresis, pin 4 open
pin 4 grounded
Proportional range control input PR (pin 5)
Proportional range, pin 5 open
pin 5 grounded
Pulse width control input PW (pin 10)
Pulse width at ho(RMS)=
1 mA: f = 50 Hz
Firing burst repetition time control input TB
(pin 12)
Firing burst repetition time,
ratio to capacitor Cy
Output of reference buffer QR (pin 8)
Output voltage
at input voltage Vg.13 = 1,6 V
Vg.i 3 = 4,8V
V9. 13 = 8 V
VCC
AVcc/All6
•16
"16
Vn-13
-111
V6-13
'6; 7; 9
AV6AV6
AV<5
AV6
Tb/CT
V8-13
V8-13
v8-13
mm. typ.
12
50
100
13,7
30
7,6
20
320
80
400
max.
15
6
7,1
40
130
200 300
320 600 960
3,2
4,8
6,4
unit
V
mV/mA
mA
mA
V
mA
V
»A
mVmV
mVmV
MS
ms/lJ.F
V
V
V
208 August 1982-^r
Proportional-control triac triggering circuit TDA1023
symbol min. typ. max. unit
Output Q (pin 3)
Output voltage HIGH at-lrjH = 15° mA V H 10 - - V
Output current HIGH -'OH - - 150 mA
Internal pull-down resistor Rpj (pin 1)
Resistance to V^e RPd 1 1,5 3 kft
Table 1. Adjustment of proportional range and hysteresis.
Combinations of resistor values giving hysteresis > % proportional range.
proportional proportional minimum maximumrange range hysteresis hysteresis
resistor R5 resistor R4mV kft mV kfi
80 open 20 open160 3,3 40 9,1
240 1,1 60 4,3
320 0,43 80 2,7
400 100 1,8
Table 2. Timing capacitor C-p values.
effective marked a.c. catalogue
d.c. value specification number*
MF V
68 47 25 2222 016 9012947 33 40 - - 9013133 22 25 - 015 9010222 15 40 - - 9010115 10 25 - - 9009910 6,8 40 - - 90098
* Special electrolytic capacitors recommended for use with TDA1023.
~^rAugust 1982 209
TDA1023
J VRX
16
©©©©STABILIZER
Fig. 3 Internal supply connections.
Rr> ' 03C* LD {heater) t
TDA1023 Q
a.c.a.c. mains
Itage
7Z85660.1
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zTDA1023 Q±AW
rv a -c-
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.c. mains
oltage
S
Fig. 4 Alternative supply arrangements.
210 August 1982^r
Proportional -control triac triggering circuit TDA1023
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August 1982 211
TDA1023
yv.7Z71707.2
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212 August 1982~\r
Proportional-control triac triggering circuit TDA1023
Fig. 13 Synchronization resistor Rg as a
function of required trigger pulse width twwith mains voltage Vg as a parameter.
15 20
'l6(AV| lmA '
Fig. 14 Nominal value of voltage dropping
capacitor Crj and power Prsd dissipated in
voltage dropping resistor Rgo as a function
of the average supply current li6(AV) witn
the mains supply voltage Vg as a parameter.
^rAugust 1982 213
TDA1023
APPLICATION INFORMATION
Vcc FIX PW
TDA1023
I
R,
"EJ 7 4 5
54
load r
(heater) E
a.c. mamsvoltage
Fig. 15 TheTDA1023usedina 1200 to 2000 W heater with triac BT1 39. For component values
see Table 3.
Conditions
Mains supply: V$ = 220 V
Temperature range = 5 to 30 °C
BT139data: Vgt<1.5Vl GT >70mA atTj = 25°C
l L <60mA
214 August 1982^r
Proportional -control triac triggering circuit TDA1023
Table 3. Temperature controller component values (see Fig. 15).
parameter symbol value remarks
Trigger pulse width tw 75 lis see BT139 data sheet
Synchronization resistor Rs 180 k$2 see Fig. 13
Gate resistor Rg 110 n see Fig. 6
Max. average gate current '3(AV) 4,1 mA see Fig. 8
Hysteresis resistor R4 n.c. see Table 1
Proportional band resistor R5 n.c. see Table 1
Min. required supply current h6(AV) 11,1 mAMains dropping resistor Rd 6,2 kfl see Fig. 10
Power dissipated in Rrj Prd 4,6 W see Fig. 10
Timing capacitor (eff. value) cT 68 mF see Table 2
Voltage dependent resistor VDR 250 V a.c. cat. no. 2322 593 62512
Rectifier diode D1 BYW56
Resistor to pin 1
1
R1 18,7 ka 1% tolerance
NTC thermistor (at 25 °C) RNTC 22 kO. B = 4200 Kcat. no. 2322 642 12223
Potentiometer Rp 22 kO
Capacitor between pins 6 and 9 C1 47 nF
Smoothing capacitor cs 220/jF; 16 V
If Rq and D1 are replaced by Crj and RSDMains dropping capacitor CD 470 nF
Series dropping resistor Rsd 390 a see Fig. 14
Power dissipated in R$d P RSD 0,6 WVoltage dependent resistor VDR 250 V a.c. cat. no. 2322 594 62512 =Notes
1. ON/OFF control: pin 12 connected to pin 13.
2. If translation circuit is not required: slider of Rp to pin 7; pin 8 open; pin 9 connected to pin 11.
APPLICATION INFORMATION SUPPLIED ON REQUEST
^rAugust 1982 215
TDA1024
ON-OFF TRIAC TRIGGERING CIRCUIT
GENERAL DESCRIPTION
The TDA1024 is a bipolar integrated circuit delivering positive pulses for triggering a triac or athyristor. It is primarily intended for use as a static switch to replace mechanical thermostats thatswitch resistive loads, such as:
• central heating installations
• washing machine heaters
• water heaters
• smoothing irons
The TDA1024 provides its own d.c. supply and will supply an external circuit, e.g. a temperaturesensing bridge. The circuit complies with the regulations on radio interference and mains distortion.
Its main features are:
• adjustable trigger pulse width
• adjustable hysteresis
• supplied from the mains
• provides supply for external temperature bridge
• protected inputs and output
• low supply current, low dissipation
QUICK REFERENCE DATA
Supply voltage (d.c.)
(internally derived from mains voltage)
Supply current (average value, unloaded)
Output current HIGH
Output pulse width
Power dissipation (unloaded)
Operating ambient temperature range
Vcc typ- 6,5 V
'RX(AV) max. 1,8 mA-IrjH* max- 100 mAtw typ. 195 ms
P typ. 12 mW1 amb -20 to +80 °C
Negative current is defined as conventional current flow out of a device. A negative output current is
suited for positive triac triggering.
PACKAGE OUTLINE
8-lead DIL; plastic (SOT-97A).
February 1983 217
TDA1024
REF-
HYS-
ZEROCROSSINGDETECTOR
INPUTBUFFER ^ IT
POWERSUPPLY
CONTROLGATE
£*
Fig. 1 Block diagram.
TDA1024
OUTPUTAMPLIFIER
VEE
vee \T O T] vCc
q QT
HYS [T*TDA1024
~7~| RX
6 ] PW
REF fT" T1 CI
Fig. 2 Pinning diagram.
NING
1 V E E ground
2 Q output
3 HYS hysteresis control input
4 REF reference input
5 CI control input
6 PW pulse width control input
7 RX external resistor
8 vcc positive supply
218 February 1983^
On-off triac triggering circuitTDA1024
J V
~\rFebruary 1983 219
TDA1024
FUNCTIONAL DESCRIPTION
The TDA1024 generates positive-going output pulses to trigger a triac. These trigger pulses coincide with
the zero crossings of the mains voltage. This minimizes r.f. interference and transients on the mains
supply.
Supply: Vcc ar|d RX (pi ns 8 and 7)
The TDA1024 may be supplied by an external d.c. power supply connected to Vcc (P in 8h Dut usually
it is supplied directly from the mains voltage. For this purpose the circuit contains a stabilizer diode
between RX and Vee that limits the d.c. supply voltage (see Fig. 4). An external resistor Rrj has to be
connected from the mains to RX (pin 7); Vee is connected to the neutral line (see Fig. 5a). A smooth-
ing capacitor Cg has to be connected between Vcc and VEE-
During the positive half of the mains cycles the current through external voltage-dropping resistor Rdcharges the external smoothing capacitor Cg up to the stabilizing voltage of the internal stabilizer
diodes. Rd should be chosen such that it can supply the current Ice f° r tne TDA1024 itself plus the
average output current — lQ(AV)' ar|d recharge the smoothing capacitor Cg. Any excess current is
bypassed by the internal stabilizer diode. Note that the maximum rated supply current must not be
exceeded.
During the negative half of the mains cycles external smoothing capacitor Cg supplies the circuit. Its
capacitance must be high enough to maintain the supply voltage above 5 V, the minimum specified
limit (see Fig. 10).
Dissipation in resistor Rq is halved by connecting a diode in series (see Figs 5b and 1 1 ).
A further reduction of dissipation is possible by using a high-quality voltage-dropping capacitor Crj in
series with a resistor Rgrj ( see Figs 5c and 12).
A suitable VDR connected across the mains provides protection of the TDA1024 and of the triac
against mains-borne transients.
Control and reference inputs CI and REF (pins 5 and 4)
The TDA1024 produces output pulses when the CI input is at a higher potential than the REF input.
For power control as a function of temperature the inputs may be connected as shown in Fig. 14.
An input buffer circuit at the CI input gives a high input impedance and a low output impedance. This
makes the hysteresis of the circuit independent of the input voltage.
Hysteresis control input HYS (pin 3)
With the hysteresis control input HYS open the device has a built-in hysteresis of 20 mV. For
temperature control this corresponds with a temperature difference of 0,25 K.
Hysteresis is increased to 300 mV, corresponding with a temperature difference of 4 K, by grounding
HYS. Intermediate values are obtained by connecting HYS to ground via a resistor.
Pulse width control input PW (pin 6)
The output pulse width may be adjusted to the value required for the triac by choosing the value of the
external synchronization resistor Rg between the pulse width control input PW and the a.c. mains. The
pulse width is inversely proportional to the input current (see Fig. 13).
Output Q (pin 2)
Since the circuit has an open-emitter output, it is capable of sourcing current, i.e. supplying a current
out of the output. Therefore it is especially suited for generating positive-going trigger pulses. The
output is current-limited and protected against short-circuits. The maximum output current is 100 mAand the output pulses are stabilized at 4 V for output currents up to that value.
220 February 1983r
On-off triac triggering circuit TDA1024
FUNCTIONAL DESCRIPTION (continued)
Output Q (pin 2) (continued)
A gate resistor Rq must be connected between the output Q and the triac gate to limit the output
current to the minimum required by the triac (see Figs 6 to 9). This minimizes the total supply current
and the power dissipation.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage (d.c.)
Supply current
average
repetitive peak
non-repetitive peak (t < 50 us)
Input voltage (all inputs)
Input current (CI, REF, PW)
Output voltage HIGH
Output current
average
peak, max. 300 ^s
Total power dissipation
Storage temperature range
Operating ambient temperature range
VCC 8 V
'RX(AV) max. 30 mA
'rxirmi max. 80 mA
'RX(SM) max. 2 A
V| max. 8 V
ci; 'ref; * 'pw max. 10 mAvQ max. 8 V
-'OHIAV) max. 30 nvA
-'OH(M) max. 400 mAptot max. 225 mWTstg -55 to + 125 °C
"Tamb -20 to + 80 °C
rFebruary 1988 221
TDA1024
^yvCHARACTERISTICS
VCC = 5to8V;Tamb = -20 to +80 °C unless otherwise specified.
Supply: Vcc and RX (pins 8 and 7)
Internally stabilized supply voltage
atl RX(AVj =1° mA
variation with Ipx
Supply current at Vqq = 5,5 V; >
unloaded; f = 50 Hz; Vrj| > Vrefpin 3 open (minimum hysteresis)
Supply current increase
pin 3 grounded (maximum hysteresis)
Control and reference inputs CI and REF(pins 5 and 4)
Input current, CI input, at Vci > VrefInput current, REF input, at Vref > Vci
Hysteresis control input HYS (pin 3)
Hysteresis,
pin 3 open (minimum hysteresis)
pin 3 grounded (maximum hysteresis)
Pulse width control input PW (pin 6)
Pulse width at Ipw(RMS) = 1 mA ;
Vcc = 5,5 V; f = 50 Hz
Output Q (pin 2)
Output voltage HIGHat-lQH = 100 mAat —Iqh = 1 mA
Output current HIGH
symbol min
vccAVCCMI RX
'RX(AV)
a'rX(AV)
'CI
'REF
AVC|-REFAVci-REF
typ.
5,5 6,5
15
1,4
V H
V H
-'oh
10
150
130
20
300
195
7,5
1,8
30
500
265
unit
V
mV/mA
100
mA
mA
MA
mVmV
/is
V
V
mA
222 > February J9S3\/T
On-off triac triggering circuit
Fig. 4 Internal supply connections.
TDA1024
load J
( heater)]
t r ax mainsvoltage
BCs
Vcc RX
TDA1024 Q
ve'e
^^ r\R5H -u
I'
toad r( heater)£
l^MMCvoltage
VS
(b)
load f
(heater) C
CS
ICD
Vcc RX
TDA1024 Q^^Woa e mainsvoltage
Vs
(0
Fig. 5 Alternative supply arrangements.
~\rFebxuairyJ983-:
i 223
TDA1024
1
> 7Z726H1
20a mini'i
"vr— H l «\ -1 "V 's ""
(A. i irtc^v-KICITA
*„ nQEJ^^L.UEItLtiMQAA >\Min^^A:p\£\:vvS
tnn \ft\ I V \ '._<_> V00 ^m\:cs> ^ ^^scm;:^\%^
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^s 5* ~~ "** "^l "*"a_ ~~ll~~
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~~~~
Rs=68kJl 82 100 120 «d_ 180 220
n — - —- —— IJ-I—' ' ' ' '—'—* ' '' '
—L—-'—'
—
10 -Io(AV><mA)15
Fig. 6.
200 f-n W \ \ Vs = 220 V
p 11 n ^ v NK —(ill m\v\\ \
row \\uu vv N1QI \\ \ s
flaw \
itCAVSficiSSav3KW .1MfT—
I\ \\'
/ 820 kHW.680-+-66^560^»». ^"—-^
,^-~-^, -__-
»«. ^^"«~ :" y '' "~ ** —.
^.;'Rs=120kn 150 180 220 270 3 30 390 470
oL<--: n: "
Fig.7.
10 -Io(AV)l'nA)1S
224 February, ;1 983
On-off triac triggering circuit TDA1024
200
UU
150
100
50
\ \w \\ \ \Vs =i«jv
L>\
In \ \ VM \ \I
1
>
L
III \ \\\ A \
\\\vI m\\'
\\Y\u\ r> *
^ .820
,680/,
Rs=120kn 150 180 220 270 330 390 470
I I I —10 -I Q ,AV)
(mA) 15
Fig. 8.
200
(A)
150
100
50
I m A \
L, - VS = 380VP \i V
1\ \\ J
uVA i
W \ V
\\WW i' ^
L_
\wr ^s. \
\ ^\ sV ,1.8
,1,b
.1,2A
/// a Mn7 5s-
Rs=270kn 330 390 470 560 680 820
1 1
10
Fig. 9.
-I Q(AV)(mA)15
\rFebruary 1983 225
TDA1024
7Z72634.1
\
\\
16\
\1
,
\
\I ._
'Dmax \km \\ }
Ul\
\ \\12
I \l1 y\I u
i\\\ c\
n
\i
lUm
\vs- i
8 \J su V ^
1
i
i_i
y \ l
\ >,240Vs
i
V y. \\ v s^— •mA
??nv
4 i
i
i
imv
n
1200
C5
(uF)
800
400
20 I R ImA) 30
Fig. 10 Maximum value of voltage-dropping resistor Rrj as a function of minimum value of the current
into RX with the mains supply voltage Vg as a parameter for the supply arrangements of Figs 5a and
5b, and recommended value of smoothing capacitor C§ as a function of the current into RX for all
three supply arrangements of Fig. 5. When Vrjc is used to supply external circuitry such as a tempera-
ture-sensing bridge, the current required by that external circuitry should be added to I RXmin-
226 February 1983^r
On-off triac triggering circuit
;vTDA1024
r"7Z72633.1
i — with diode-
j\ — without diode
20ht~3
L L_
i_R0 _ i
TW)
--1" T c" i ^
l_
15 _::_[u._] 11 r V
J XX. i _ £•+ J 3
I H ^ -i
-I -3_t_: k.
Xr- ^ LA. _y ,
11 t4V-4l A\r43 n.
10 It -£n £_ - V —I 5 ^.31 -V- -
t^ 1 ^-^ - -^V -
it V - *- J \_J4- j \ S \
3 x\_S_IX ^ v 5 . ^13 S S_ \
L J_ £ % ^ s
X £3 \ ^ : >»
5_i j^ - v-% *"
S\ i ^ s«.
A % \ S H v «,C i " -
^ \ S.-*. ^v * •= „ 380 V
r ^r 5» s s --- Tt-
3 s __ I^Ss.S •4.1
S ^: : ^ C. 22nv~ 240 V
\ c <^ J s^ >—
-
0V L= 240V110 V i
n-'
i i \1 1 1
10 20 RD <kA)30
Fig. 1 1 Power dissipated in voltage-dropping resistor Rrj as a function of its value with the mains
supply voltage Vg as a parameter, for the supply arrangements of Figs 5a and 5b.
^rFebruary 1983 227
TDA1024
1000
r RSD(mW)
500
,
VRS[3
' \/r =
220 V1j
/
/ / /240V
/ ,/ /r
1
f ^ *1 //
'/
Lf/r
'A'
J 7i
/ir
A7/>/
/ />' '
I/
1000
ConF)
500
10 20 30
iRXmintmAI
Fig. 12 Power dissipated in voltage-dropping
resistor Rsd and dropping capacitor Cp as a
function of the minimum current into RX with
the mains supply voltage Vg as a parameter, for
the supply arrangement of Fig. 5c. When Mqq,
is used to supply external circuitry such as a
temperature-sensing bridge, the current
required by that external circuitry should be
addedtolRXmin-
7272625.1
I I I
Vs = 3801000
V^•>40 \i.
,
r
.
fj]I
J / "/220 V
/r
_iks
/(kll)
f
500110V
(
I
250 500tw (us)
750
Fig. 13 Synchronization resistor Rg as a
function of required trigger pulse width twwith mains supply voltage Vg as a parameter.
2^8 February 1983\r
On-off triac triggering circuit
APPLICATION INFORMATION
TDA1024
I^cs
RNTCfV Rp
DRs U rd
OOnF:c
"
vcc RxPW
ci
REF
HYS
TDA1024 Q
resistive
load
1200WI
BT138, _
ax. mainsvoltage
Fig. 14 Typical application of the TDA1024 in a 1200 W thermostat covering the temperature range 5
to 30 °C. For component values seeTable 1
.
Conditions
Mains supply voltage Vg(RMS) = 220 V
Temperature range: 5 to 30 °C
BT138 data: VGT < 1,5 V >
lGT > 70 mA atTj = 25°Cl L < 60mA J
^rFebruary 1:983 229
tDA1024
Table 1
Temperature controller component values (see Fig. 14)
parameter symbol value remarks
Trigger pulse width tyy 105/w see BT138 data sheet
Synchronization resistor RS 180 kn see Fig. 13
Gate resistor Rg 33 ft see Fig. 7
Average output current '(KAV) 3,7 mA
Mint required supply current !RX(AV) 6,5 mA
Voltage-dropping resistor Rd 10kft see Fig. 10
Power dissipated in Rrj> pRD 3,2 W see Fig. 11
Voltage dependent resistor VDR 250 V a.c. cat. no. 2322 593 62512
Rectifier diode D1 BYW56
NTC thermistor (at 25 °C) RNTC 22 kft B = 4200 Kcat. no. 2322 642 12223
Smoothing capacitor cs 220 mF; 16 V
If Rrj and 01 are replaced by Crj and Rsd
Voltage-dropping capacitor cD 270 nF
'Series dropping resistor RSD 390 nPower dissipated in Rsq PRSD 190 mWVoltage dependent resistor VDR 250 V a.c. cat. no. 2322 594 62512
\ £§ w:
\ § fc ^ *-
w CSsaSv;;.v<s -A^S^^s.., --
[ S's^k.^ "^ ^.*^ s> ^
3 uv'vW s^->.j8n.
V l\v^^I\ Ss__ f 5V^5^% ^&
J as\%% s ^ Sf 5> ^ ^ S
v Si"3 \S S \\ r^
_ _ ^ 3 i, ^ ^ v SJ3- £ \ v\ \ S
::^ 3 vs \ \J: . ^ !v, \ ^m_
TDA1024
2 1
t
Vq UL7Z7424Sj3»P
Fig. 15 Gate voltage (Vq) as a function of trigger
current (Iq) with gate resistor (Rq) load lines.
soI (mA) WO
230 February 1983^r
DEVELOPMENT SAMPLE DATAThis information is derived from development samples
made available for' evaluation. It does not necessarily
imply that the device will go into regular production.
TEA1010TEA1010T
TOUCH-CONTROLLED LAMP DIMMER CIRCUIT
GENERAL DESCRIPTION
The TEA1010 is a bipolar integrated circuit for switching and regulating lamps and other loads with a
minimum of external components. It provides ON/OFF switching and a physiological power regulation
(equal brightness steps). It is suited for touch plates and for switches, and may combine local and
remote control. It produces negative pulses to drive a triac. The circuit is suited for resistive and fpr
inductive loads, i.e. it is not only suited for dimming lamps but also for regulating motors in fans,
vacuum cleaners, etc.
The TEA 1010 and TEA1010T switch on at the maximum brightness level upon a brief touch of the
contacts.
The circuits feature:
— Alternative ON/OFF switching by a brief touch of one or both contacts.
— ON switching at minimum brightness by a long touch of one or both contacts.
— Gradual change to maximum brightness during a long touch of the UP contact.
— Gradual change to minimum brightness during a long touch of the DOWN contact.
— No action during a long touch of both contacts in the ON state.
QUICK REFERENCE DATA
Supply voltage, d.c. (derived from mains voltage)
Supply current
Output current
Firing phase range
Time to change from minimum to maximumbrightness, or vice versa
Power dissipation in the ON state
Operating ambient temperature range
vcc typ. 15 V
ice typ. 1 mA
'0 max. 100 mA
f typ. 30° to 140°
tv typ. 3,8 s
p typ. 19 mW
Tamb to + 85 °C
PACKAGE OUTLINE
TEA1010 : 8-lead DIL; plastic (SOT-97C2).
TEA1010T:8-lead mini-pack; plastic (SO-8;SOT-96AC1).
~\fFebruary 1983 231
TEA1010TEA1010T
FUNCTIONAL DESCRIPTION
The TEA10T0 generates negative output pulses to trigger a triac. These output pulses are phase shifted
with respect to the mains voltage. The amount of phase shift is determined by the difference between
the initial states of two 7-bit counters. Both counters are driven by the same clock pulse generator.
One of the counters is preset to a number determined by the required phase angle. The higher the
required brightness, the smaller the required phase angle, the lower the number to which the counter
is preset. The relation between brightness and preset number has been chosen so that almost equal
brightness steps are obtained (physiological control). The minimum phase shift corresponds with 32
dock pulses and the maximum with 160.
Upwards and downwards regulation inputs UP and DN (pins 7 and 6)
At 50 Hz mains frequency the device ignores signals with a duration of less than 80 ms and signals with
a duration of 80 to 320 ms are accepted as brief commands, these cause the ci rcuit to switch on and off
alternatively. Signals that last longer than 320 ms are interpreted as long commands. A long commandvia the UP input causes the output phase angle to decrease, i.e. the brightness to increase gradually; a
long command via the DN input has the opposite effect. A long signal on both inputs will switch on the
lamp at minimum brightness. If the lamp is already on, a long signal on both inputs will have no effect.
The UP and DN inputs may be activated by touch plates or by switches. For the input arrangements
see Fig. 2.
Slave input SLV (pin 2)
The SLV input operates in the same manner as the UP and DN inputs, but with a two-wire connection,
ideal for remote control. The SLV input is only suited for switches. For the arrangement see Fig. 3.
If the SLV input is not used it must be connected to the load via a 1 ,5 Mfi resistor (see Fig. 4).
Oscillator RC pin OSC (pin 1)
The frequency of the clock pulse generator is determined by an external resistor and capacitor, both
connected to the OSC terminal (see Fig. 4). The generator switches at levels equal to 1/6 and 1/2 of
the difference between the injector voltage Vjnj and the supply voltage Vrjc- The clock pulse period
is about 50 fts.
Output Q (pin 3)
Since the circuit has an open-collector output, it is capable of sinking current, i.e. drawing a current
into the output. Therefore it is especially suitable for delivering negative trigger pulses.
The maximum output current is 100 mA. A gate resistor Rq must be connected between the output Qand the triac gate to limit the output current to the minimum required by the triac (see Fig. 4). This
minimizes the total supply current and the power dissipation.
A negative-going trigger pulse is generated at the output after every zero crossing of the mains voltage.
The output pulse has a maximum duration of one clock pulse period, i.e. 50 /is. To reduce the powerdissipation the output pulse is terminated as soon as the triac has switched on.
Supply Vcc and Vee <Pins 8 and 4)
The TEA1010 is supplied from the a.c. mains via a capacitor Crj and a diode to Vee; VCC 's connectedto the line (see Fig. 4). A smoothing capacitor Cs has to be connected between Vrjrj and Vee- Tne.circuit contains a string of stabilizer diodes between Vrx and Vee tnat lirnit tne d.c. supply voltage.
During th« positive half of the mains cycles the current through external voltage dropping capacitor
Crj charges the external smoothing capacitor Cs up to the stabilizing voltage of the internal stabilizer
diodes. Cp should be chosen such that it can supply the current Iqc for the TEA1010 itself plus the
average output current l3(AV)- and recharge the smoothing capacitor Cs-
232 February 1983
Touch-controlled lamp dimmer circuit TEA1010TEA1010T
Any excess current is bypassed by the internal stabilizer diodes. Note that the maximum rated supply
current must not be exceeded.
During the negative half of the mains cycles external smoothing capacitor C§ supplies the circuit. Its
capacitance must be high enough to maintain the supply voltage above the minimum specified limit.
A supply voltage at Vgg that is negative with respect to Vrjrj and the line is developed at the Vgg pin.
Note that in the characteristics the voltages are mainly measured with respect to Vgg and not with
respect to V^c and the line. '
The circuit has an internal power-on reset, which forces the circuit into the OFF state.
Synchronization input SYN (pin 5)
The connection to the SYN input should be short and must be decoupled via a capacitor to Vqc (P>n 8).
PINNING
osc n* U T| vcc
< SLV|T T"|upTEA1010
<QUJ
o (T 6 |DN
vEE [T T"]SYN
S35
7Z89709
HZHi
S Fig. 1 Pinning diagram.
oUl RATINGS>
1 OSC oscillator (RC)
2 SLV slave input
3 Q output
4 VFF common5 SYN synchronization input
6 DN downward regulation input
7 UP upward regulation input
8 vCc positive supply
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage range, d.c. VqC —0,5 to + 18 V
Supply current, d.c. IfX max. 20 mApeak, max. 10 /us 'CCM max - 0»5 A
Input voltage range, all inputs V| —0,5 to + 18, V -
Input current, all inputs ± l| max. 20 mAOutput voltage range Vq -0,5 to + 18 V
Output current range Iq —20 to + 150. mAPower dissipation Ptot max. 250 mWStorage temperature range T^g —55to + 125°C
Operating ambient temperature range TamD to +85 °C
~\rFebruary 1983 233
TEA1010TEA1010T
CHARACTERISTICS
Vcc = 5 to 18 V; Tamb = to + 85 °C
parameter symbol min. typ. max. unit
Supply Vcc (P'n 8 '
Internally stabilized supply voltage,
at lcc = 1 '5to20mA vcc 13,3 15 16,8 V
Supply current at Vcc = 15 V, unloaded,
OFF state 'cc_ 1 1,2 mA
ON state ice - 1,25 1,5 mAPower dissipation, unloaded,
OFF state p — 15 _ mWON state p - 19 25 mW
Thermal resistance
TEA1010 Rth j-a_ 162 K/W
TEA1010T(note1) Rth j-a- 140 - K/W
TEA1010T (note 2) Rth j-a
- 220 - K/W
Power-on reset threshold voltage vCCpor - - 4,8 V
Oscillator RC pin OSC (pin 1
)
Injector voltage Vinj 550 - 700 mV
Synchronization input SYN (pin 5)
Input current (r.m.s. value) '5(rms) 3 - - AtA
Upwards and downwards regulation
inputs UP and DN (pins 7 and 6)
Input voltage V6-4;V7 -4 1 - - V
Input current -'e;-'7 - 3 ^(rms)- MA
Slave input SLV (pin 2)
Input current ±l2 10 - - /xA
Output Q (pin 3)
Output current '3 - - 100 mA
Notes
1. TEA1010T mounted on a ceramic substrate of 50 x 50 x 0,7 mm.
2. TEA1010T mounted on a printed-circuit board of 50 x 50 x 1,5 mm.
234 February 1983\r
Touch-controlled lamp dimmer circuit TEA1010
TEAKMOT
R between 150S2 and 390kn
<QUJ_ia.
S<HZUJ
Sa.
O-iUJ
>UJa Fig. 2 Alternative arrangements for the UP and DN inputs.
®& 6*.
Fig. 3 SLV input arrangement.
A^F«bruary1983 2*
TEA1010TEA1010T
APPLICATION INFORMATION
touch 120knplates
(1
)
The connection to the SYN input should be short and must be decoupled near to pins 5 and 8.
(2) For example, Vakuumschmelze FD 2.5 1 N1 KN.
Fig. 4 Touch-controlled lamp dimmer circuit for max. 450 W. L1 and C1 form a radio-frequency
interference filter with a quality factor Q of less than 1. This filter is necessary to satisfy the
regulations of C.I.S.P.R. and V.D.E.
APPLICATION INFORMATION AVAILABLE ON REQUEST
236 February 1983\r
TEA1058TEA1058T
TOUCH-CONTROLLED LAMP DIMMER CIRCUIT
GENERAL DESCRIPTION
The TEA1058 is a bipolar integrated circuit for switching and regulating lamps and other loads with a
minimum of external components. It provides ON/OFF switching and a physiological power regulation
(equal brightness steps). It is suited for touch plates and for switches, and may combine local and
remote control. It produces negative pulses to drive a triac. The circuit is suited for resistive and for
inductive loads, i.e. it is not only suited for dimming lamps but also for regulating motors in fans,
vacuum cleaners, etc.
The TEA1058 and TEA1058T switch on at the level at which they were switched off.
The circuits feature:
- Alternative ON/OFF switching by a brief touch of one or both contacts.
- ON switching at previous brightness by a long touch of one or both contacts.
- Gradual change to maximum brightness during a long touch of the UP contact.
- Gradual change to minimum brightness during a long touch of the DOWN contact.
- No action during a long touch of both contacts in the ON state.
QUICK REFERENCE DATA
Supply voltage, d.c. (derived from mains voltage)
Supply current
Output current
Firing phase range
Time to change from minimum to maximumbrightness, or vice versa
Power dissipation in the ON state
Operating ambient temperature range
VCC typ. 15 V
Ice typ. 1 mAIq max. 100 mA
V typ. 30° to 140°
tv typ. 3,8 s
p typ. 19 mW
Tamb to + 85 °C
PACKAGE OUTLINE
TEA1058 : 8-lead Dl L; plastic (SOT-97C2).
TEA1058T: 8-lead mini-pack; plastic (SO-8;SOT-96AC1).
^\r,February1983 237
TEA1058TEA1058T
FUNCTIONAL DESCRIPTION
The TEA1058 generates negative output pulses to trigger a triac. These output pulses are phase shifted
with respect to the mains voltage. The amount of phase shift is determined by the difference betweenthe initial states of two 7-bit counters. Both counters are driven by the same clock pulse generator.One of the counters is preset to a number determined by the required phase angle. The higher therequired brightness, the smaller the required phase angle, the lower the number to which the counteris preset. The relation between brightness and preset number has been chosen so that almost equalbrightness steps are obtained (physiological control). The minimum phase shift corresponds with 32clock pulses and the maximum with 160.
Upwards and downwards regulation inputs UP and DN (pins 7 and 6)
At 50 Hz mains frequency the device ignores signals with a duration of less than 80 ms and signals witha duration of 80 to 320 ms are accepted as brief commands, these cause the circuit to switch on and offalternatively. Signals that last longer than 320 ms are interpreted as long commands. A long commandvia the UP input causes the output phase angle to decrease, i.e. the brightness to increase gradually; along command via the DN input has the opposite effect. A long signal on both inputs will switch on thelamp at previous brightness. If the lamp is already on, a long signal on both inputs will have no effect.
The UP and DN inputs may be activated by touch plates or by switches. For the input arrangementssee Fig. 2.
Slave input SLV (pin 2)
The SLV input operates in the same manner as the UP and DN inputs, but with a two-wire connection,ideal for remote control. The SLV input is only suited for switches. For the arrangement see Fig. 3.If the SLV input is not used it must be connected to the load via a 1 ,5 MSi resistor (see Fig. 4).
Oscillator RC pin OSC (pin 1
)
The frequency of the clock pulse generator is determined by an external resistor and capacitor, bothconnected to the OSC terminal (see Fig. 4). The generator switches at levels equal to 1/6 and 1/2 ofthe difference between the injector voltage V inj and the supply voltage Vrjc- The clock pulse periodis about 50 ps.
Output Q (pin 3)
Since the circuit has an open-collector output, it is capable of sinking current, i.e. drawing a currentinto the output. Therefore it is especially suitable for delivering negative trigger pulses.
The maximum output current is 100 mA. A gate resistor RG must be connected between the output Qand the triac gate to limit the output current to the minimum required by the triac (see Fig. 4). Thisminimizes the total supply current and the power dissipation.
A negative-going trigger pulse is generated at the output after every zero crossing of the mains voltage.The output pulse has a maximum duration of one clock pulse period, i.e. 50 ms. To reduce the powerdissipation the output pulse is terminated as soon as the triac has switched on.
Supply Vcc and Vee <P>ns 8 and 4)
The TEA1058 is supplied from the a.c. mains via a capacitor CD and a diode to VEE ; Vcc is connectedto the line (see Fig. 4). A smoothing capacitor CS has to be connected between Vcc and VEE . Thecircuit contains a string of stabilizer diodes between Vcc and VEE that limit the d.c. supply voltage.
During the positive half of the mains cycles the current through external voltage dropping capacitorCD charges the external smoothing capacitor Cs up to the stabilizing voltage of the internal stabilizer
(
diodes. Cp should be chosen such that it can supply the current lcc for the TEA1058 itself plus theaverage output current l3(AV)> and recharge the smoothing capacitor Cs-
238 February 1983^\r
<
a.
£<CO
I-zUl
S0.
O-iLU
>Ul
Q
Touch-controlled lamp dimmer circuit TEA1058TEA1058T
Any excess current is bypassed by the internal stabilizer diodes. Note that the maximum rated supply
current must not be exceeded.
During the negative half of the mains cycles external smoothing capacitor C$ supplies the circuit. Its
capacitance must be high enough to maintain the supply voltage above the minimum specified limit.
A supply voltage at Vr££ that is negative with respect to Vcc and the line is developed at the V^ pin.
Note that in the characteristics the voltages are mainly measured with respect to Vgg and not withrespect to V^q and the line.
The circuit has an internal power-on reset, which resets the brightness to minimum and forces the cir-
cuit into the OFF state.
Synchronization input SYN (pin 5)
The connection to the SYN input should be short and must be decoupled via a capacitor to VqC (P'n 8).
PINNING
osc [T_ U T]vcc
SLV [T
Q |T"
TEA1058T~|up
~6~| DIM
VEE [T ~j~| SYN
1 OSC oscillator (RC)
2 SLV slave input
3 Q output
4 VFF common5 SYN synchronization input
6 DN downward regulation input
7 UP upward regulation input
8 vCc positive supply
Fig. 1 Pinning diagram.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage range, d.c. Vqq
Supply current, d.c. IfjC
peak, max. 10/iis 'CCM
Input voltage range, all inputs V|
Input current, all inputs ± l|
Output voltage range Vg
Output current range lg
Power dissipation
Storage temperature range
Operating ambient temperature range
rtot
Tstg
Tamb
-0,5 to +18 V .
max. 20 mAmax. 0,5 A
-0,5 to +18 V
max. 20 mA-0,5 to +18 V
-20to + 150 mA
max. 250 mW-55 to + 125 °C
Oto +85 °C
~^\f,February 1983 239
TEA1058TEA1058T
CHARACTERISTICS
Vcc-StolSVjTamb'Oto + SBOC
parameter symbol min. tVP. max. unit
Supply Vcc (Pi" 8)
Internally stabilized supply voltage,
at lcc = 1,5 to 20 mA Vcc 13,3 15 16,8 V
Supply current at Vrx = 15 V, unloaded,
OFF state 'cc_ 1 1,2 mA
ON state 'cc- 1,25 1,5 mA
Power dissipation, unloaded,
OFF state p 15 mWON state p - 19 25 mW
Thermal resistance
TEA1058 Rth j-a_ 162 _ K/W
TEA1058T (note 1) Rth j-a— 140 — K/W
TEA1058T(note2) Rthj-a - 220 — K/W
Power-on reset threshold voltage vCCpor - - 4,8 V
Oscillator RC pin OSC (pin 1 )
Injector voltage Vinj 550 - 700 mV
Synchronization input SYN (pin 5)
Input current (r.m.s. value) '5(rms) 3 - - HA
Upwards and downwards regulation
inputs UP and DN (pins 7 and 6)
Input voltage V6-4; V7.4 1 - - V
Input current -is; -'7 - 3 '5(rms)- ,xA
Slave input SLV (pin 2)
Input current ±l2 10 - - MOutput Q (pin 3)
Output current '3 - - 100 mA
Notes
1
.
TEA1058T mounted on a ceramic substrate of 50 x 50 x 0,7 mm.
2. TEA1058T mounted on a printed-circuit board of 50 x 50 x 1,5 mm.
240 February 1983~\r
Touch-controlled lamp dimmer circuitTEA1058TEA1058T
R between 150J2 and 390kS2
<QLU-Ia.
S<v>
I-zUJ
SOLO-iLU
>a Fig. 2 Alternative arrangements for the UP and DN inputs.
Fig. 3 SLV input arrangement.
^r.February 1983 24T
TEA1058TEA1058T
APPLICATION INFORMATION
7Z89712.1A
(1) The connection to the SYN input should be short and must be decoupled near to pins 5 and 8.
(2) For example, Vakuumschmelze FD 2.5 1N1 KN.
Fig. 4 Touch-controlled lamp dimmer circuit for max. 450 W. L1 and C1 form a radio-frequencyinterference filter with a quality factor Q of less than 1 . This filter is necessary to satisfy theregulations of C.I.S.P.R. and V.D.E.
APPLICATION INFORMATION AVAILABLE ON REQUEST
242 February 1983^r
GENERAL INDUSTRIAL
CA3046
FIVE-TRANSISTOR ARRAY
GENERAL DESCRIPTION
The CA3046 is a bipolar integrated circuit consisting of five n-p-n transistors. Two transistors have
common emitters, the others are freely accessible. The transistors are capable of driving loads up to
100 mA. The transistor geometry is such that it reaches its maximum current gain at quite low cur-
rents, making the devices also suitable for small-signal applications.
The transistors are partly matched, i.e. TR1 and TR2 form a matched pair, TR3 and TR4 also.
QUICK REFERENCE DATA
Collector-base voltage (open emitter)
Collector-emitter voltage (open base)
Collector current (d.c.)
Power dissipation
each transistor
total
vCBO max. 18 V
vCEO max. 18 V
'C max. 100 mA
P max. 400 mWptot max. 500 mW
B1 01 C2 B2 B3 C3 B4 C4 B5 C5
2 1 5 4 6 8 9 11 12 14
y L-£rR3 L-£rR4 L-tjR5
TR1 | TR2
i 7 10 ^ 13
i
E1.E2 E 3 E 4 E 5
7Z86797
Fig. 1 Circuit diagram.
ci|T U u] C5
Bl|~2~ 75] EB
E1,E2pT Ta~| bb
B2[T CA3046 TT] C4
C2[T Tol E4
B3|~T "s~] B4
E3[~T "jTc3
7Z86796
Fig. 2 Pinning diagram.
PACKAGE OUTLINE
14-lead DIL; plastic (SOT-27T).
ArJanuary 1983 245
CA3046
RATINGS
Limiting values in accordance with the Absolute Maximum System
Each transistor
Collector-emitter voltage (open base)
Collector-base voltage (open emitter)
' Collector-substrate voltage (open base and emitter)
Emitter-base voltage (open collector)
Collectpr current (d.c.)
Base current (d.c.)
Power dissipation
each transistor
. total (see also Fig. 3)
Storage temperature range
Operating ambient temperature range
(IEC134)
vCEO max. 18 V
VCBO max. 18 V
Vcso max. 18 V
vEBO max. 5 V
c max. 100 mA
<B max. 20 mA
P max. 400 mWptot max. 500 mWTstg
-50 to + 125 °C
Tamb -40 to + 125 °C
Z86798
Fig. 3 Power derating curve.
OPERATING NOTE
As each collector forms a parasitic diode with the substrate, the substrate has to be connected to a
voltage which is lower than any collector voltage. To minimize parasitic coupling between the tran-
sistors, this voltage should be signal ground.
24* January 1983\r
Five-transistor array. CA3046
CHARACTERISTICS
Tamb = 25 °C unless otherwise specified
parameter symbol min. typ. max. unit
Collector-emitter breakdown voltage
at lc= 1 rnA.lg = v(BR)CEO 30 - - V
Collector-substrate breakdown voltage
at lc= 1 itiA;Ie = v(BR)CSO 30 75 - V
Collector-base breakdown voltage
at lc= 100mA;|£ = v(BR)CBO 30 75 - V
Emitter-base breakdown voltage*
at Ie = 100/iA;Ic = v(BR)EBO 6,2 7 7,8 V
D.C. current gain
I e =350mA;Vce =5V hFE 75 - 525
lE = 20mA;VCE = 5V "FE 47 - 365
Saturation voltage
at lc = 5mA;lg = 0,5mA vCEsat - 200 400 mVat Iq = 50 mA; Iq = 5 mA vCEsat - 400 840 mV
Input offset voltage at Vrjg = 5 V; \q = 1 mAany two transistors V|0 -
1 - mVmatched pair TR1 and TR2 V|0 - 0,5 - mV
Input offset current at Vqe = 5 V; Iq = 1 mAany two transistors ho -
1 - AtA
matched pair TR1 and TR2 '10 - 0,5 - MCollector cut-off current
at l B = 0;VCEo = 10 V 'CEO - - 0,6 "A,
atl E = 0;VCBO = 10V 'CBO - -1 liA
Breakdown of the emitter-base junction will cause degeneration of the current gain of the transistor.
*\fJanuary 1983 247
SAA10?7
STEPPING MOTOR DRIVE CIRCUIT
GENERAL DESCRIPTION
The SAA1027 is a bipolar integrated circuit intended for driving a four-phase two-stator motor. Thecircuit consists of a bidirectional four-state counter and a code converter to drive the four outputs in
the sequence required for driving a stepping motor.
Features
• high noise immunity inputs
• clockwise and counter-clockwise operation
• reset facility
• high output current
• outputs protected against damage by overshoot.
QUICK REFERENCE DATA
Supply voltage range
Supply current, unloaded
Input voltage, all inputs
HIGH
LOW
Input current, all inputs, LOW
Output current LOW
Operating ambient temperature range
vCc 9,5 to 18 V
'cc typ. 4,5 mA
V|H min. 7,5 V
V| L max 4,5 V
'IL typ. 30 nA
lOL max 500 mA
Tamb -20 to +70 °c
PACKAGE OUTLINE
16-lead DIL; plastic (SOT-38A).
>/October 1982 249
SAA1027
SAA1027
HNIL/CML
HNIL/CML
CTR21+/T-
0/3
2 0/1
2/3
OUTPUTDRIVERSTAGES
tcC
.1
.1
3.
12
V EE1 VEE2
Fig. 1 Block diagram. The blocks marked HNIL/CML are high noise immunity input stages, the block
marked CTR2 is a bidirectional synchronous 2-bit (4-state) counter and the block marked X/Y is a code
converter. C is the count input, M the mode input to select forward or reverse counting and R is the
reset input which resets the counter to content zero.
n.c. [jT U ""
~\F\ n.c.
rU is] C
M \T El VC(
rx [~r
vEEl[TSAA1027
H] VC(
«] VE(
oi \T IT] Q4
n.c. [T To] n.c.
" Q2 \jT T] Q3
Fig. 2 Pinning diagram.
PINNING
1 n.c. not connected
2 R reset input
3 M mode input
4 RX external resistor
5 VE E1 ground
6 Q1 output 1
7 n.c. not connected
8 Q2 output 2
9 Q3 output 3
10 n.c. not connected
11 Q4 output 4
12 VEE2 ground
13 VCC2 positive supply
14 VCC1 positive supply
15 C count input
16 n.c. not connected
25ft October 1882
"\/"
Stopping motor drive circuit SAA1027
FUNCTIONAL DESCRIPTION
Count input C (pin 15)
The outputs change state after each L to H signal transition at the count input.
Mode input M (pin 3)
With the mode input the sequence of output signals, and hence the direction of rotation of the stepping
motor, can be chosen, as shown in the following table.
counting
sequence
M = L M = H
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
L H L H L H L H
1 H L L H L H H L
2 H L H L H L H L
3 L H H L H L L H
L H L H L H L H
Reset input R (pin 2)
A LOW level at the R input resets the counter to content zero. The outputs take on the levels shown in
the upper and lower line of the table above.
If this facility is not used the R input should be connected to the supply.
External resistor pin RX (pin 4)
The external resistor R4 connected to RX sets the base current of the output transistors. Its value has
to be chosen in accordance with the required output current (see Fig. 5).x
•
Outputs Q1 to Q4 (pins 6, 8, 9 and 1 1
)
The circuit has open-collector outputs. To prevent damage by an overshooting output voltage the
outputs are protected by diodes connected to VrjC2' P'n 13 - Hi9n output currents mainly determinethe total power dissipation, see Fig. 3.
^/"@«6ber 1982 251
SAA1027
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage, d.c.
Input voltage, all inputs
Current into pin 4
Output current
Power dissipation
Storage temperature range
Operating ambient temperature range
VCCV VCC2 max. 18 V
V| max. 18 V
!rX max. 120 mA
lOL max. 500 mAptot see Fig. 4
Tstg -40 to +125 °C
"amb -20 to + 70 °C
CHARACTERISTICS
Vcc = 9,5to18V;VE E = 0V;Tamb = -20 to 70 °C unless otherwise specified.
parameter symbol min. typ. max. unit
Supply Vcci antl V(X2 'P 'nS 14 and 1 ^'
Supply current at VcC\ = 12 V;
unloaded; all inputs HIGH; pin 4 open 'cc 2 4,5 6,5 mA
Inputs C, M and R (pins 15, 3 and 2)
Input voltage
HIGH V|H 7,5 _ V
LOW V|L - 4,5 V
Input current
HIGH l|H 1 _ MA
LOW -l|L 30 - ma
External resistor pin RX (pin 4)
Voltage at RX at Vcc = 12 V ± 15%;
R4=130n±5% Vrx 3 4,5 V
Outputs Q1 to Q4
Output voltage LOWat Iql = 350 mA vol 500 1000 mVat Iql = 500 mA vol 700 - mV
Output current
LOW 'OL __ 500* mAHIGH at Vq= 18 V -!OH - - 50 MA
* See Figs 3 and 4.
252 October 1982~\r
Stepping motor drive circuit
J VSAA1027
100 200 300 400 500l0L (mAI
Fig. 3 Total power dissipation V\a\ as a
function of output current Iql-
7Z64952.1
2000
\ptot
'
\N
^S k
\
\25 50 75 100 125
Tamb<°C>
Fig. 4 Power derating curve.
Vr *~/
>R)<
'RX
(mAI
Fig. 5 Current Irx into RX and voltage Vrx °"RX as a function of required output current Iql-
0,1 (/F
Q1
Q2
Q3
Q4
V EE1 V EE2
STEPPINGMOJOR
—U nnrYx_L
12
Zfc 7Z87071
Fig. 6 Typical application of the SAA1027 as a stepping motor driver.
October 1982 253
SAA1029
UNIVERSAL INDUSTRIAL LOGIC AND INTERFACE CIRCUIT
GENERAL DESCRIPTION \
The SAA1029 is a universal bipolar logic and interface IC with high noise immunity and operational
stability for industrial control applications. The most fundamental industrial control functions can be
accomplished with only one SAA1029 IC. Figure 1 shows the logic configuration.
The I C comprises,
(1) Gate 1 : 4-input AND gate with 1 inverted input,
(2) Gate 2: 3-input AND gate with 1 inverted input and adjustable propagation delay,
(3) Gate 3: 2-input AND gate with 1 inverted input.
The SAA1029 can be used as direct interface with LOCMOS (CMOS) ICs for realizing more complexfunctions. Therefore, the output signal can be limited to the voltage level of the common output
clamping pin Z.
The propagation delay of NAND gate 2 is adjustable from microseconds to seconds by using an external
capacitor at pin C. This makes it possible to adapt the control frequency limits to the system, so the
optimum dynamic noise immunity can be achieved.
All the static and dynamic circuit values (including the output voltage) are independent of the supply
voltage over a wide operating range. This allows the use of a simple unstabilized power supply.
The output is held to the LOW state automatically during switching on the power supply, so a special
reset pulse can be omitted.
Features
• Simple realization of the basic industrial control functions (logic functions, timing functions,
memory functions).
• High dynamic and static noise immunity.
• High operation stability.
• Short-circuit protection of inputs and outputs to both Vr££ and Vcc-• Wide supply voltage range, so a simple power supply can be used.
• Wire interruption results in a safe input LOW state.
• LOCMOS (CMOS) compatible.
QUICK REFERENCE DATA
Supply voltage range
Operating ambient temperature range
vCc
lamb
14 to 31,2 V
-30 to +85 °C
Input voltage HIGH
Output voltage HIGH (without clamping)
Output voltage HIGH (with clamping at pin Z)
Input current
Quiescent supply current
V|H 6,5 to 44 V
VOH 13 to 30 V
V H 2,0 to (Vcc -0,7) V
"Imax. 10 mA
'cc typ. 7,8 mA
PACKAGE OUTLINE
16-lead DIL; plastic (SOT-38).
~\rJanuary 1982 255
SAA1029
Ml '12 '13 "14 '21 '22 '23 <31 '32
VCC VEE 0!
Logic equations:
°1 =]r\ '12 ' >13 " '14
2 = l2y • l22 • <23
°3 ='31 * "32
Fig. 1 Logic diagram.
'14
'13
1 12
"11
'32
"31
C
vEE
1u 16
2 15
3 14
4
SAA102913
5 12
6 11
7 10
8 9
PINNING
u1
Z
o 3
2
'21
'22
'23
4 in|
3
2'12
'13inputs of gate 1
1
15
'14 )
01 output of gate 1
11
10
9
12
"21
'22
'23 J
2
inputs of gate 2
output of gate 2
6
5'31
'32inputs of gate 3
13 °3 output of gate 3
7 C external delay capacitor
14 z common output clamping
16 vCc positive supply voltage
8 VEE ground
Fig. 2 Pinning diagram.
2j5ft January 1982 ...,r y
.
Universal industrial logic and interface circuit SAA1029
RATINGS
Limiting values in accordance with the Absolute
. Supply voltage range
Input voltage (independent of Vrjc)
Output clamping voltage (pin 14)
Voltage at any output (pins 12, 13 and 15)
pin 14 (Z) open
pin 14(Z)at Vz
Current into any input
d.c.
tp= 0,5jus;6 = 0,1% (peak value)
Sum of input currents
d.c.
tp=0,5 jus; 8 = 0,1% (peak value)
External applied current at any output (pins 1 2,
pin 14 (Z) open
d.c.
tp = 0,5 /us; 8 = 0,1% (peak value)
External applied current at any output (pins 1 2,
pin14(Z)atVzd.c.
tp= 0,5 /us; 8 =0,1% (peak value)
Voltage at pin 7 (C)
External capacitor at pin 7 (C)
Short-circuit of outputs (pins 12, 13 and 15)
pin 14 (Z) open
at VZ < VCCTotal power dissipation (see also Fig. 3)
at Tamb = 50 °C; continuous
at Tamb = 65 °C; max. 1000 hours
Storage temperature range
Maximum System (I EC 134)
vCcV|
vz
Oto+35 V-0,1 5 to + 44 V
Oto+35 V
v
v
-0,1 5 to VCC Vmax. Vz VorVcc if Vcc <VZ
±l|
±I|M
max. 10 mAmax. 100 mA
13 and 15)
SI,
SI IM
-90 to + 10 mA-900 to + 300 mA
13 and 15)
±io max. 30 mAmax. 500 mA
io
io
vcany value
-30 to + 10 mA-500 to + 100 mA-0,15 to + 6 V
allowed to Vcc and V EE l° V)allowed only to Vee (0 V)
rtotptotTstg
max. 1100 mWmax. 1100 mW
-40to + 150 6C
max. 1000 hours
continuous
H±
125 140
Tamb (°C)
Fig. 3 Power derating curves; Rtn j.a= 70 K/W.
~\rJanuary 1982 ..257-, B0-
inrar
CHARACTERISTICS
At Tamb = -30 to +85 °C; Tj < 125 °C; Vcc = 14 to 31,2 V; unless otherwise specified
symbol min. typ. max. unit conditions
Supply voltage(
vCc 14 24 31,2 V
Quiescent supply current >cc- 7,8 - mA
!CC- - 12,2 mA VCC=31V;Tamb = 25 0C
Quiescent current ratio'CC1
'CC2
- 0,67 - 'CC1 =icc atTj
= 125 °c
'CC2 = lccatTj = 25°C
Input voltage LOW V| L- - 5 V
Input voltage HIGH V|H 6,5 - - V
V|H 6,55 - - V
Input current LOW -"lL- - 100 IxA
-'IL- - 95 /*A
Input current HIGH IH 300 - - MA
Rate of change of input signal dV/dt 3 - - V/ms
Input current* -'I- - 120 MA V| = 1 V
'I- - 280 ma V|=35V
Output clamping voltage* vz - - 30 V vz = VCC -1 V
Output voltage without clamping
(pin 14 open)*
non-inverting input: V| = 5,1 Vinverting input: V| = 6,3 VLOW vol
vol
_ _ 1
1,5
VV
VCC = 14V
IO = 1,32 mAlO = 2,91 mA
HIGH V H vCc- 1 -4 - - V — Iq = 5 mAOutput voltage with clamping
(pin 14 at Vz )*
LOW volvol
- - 1
1,5
VV
VCC = 31,2 VV2 < Vcc-1 vIO = 1,32 mAIq= 1,91 mA
>>6ioCD
HIGH V HVOHV H
(VZ -0,475)
(VZ -0,455)
(Vz -0,41)
-(Vz +0,225)
(Vz+0,12)(VZ + 0,055)
VVV
Iq = mA-Iq = 1 mA-lQ = 3mA
Output short-circuit current*
LOW-signal 'OscL 2,95 _ 9,6 mA output at VqcHIGH-signal -'OscH 10,1 - 21,9 mA output at VEE (0 V)
Capacitor charging current* >C- 30 - MA
Propagation delays*
gates 1 , 2 and 3
HIGH to LOW
LOW to HIGH
tPHL
tPLH
- 3,5
3,5
- /us
lis
C = (at gate 2)
gate 2
HIGH to LOW tPHL 1,85 5,2 ms|C = 47nF± 1%
LOW to HIGH tPLH 7,5 - 14 ms I Rinsulation>100Mn
At Tam t,= 25 °C; Vqq = 24 V; unless otherwise specified.
>>IV)
to
HUM
m\
CHARACTERISTICS (worst case conditions)
AtTj = + 125 to + 140 °C; maximum 1000 hours
symbol min. typ. max. unit conditions
Input voltage LOW V| L - - 5 V
Input voltage HIGH V|H 6,55 - V
Input current l| 95 300 nA V| = 1 to 44 V
Change of input current
overdrive of other
inputs S(-l|)< 10 mA All
Al|
— — 120
158
MAfiA
V|<VCC -1VV|>VCC -1 V
overdrive of other
inputs S(-l|) <90mA Al,
Al, _ —280320
MA,xA
V|<VCC -1 VV|>VCC -1 v
Input voltage by
current overdrive V| 46 65 V 2(-l|) = 10mA
Output voltage without
clamping (pin 14 open)
LOW volvolvol
- 0,35
1
1,5
VVV
Iql< 0,095 mAIOL = 0-095to 1 mAIql =
1 to 2,5 mA
HIGH V H Vcc-1,5 - V —'oh ^ ^ mA
Output voltage with
clamping (pin 14 at Vz>HIGH V H
V HV HV H
(VZ -0,5)
(VZ -0,5)
(VZ -0,5)
(VZ + 0,245)
(Vz+0,15)vz0,75
VVVV
Vz = 2,5 to Vcc -1 VlOH = 0mAl0H = 1 mAl0H =3mAlOH = 0mA;Vz = V
Output short-circuit current
LOW-signal 'OscL— — 11 mA output at Vcc
HIGH-signal -'OscH 5 28,5 mA output at Vee(OV)
HIGH-signal -'OscH - 10 mA ) output at Vee(OV)| Tj = 140°C
CO>>6l\3
Current out of pin 14 (Z) -'z - - 2,2 mA -IO<3mAwhen currents are
forced into outputs -iz si - mA Sl " <'01 +,02 + l03>Current into pin 14 (Z)
when inputs are set
for output to be LOW >Z 300 MA -lO = 30 mA; Vq < VEE1 input and/or output voltages
Supply current change AI CCmax (0,3 x|l||) + (0,55 x|l |) mA ! are negative with respect
1 to VEEPropagation delays
gates 1 and 3
HIGH to LOW tPHL 1 7 MSLOW to HIGH tPLH 1 7 MS
gate 2
HIGH to LOW tpm_ 0,1 4 MS 1 uLOW to HIGH tPLH 0,3 6 MS
without capacitor
HIGH to LOW tpj-iL 38 xC 113xC MS 1 u „• r-
LOW to HIGH *PLH 142 x C 334 xC MSwith capacitor; C in /iF
Voltage spikes output
LOW vol — — 2 V see note
Note
c-3
i'
i
Vqc rising from to 14 V; all inputs open; internally it is guaranteed that the input threshold voltage V| |_ > Vql-
J
>>oCD
imtiL
SAA1029
APPLICATION INFORMATION
The following figures (Figs 4 to 1 1 ) give some examples of the basic industrial control functions.
o—M-
o-M- t> o M-
Fig. 4 OR function.
t3>bEH>
jjte
Fig. 8 Monostable flip-flop; for C = 4,7 j/F,
1 s no reaction.
rr€E>
tz> H-Site
Fig. 5 EXCLUSIVE-OR function. Fig. 9 Start delay function.
hi
sethiW\ "<
T=T7Vreset J^LT —
C
lrz>
IFig. 6 Delayed memory; reset is dominating.
7Z85517
Fig. 10 Decay delay function.
start /stop
L£t>
I Fig. 7 Delayed memory; set is dominating. Fig. 11 Square-wave oscillator.
2S2, January J982 ;
DEVELOPMENT SAMPLE DATAThis information is derived from development samples
made available for evaluation. It does not necessarily
imply that the device will go into regular production.
SAK150BT
SERVO-MOTOR CONTROL CIRCUIT
GENERAL DESCRIPTION
The SAK150BT is a bipolar integrated circuit intended for remote control applications in digital pro-
portional systems or other closed-loop position control applications, in which it will translate the widthof its input pulses into a mechanical position. It incorporates a linear one-shot for improved positional
accuracy. The circuit has additional outputs for driving external p-n-p transistors to form a bidirectional
bridge.
Features
• high output current
• bidirectional bridge output facility with single power supply
• adjustable deadband
• adjustable proportional range
• high linearity
• wide supply voltage range
• low standby supply current
• provides stabilized supply for external circuit
QUICK REFERENCE DATA
Supply voltage range
Supply current, standby, at Vqq = 4,8 V
Stabilized supply voltage for external circuit
Output current at Vqq = 4,8 V
Operating ambient temperature range
vCc 3 to 9 V
ice typ. 4 mAvz typ. 2 V
'Q max. 500 mA
Tamb -20 to + 60 °C
PACKAGE OUTLINE
14-lead mini-pack; plastic (SO-14; SOT-108A).
~\fFebruary 1983 26&
Illllffl
CO>
om
VEE2 VEE1
Fig. 1 Block diagram. The blocks marked "&"are AND gates, the block marked ">V is an OR gate, the blocks with inputs marked Sand Rareset-reset flip-flops and the block marked "COMP" is a comparator. The inputs of this comparator have unequal weights; this particular comparatormay be considered as a high-gain amplifier for the upper input with the lower input giving a small shift of the switching Jevel. The triangles at someof the inputs and outputs are polarity indicators showing that the internal logic 1 -state at that input or output corresponds with the external logic
L-levS (LOW). At inputs and outputs without polarity indicator the internal logic! -state corresponds with the external logic H-level (HIGH).
Servo-motor control circuit SAK150BT
SS
111
>Ula
PINNING
Fig. 2 Pinning diagram.
2
3 DIS
4 RA5 QB26 Q27
8
9
VEE2vCcQB1
10 Q111 MF12
13VEE1I
14 RX
external monostable capacitor
stabilized voltage output
discharging resistor
reset amplifier
p-n-p driver output
power output
ground of output stage
positive supply
p-n-p driver output
power output
monostable feedback
ground of circuit (except outputinput
external resistor
FUNCTIONAL DESCRIPTION (See also Fig. 5)
The SAK150BT has two sets of outputs on which it is capable of producing output pulses of variablewidth. The output arrangement is such that these output pulses can drive a servo-motor in both direc-tions. The servo-motor actuates a potentiometer. The width of the output pulses is reduced to zero whenthe position of the potentiometer slider corresponds with the width of the input pulses.
The circuit operates as follows. The positive-going leading edges of the input pulses trigger a monostableelement. Its output pulses have a duration that is a linear function of the position of the potentiometerslider. These pulses therefore will be referred to as feedback pulses.
The presence of both the input pulse and the feedback pulse switches on a current source of approx.0,3 mA which charges an external capacitor C2 connected from RA (pin 4) to ground. The variation ofthe voltage on this capacitor after some time causes the output of the high-gain reset amplifier to changestate and reset the two output flip-flops.
Depending on the relative durations of input pulse and feedback pulse the following happens.1
.
Difference in duration of input pulse and feedback pulse less than the deadband time: no outputsignals generated.
'"
2. Input pulse shorter than feedback pulse: outputs Q1 and QB1 activated.'
3. Input pulse longer than feedback pulse: outputs Q2 and QB2 activated.
The trailing (negative-going) edge of the shorter of the two pulses (input pulse or feedback pulse) switchesoff the current source that charged C2. It further switches on the discharging of C2 via R2, connected to *
DIS (pin 3). As a consequence the output of the reset amplifier changes state after a short delay and nolonger resets the flip-flops. Finally the code converter generates a signal which sets the appropriate outputflip-flop but inhibits the output. ,.
At the trailing edge of the longer of the two pulses the signal that has set one of the flip-flops changesstate. This enables the corresponding output. It further finishes the discharging of C2 via R2. C2 willnow be charged via R3. When the voltage on C2 reaches the switching level of the reset amplifier its
output signal will reset the flip-flops again and this will terminate the output pulse (see Fig. 3). Theduration of the output pulse is proportional with the charge required by C2 to reach the switching levelof the reset amplifier, and this charge is proportional to the time that C2 has been discharged via R2,i.e. the difference in duration of the input pulse and the feedback pulse.
The maximum output pulse duration is reached when the output pulse is terminated by the next inputpulse.
^\rFebruary T983 28#
SAK150BT
FUNCTIONAL DESCRIPTION (continued)
, Supply: Vcc VEE i,VEE2 and Vz (pins 8, 12, 7 and 2)
The SAK150BT contains a voltage stabilizer. This permits the circuit to be used over a very wide supply
voltage range without substantial variation of its performance. The stabilized supply voltage is available
at Vz (pin 2) to supply an external peripheral circuit, e.g. a feedback potentiometer.
The circuit has two ground pins, one for the output stage (V E E2) anc' one f°r tne rest °f tne
circuit (VEE i).They should be interconnected externally.
Input I (pin 13)
Input pulses should be positive-going, i.e. the time that the input signal is HIGH is the input parameter.
Usual values are 1 to 2 ms for the pulse to be HIGH and 20 ms for the pulse repetition time.
Feedback pulse duration: CMX, MF and RX (pins 1, 11 and 4)
The duration of the feedback pulse is determined by external capacitor C1 connected between CMX\ and MF. This capacitor is charged by a current source whose current is determined by external resistor
R1 connected between RX and ground.
Deadband time
The deadband time is the maximum difference in duration between the input pulse and the feedback
pulse that will not give an output signal (see Fig. 4). The deadband time is determined by external
resistor and capacitor R2 and C2 connected to RA and by the threshold voltage Vtr, rof the Schmitt
trigger and by its deadband V^t,, according to the following approximative formula:
^ R2 x C2 x Vdb _ Q Q215 R2 x C2 (typjca|rVthr - vdb
Proportional range
The output pulse width is proportional to the input pulse width up to the point that the output pulse
width equals the time between the input pulses t| |_ (see Fig. 4). The input pulse width at which the
maximum output pulse width is reached may be chosen by the ratio of R2 and R3. It is given by the
following approximative formula:
R2 /VCC \
V°P~lW*lvW- 1
)
xt 'L*-thr
Outputs Q1, QB1, 02 and QB2 (pins 10, 9, 6 and 5)
The outputs Q1 and Q2 are open-collector outputs capable of sinking up to 500 mA. The outputs QBl
and QB2 are intended to drive external p-n-p transistors. Together with the Q outputs these p-n-p
transistors may form a bidirectional bridge output with a single power supply, see Fig. 4.
' If ex'* 1 + x for charge and discharge at RA (pin 4).
2Q6 Fe|jruary.19$3^\r
--
Servo-motor control circuit SAK150BT
A i \
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage, d.c. * Vqc max.
Current at V2 _,vz max
12 V
3, mA
Input voltage
Voltage at CMX
Current at CMXCurrent at RX
Voltage at MF
V| max.
—V| max.
~VCMX max.
ICMX max.
-IrX max.
VMF max.
12 V5 V
5 V
5 mA1 mA
12 V
Current at MF IMF max.
-IMF max.p mA -
3 mA
Current at RA
Output voltage, Q1 and Q2
Ira max.
-Ira max.
Vq max.
6 mA5 1 mA
24 V<1-
<QUJ
Output current, Q1 and Q2, repetitive peak
Output voltage, QB1 and QB2
'QRM max.— Iq max.
Vqb max.
800 mA10 mA
12 V0.
CO1-zUJ
Output current, QB1 and QB2
Storage temperature range
Operating ambient temperature range
•qb-Iqb
Tstg
Tamb
max. 70 mAmax. 10 mA-35 to +125 *>C
-20 to + 70 °CE&UJ>
\/"FfelhJary iSoS 2(*7
SAK150BT
CHARACTERISTICS
Vcc = 3 to 9 V; Veei = VEE2 = V; Tamb = _2° 10 + 70 °c unless otherwise specified
parameter symbol min. typ. max. unit
Supply: Vcc a"d VZ <Pins 8 and 2)
Supply current at Vcc = 4,8 V;
Tamb = 25 °C; output stages OFF 'cc- 4 - mA
Stabilized voltage output Vz - 1,95 - V
Variation with temperature AVZ/AT - 6 - mV/K
Output current at Vcc = 4 -8 v for AVZ = 40 mV -iz — — 1 mA
Input 1 (pin 13)
Input voltage
HIGH V|H 2,4 — — V
LOW V| L- - 0,6 V
Input current
HIGH at V| =2,4V l|H— — 250 MA
LOW at V| = 0,6 V -hL - - 30 MExternal resistor pin RX (pin 14)
Voltage at -I rx = 100 /xA VRX - 0,7 - V
Current range |rx 10 - 200 tiA
Monostable feedback pin MF (pin 1 1
)
Voltage at l^p = 2 mA vMf- - 300 mV
Output current !|VIF- - 3 mA
Reset amplifier pin RA (pin 4)
Switching level of reset amplifier,
internal current source OFF Vsw _ 1,9 _ V
Deadband (shift of switching level by
internal current source) Vdb — 40 - mV
Input current
HIGH >RA_ _ 6 mA
LOW -!RA - 300 - HA
External monostable capacitor pin CMX (pin 1
)
Current^MX-!CMX
'.
!RX
1 mA
268 February 1983\r
Servo-motor control circuit SAK150BT
<QUJ_ia.
S<
parameter symbol min. typ. max. unit
Outputs Q1 and Q2 (pins 10 and 6)
Output voltage at Vqc = 4,8 V;
IqB = 50 mA; Iq = 500 mA vQ 450 550 mVOutput current at Vrjc = 4,8 V;
Iqb = 20 mA iq - - 500 mA
Outputs QB1 and QB2 (pins 9 and 5)
Output voltage at V^c = 4,8 V;
IqB = 50 mA Vqb 1,2 1,6 V
Output current at Vqq = 4,8 V 'qb- 50 mA
Discharging pin DIS (pin 3)
Output voltage LOW at Ipis = 2 mA VDISL - 300 mVOutput current
HIGHat VD | S = 9 V -'dish - 500 nA
LOW •disl- 5 mA
UJ
>
FEEDBACK PULSE
PULSE LENGTHDIFFERENCE
OUTPUT CURRENT
ATQ1
OUTPUT CURRENT
ATQ2
|-«-l IH -»-|-« <IL
J,_ ».
l
- <Q1 — »
Vt„«
V
Fig. 3 Timing diagram.
^\rPSbruary, 1983 269
SAK150BT
Fig. 4 Output current pulse duration tQ as a function of the difference between input pulse duration
t|H and feedback pulse duration tpH- There is no output signal for differences less than the deadband
time tjjt). The maximum output pulse duration at outputs Q1 and QB1 is equal to the time between
the feedback pulses tp |_, the maximum duration at Q2 and QB2 is equal to the time between the input
pulses t| |_. The maximum pulse duration is reached at a pulse duration difference tpr0p.
APPLICATION INFORMATION
DIS RA
SAK150BT
Q1
QB2
Q2
TjOOnF
i2on &i
270
Fig. 5 Typical application of the SAK150BT for remote control of a model. The arrangement may be the
last part at the receiving side, e.g. after a multi-channel time division multiplex system, to drive the
steering motor. The potentiometer Rp is actuated by the motor.
February 1983
J V
TDA1060TDA1060ATDA1060B
CONTROL CIRCUIT FOR SWITCHED-MODE POWER SUPPLY
GENERAL DESCRIPTION
The TDA1060 is a bipolar integrated circuit intended for the control of a switched-mode power supply.
It incorporates all the control functions likely to be required in switched-mode power supplies for
professional equipment.
The circuit features:
• Suitability for a wide range of supply voltages
• Built-in stabilized power supply for external circuitry
• Built-in temperature-compensated voltage reference
• Adjustable frequency
• Adjustable control loop sensitivity
• Adjustable pulse width
• Adjustable maximum duty factor
• Adjustable overcurrent protection limit
• Low supply voltage protection with hysteresis '
• Loop fault protection
• Slow-start facility
• Feed-forward facility
• Core saturation protection facility
• Overvoltage protection facility
• Remote ON/OFF switching facility
QUICK REFERENCE DATA
Supply voltage (voltage source)
Supply current (current source)
Output current
Stabilized voltage
Reference voltage
Output pulse repetition frequency range
Operating ambient temperature range
TDA1060
TDA1060A
TDA1060B
vCc max. 18 V
'cc max. 30 mA
-'14; h5 max. 40 mAvz typ. 8,4 V
Vref typ. 3,72 V
fo 50 Hz to 100 kHz
Tamb -25 to + 125 °C
'amb 0to + 70 °C
Tamb -55 to +150 °C
PACKAGE OUTLINES
TDA1060, TDA1060A: 16-lead DIL; plastic (SOT-38).
TDA1060B: 16-lead DIL; ceramic (SOT-74).
\rAtitfrst'1982s 271
TDA1060TDA1060ATDA1060B
yv.FW RX CX SYN
16 7 8 9
REFERENCEVOLTAGE
SAT
13
SAWTOOTHGENERATOR
TDA1060
£>STABILIZEDSUPPLY
10
EN
1
VCC
&12
VEE
Fig. 1 Block diagram.
PINNING
ycc \T
!
u Te] FW
v2 [T Ti] Qc
FB (T TT| QE
GA [T
MOD [T
TDA1060TDA1060ATOA1060B
7i] SAT
JH VEE
DFM [T" T7| cm
RX(
|T To] EN
cx [F ~9~| SYN
Fig. 2 Pinning diagram.
272 August 1982A^
1 vCc2 vz3 FB
4 GA5 MOD6 DFM
7 RX
8 CX
9 SYN
10 EN
11 CM
12 VEE
13 SAT
14 QE
15 Qc16 FW
positive supply connection
stabilized voltage output
feedback input
gain adjustment output
modulation input
maximum duty factor input
external resistor connection
external capacitor connection
synchronization input
ENABLE input
overcurrent protection input
common
core saturation and overvoltage protection
input
emitter output
collector output
feed-forward input
Control circuit for SMPS
TDA1060TDA1060ATDA1060B
FUNCTIONAL DESCRIPTIONs
The TDA1060 contains the control loop for a fixed-frequency pulse-duration regulated SMPS. Thedevice works as follows. The output voltage Vq of the SMPS is sensed via a feedback network andcompared with an internal reference voltage Vref . Any difference between Vq and Vref is amplifiedand fed to a pulse-width modulator (PWM), where it is compared with the instantaneous level of a
ramp waveform (sawtooth) from an oscillator. The output from the PWM is a rectangular waveformsynchronized with the oscillator waveform; its duty factor depends on the difference between Vq and
Vref- This signal drives the base of the SMPS power switching transistor so that its conduction periodand hence the amount of energy transferred from the input to the output of the SMPS is controlled,
resulting in a constant output voltage.
Stabilized power supply: Vrx and Vz (pins 1 and 2)
The circuit contains a voltage/current regulator and may be supplied either by a current source (e.g. aseries resistor connected to the high voltage input of the SMPS), or a voltage source (e.g. a 12 Vbattery).
The stabilized voltage, typically 8,4 V, is also available at V^, pin 2 for supplying external circuitry,
e.g. a potentiometer to adjust the maximum duty factor. This supply output is protected against short-
circuits. The current drawn from this output increases the total IC supply current by the same amount.
When the supply voltage Vrjc becomes too low, i.e. Vrjc < V^ + 0,2 V, the circuit is automaticallyswitched off. As soon as the supply voltage exceeds this threshold value by more than 0,2 V the circuit
starts the SMPS via the slow start procedure.
Operating frequency: RX and CX (pins 7 and 8),
The frequency of the sawtooth generator, and hence of the output pulses, is set by an external resistor
R7 at RX, pin 7, and an external capacitor C8 at CX, pin 8. The frequency will be 1,2/R7C8. It maybe set between 50 Hz and 100 kHz and is virtually independent of the supply voltage.
Maximum duty factor and slow start: DFM (pin 6)
The maximum duty factor is set by the voltage on the duty factor input DFM (see Fig. 4). This voltageusually is derived from the stabilized power supply V^, pin 2, by an external voltage divider, see Fig. 6.
As the upper and lower levels of the sawtooth waveform are set by an internal voltage divider, theaccuracy of the maximum duty factor setting is determined by resistor ratios rather than by absolutevalues.
In case of a short-circuited feedback loop (V3.12 less than typ. 600 mV) the duty factor input is
internally biased to the lower level of the sawtooth waveform via a resistor of typ. 1 kft. The maximumduty factor permitted in that case sets a maximum limit to the impedance level of the external voltagedivider at pin 6.
During the flyback of the sawtooth the output pulse is inhibited. For a 1 nF capacitor C8 at pin 8 this!
flyback time is 1 /js. This sets a natural limit to the duty factor.
The time constant for the slow start is determined by an external capacitor connected between themaximum duty factor input DFM and V^e, pin 12, together with the impedance of the voltagedivider at pin 6. This capacitor also determines the dead time before the slow start procedure forremote ON/OFF or when the current sensing voltage has exceeded 600 mV, see below.
If the DFM input is not used it should be connected to V^ via a resistor of 5 kS2.
^rAugust 1982 (
873
TDA1060TDA1060ATDA1060B
FUNCTIONAL DESCRIPTION (continued)
Control loop sensitivity, stability, and feedback loop fault protection, FB and GA (pins 3 and 4)
The device contains a control loop error amplifier, i.e. a differential amplifier that compares the
voltage on the feedback input FB, pin 3, with the internal reference voltage. This reference voltage is a
temperature-compensated voltage source based on the band-gap energy of silicon.
The control loop sensitivity is determined by the closed-loop gain Af of the error amplifier. Normally
the output from the SMPS is connected to the feedback input FB via a voltage divider and a series
resistor. The closed-loop gain of the error amplifier is set by applying feedback from the gain adjustment
output GA, pin 4, to the feedback input FB by a resistor R3-4, see Fig. 6.
To avoid instability a capacitor should be connected between the gain output GA and Vgg,
pin 12. A 22 nF capacitor will cause the frequency response to fall off above 600 Hz.
The feedback input FB is internally biased to the HIGH level, this gives a protection against a feedback
loop fault: an open feedback loop will make the duty factor zero.
A shorted feedback loop (feedback voltage less than typ. 600 mV) causes the maximum duty factor
input DFM to be internally biased to the lower level of the sawtooth waveform via a resistor of typ.
1 kI2, thus substantially reducing the maximum duty factor. This duty factor will then be determined
by the impedance of the external voltage divider at DFM, pin 6, and the internal biasing resistor.
Overcurrent protection input CM (pin 1 1
)
There are two current limits, corresponding with voltages on the overcurrent protection input CM of
typ. 480 mV and 600 mV. As soon as the voltage on this input exceeds 480 mV, the running output
pulse is immediately terminated; the next pulse starts normally at the next period. If the voltage
exceeds 600 mV, the output pulses are inhibited for a certain dead time, during which the slow start
capacitor at pin 6 is unloaded. After this the circuit starts again with the slow start procedure.
If the overcurrent protection input CM is not used, it should be connected to V^g, pin 12.
Feed-forward input FW (pin 16)
The feed-forward input FW can be connected to an external voltage divider from the input voltage of
the SMPS, see Fig. 6. It has the effect of varying the supply voltage of the sawtooth generator with
respect to the stabilized voltage. When the voltage on the feed-forward input increases, the upper level
of the sawtooth is also increased. Since neither the voltage level that sets the maximum duty factor nor
the feedback voltage are influenced by the feed-forward, the duty factor reduces (see Fig. 5). This can
therefore compensate for mains voltage variations.
If feed-forward is not required the feed-forward input FW should be connected to V^e, pin 12.
Synchronization input SYN (pin 9)
The frequency of the sawtooth waveform, and hence of the output pulses, can be synchronized via the
TTL compatible synchronization input SYN. The synchronizing frequency must be lower than the
oscillator free-running frequency. When the synchronization input is LOW the sawtooth generator is
stopped; it starts again when the input goes HIGH. Synchronization pulses do not influence the slope
of the sawtooth, and hence not the width of the output pulses, they only change their separation in
time.
For free-running operation it is advisable to connect the synchronization input SYN to V^, pin 2.
274 August 1982~\r
Control circuit for SMPS
TDA106&TDA1060ATDA1060B
Core saturation and overvoltage protection input SAT (pin 13)'
To obtain a protection against core saturation, especially during transient conditions, the output
transformer of the SMPS has to be fitted with a winding serving as a current sensor. Its output vqttage,-
is rectified and fed to the SAT input.
This core saturation protection may be combined with an overvoltage protection. To this end a portion
of the SMPS output voltage is also fed to the SAT input either via a voltage divider or via a suitable
regulator diode (zener diode). The output pulses are inhibited as long as the voltage on this input
exceeds the threshold voltage, typ. 600 mV.
The voltage at the SAT input does not influence the frequency of the sawtooth generator and hence
nat of the output pulses.
If none of these protection facilities are used, the SAT input should be connected to V^g. Pin 12.
Remote ON/OFF switching: ENABtE input EN (pin 10)
The output pulses can be switched on and off by applying logic levels to the TTL compatible ENABLEinput. A LOW level causes immediate inhibition of the output pulses, a subsequent HIGH level
switches the circuit on with the slow-start procedure.
If this facility is not required, EN should be connected to V^, pin 2.
Modulation input MOD (pin 5)
The duty factor of the output pulses may be reduced below the value resulting from the voltages on
the maximum duty factor input OFM and the gain adjust output GA by applying a lower voltage to
the modulation input MOD. This input may be used with an external control loop, e.g. for constant-
current control, or to obtain a fold-back characteristic.
If the modulation input is not used, it should be connected to Vz, pin 2.
Outputs QC and QE (pins 13 and 14)
To avoid double pulses that might occur at an excessively low mains voltage or an excessively high
output current the output is preceded by a latch. The two outputs offer a choice of output current
polarity, QC giving a positive current, i.e. a current flowing into the output, and QE giving a negative,
current, a current flowing out of the output. The two connections have the additional advantage that
the relatively large output currents do not flow through the Vrx ar>d ^EE connections, where they
could induce noise.
^rAugust 1982 275
TDA1Q60TDA1060ATDA1060B yv
RATINGS \
Lfmjting values ifl-accordance with the Absolute Maximum System (IEC 134)
Supply voltage range (voltage source)
Supply current (current source)
Feed-forward input voltage range
Vcc<24VVpc > 24 V
Input voltage range (all other inputs)
Emitter output voltage range
Collector output voltage range
Output current
d.c. (see Figs 3a, c and e)
peak; t = max. 1 ms; duty factor d < 10%
Storage temperature range
TDA1060
TPA1060A
TDA1060B
Operating ambient temperature range
TDA1060
TDA1060A
TDA1060B
Power dissipation (see Figs 3b, d and f)
vCc -0,5 to + 18 V
ice max. 30 mA
v 16-12 OtoVcc v
V16-12 Oto 24 V
V| Oto VZ V
Vl4-12 Oto 5 V
V15-12 Oto vCc v
-h4;h5 max. 40 mA—
' 1.4; ' 1 s max. 200 mA
Tstg-40 to + 125 °C
Tstg -40 to + 125 °C
Tstg-40 to +125 °C
Tamb -25 to + 125 °C
Tamb Oto + 70 °C
Tamb -55 to + 150 °C
Ptnt max. 1 W
276 August 1982^\r
Control circuit for SMPS
J V
TDA1060TDA1060ATDA1060B
(mAI
40-
I
30-
\.TDA1060
10-
u-l 1 1 1 1 1
7ZS9777
ptot
(W)
-TDA106C \
0-1 1 1 i t— 1 -r-
Tamb I "CI
I,
ImA)
40-
30 \
20-
TDA1060 A
10-
0-I I I
70
I 1 1 I
—
ptot
(W)
-50 50 100 150
Tamb (°d
TOA1060A
65 70
-1 1 T 1 1 1-
-50 50 100 150
Tamb (°CI
-50 50 100 150
Tamb (°C)
-50 60 100 150
Tamb !°C)
Fig. 3 Output current and power dissipation derating curves.
^\rAugust 1982 277
TDA1060TdA1060ATDA1060B
CHARACTERISTICS
VcC =12 V; Tamb = operating ambient temperature range, unless otherwise specified.
/ parameter symbol min. typ. max. unit
Operating ambient temperature range
TDA1060 Tamb -25 125 OC\
TDA1060A Tamb - 70 °C
TDA1060B Tamb -55 - 150 oc
Supply Vcc (pin 1
)
I Supply voltage
at Ice = 15 mATDA1060 vcc 18,5 23 27 V
TDA1060A vcc 18,5 23 27 V
TDA1060B vcc 18 23 27,5 V
at Ice = 30 mATDA1060 vcc 19,5 24 29 V
TDA1060A vcc 19,5 24 29 V
TDA1060B vcc 19 24 29,5 V
Supply current; R7 = 25 k£2;
duty factor d = 50%; lz = 0;
atTamb = 25<>C 'cc 2,5 10 mA
over ambient temperature range !CC 2,5 - 15 mA
Threshold voltage of low supply
voltage protection at TamD = 25 °C vCc 8,85 - 10,8 V
Variation with temperature -AVCC/AT - 7,5 - mV/K
{
Hysteresis of low supply
voltage protection
Stabilized supply output Vz (pin 2)
AVCC - 500 - mV
Output voltage at Tamb = 25 °C vz 7,5 8,4 9 V
Variation with temperature AVZ/AT -1,5 - + 1,5 mV/K
s Output current
Feedback input FB (pin 3)
-'z 5 mA
as Input voltage, feedback operation V3-12 2 - VZ-1 V
Input current at V3.1 2 = 2 V -l3 1,5 12 35 MInternal reference voltage, measured
at pin 3; pins 3 and 4 interconnected
and grounded via a 100 nF capacitor;
Tamb =25°C Vref 3,42 3,72 4,03 V
Variation with temperatureAVref/Vref - 0,01 - %/K
AT
v'
'
Variation with supply voltage
AV ref
AVCC- 0,8 - mV/V
27* January 1983^r
Control circuit for SMPS
J V
TDA1060TDA1060ATDA1060B
parameter
Long-term variation with time
Threshold voltage of feedback loop
short-circuit protection at TamD = 25 °C
Variation with temperature
Gain adjustment output GA (pin 4)
Open-loop gain, pin 3 to pin 4
External feedback resistor
Modulator input MOD (pin 5)
Input current at Vz>-\7 = 2 V;
V4;6-12>2V
Maximum duty factor input DFM (pin 6)
Input voltage for limiting the duty factor
to50%;fo = 10 to 100kHz;Vi6-i2 = 0VInput current at Vg_i2 = 2 V
Capacitor discharge current during fault
condition
Minimum output OFF time at C7 = 1,8 nF
Variation of max. duty factor with tempera-
50%
symbol
±AV ref/At
v3 12
AV3.12/V3.12
AT
R3-4
typ. max.
460
-15
Internal biasing resistor to Vf£E at
V3-12 = 0V R6-12
Synchronization input SYN (pin 9)
Input voltage,
sawtooth ON V| Hsawtooth OFF: TDA1060; TDA1060A V|L
TDA1060B V|L
Input current at Vg.-| 2 = V -IlL
External resistor connection RX (pin 7)
External frequency adjustment resistor R7
External capacitor connection CX (pin 8)
Sawtooth,
upper level at Vig.12 = V Vs-12
lower level v8-12Output pulse repetition frequency fo
Variation with temperatureAf /f
ATJ
v6-12-16
'6
toff
10
2,5
0,75
2
600 720
0,01
60
0,4VZ
1
0,02
1 1,25
2 - vz V- 0,8 V- 0,6 V
20 - 120 MA
40
5,7
1,3
0,05 - 100
0,01
unit
MV/h
mV
%/K
dB
k«
MA
V
ma
mA
MS
%/K
kn
kfi
V
V
kHz
%/K
\rJanuary 1983 279
TDA1060TDA1060ATDA1060B J VCHARACTERISTICS (continued)
parameter symbol min. typ, max. unit
Feed-forward input FW (pin 16)
Input voltage
for VCc < 24 V V16-12 vcc V
for Vqc > 24 V V16-12 24 V
Input current at Vie_i2 = 16 V;
VCc=18V;Tamb =25 C he - 60 ma
Frequency variation with input voltage
at Vi6-i2 >8vAf<A>
- 1 %/VAV 16-12
Overcurrent protection input CM (pin 1 1
)
Input voltage v 11-12 VZ V
Input threshold voltage for single pulse
inhibit (current limit modehTamk = 25 °C VT 1370 480 575 mV
Ratio of threshold voltages for shut down/
slow start and for single pulse inhibit VT2/VT1 _ 1,25
Threshold variation with temperature AV/AT 60 MV/K
Input current at Vii_-|2= 250 mV -'11 - 10 MA
Turn-off delay, 1\ 5 = 30 mA;
V 11.i2=1.2xVT1 td - 0,8 MS
Core saturation and overvoltage protection input SAT (pin 13)
Input voltage V13-12 VZ V
Input threshold voltage at Tamb = 25 °C v 13-12 460 600 720 mV
Threshold variation with temperature AV/AT 60 MV/K
Input current at V13.12 = 250 mV -'13 - 7 MENABLE input EN (pin 10)
Input voltage
ON VlN 2 VZ V
OF F : TDA 1 060; TDA 1 060A V|L 0,8 V
TDA1060B V|L 0,6 V
Input current at Viq,-12 = v -l|L 20 120 /xA
Outputs QC and QE (pins 14 and 15)
Output current -| 14-' l 15
- 30 mAEmitter output voltage v 14-12
- 5 V
Collector output voltage at V14.12 = V;
ll5 = 30mA ^15-14 - 400 mV
260 January 1983^r
Control circuit for SMPS
TDA1060TDA1060ATQA1060B
7Z89776
0,8
0.6
0,4
0,2
0.1 0,2 0,3 0,4 0,5 0,6 0,7
Fig. 4 Maximum duty factor dmax as a function
of the voltage divider ratio at the duty factor
input DFM.
0,6
0.2
0,6 1 1,4 1,8 2,2 2,6 3
Fig. 5 Feed-forward regulation characteristic. Dutyfactor d as a function of the voltage Vig-12 on *ne
feed-forward input FW. d is the duty factor for
V 16-12<VZ .
^rAugust 1982 281
ffwn
APPLICATION INFORMATION >>>606o) g> o>00003 J>
Fig. 6 Connections to the TDA1060 in a switched-mode power supply.
BYV958 BYV95B
T 3l3i:t t ,2W
<m ©
c/>
3W
Fig. 7 Application of the TDA1060 in a 24 V, 12 W SMPS with flyback converter.
Illllll
goo000w O) o»OOO00>
TDA106QTDA1060ATDA1060B
16 15 14 13 12 11 10 9
TDA1060
12 3 4 5 6 7 8
Vz
D +
-CZD-
24V/10A
Fig. 8 Application of the TDA1060 in a 24 V, 240 W SMPS with forward converter.
284 August 1982
Control circuit for SMPS
J V
TDA1060TDA1060ATDA1060B
16 15 14 13 12 11 10 9
TDA1060
1 2 3 4 5 6 7 8
CNY62 p h -r
Fig. 9 Application of the TDA1060 in a 5 V, 30 W SMPS with forward converter and with an
optocoupler CNY62 for voltage separation.
APPLICATION INFORMATION SUPPLIED UPON REQUEST.
~\rAugust 1982 285
DEVELOPMENT SAMPLE DATAThis information is derived from development samples
made available for evaluation. It does not necessarily
imply that the device will go into regular production.
yv.
TDA1540D
SUPERSEDES DATA SHEET OF TDA1540
14-BIT DAC WITH 85 dB S/N RATIO
GENERAL DESCRIPTION
TheTDA1540D is a monolithic integrated 14-bit digital to analogue converter (DAC). It incorporates s
14-bit input shift register with output latches, binary weighted current sources with switches and a
reference source.
The IC features an improved switch circuitry which eliminates the need for a deglitcher circuit at the
output. This results in a signal-to-noise ratio of typical 85 dB in the audio band.
QUICK REFERENCE DATA
Supply voltages
pin 4
pin 7
pin 11
Signal-to-noise ratio (full scale sine-wave)
at analogue output (pin 22)
Non-linearity at Tamb = -20 to + 70 °C
Current settling time
Maximum input bit rate
at data input (pin 1)
Maximum clock frequency
at clock input (pin 28)
Full scale temperature coefficient
at analogue output (pin 22)
Operating ambient temperature range
Total power dissipation
VP1 typ. 5 V
VN1 typ. -5 V
VN2 typ. -17 V
S/N typ. 85 dB
typ. Vz LSB
tcs typ. 0,5 /is
BRmax min. 12 Mbit/s
fcl max min. 12 MHz
TCFS typ. ±30-10"6K-
1
Tamb -20 to + 70 °C
Ptot typ. 350 mW
PACKAGE OUTLINE
28-lead DIL; ceramic (cerdip);SOT-135A.
^\rNovember 1982 287
TDA1540D
FUNCTIONAL DESCRIPTION
The tiinary weighted current sources are obtained by a combination of a passive divider and a time
division concept. Figure 1a gives the diagram of one divider stage. The total emitter current 4 1 of the
passive divider is divided into four more or less equal output currents.
The output currents of the passive divider are now interchanged during equal time intervals generated
by means of a shift register. The average output currents are exactly equal as a result of this operation.
A npple on the output current, caused by a mismatch of the passive divider, is filtered by an a.c.
low-pass filter, requiring an external filter capacitor.
The outputs of the dividers are combined to obtain the output currents I (i-|),l (fj) and 21 (I3)
(see Fig. lb). The current of the most significant bit is generated by an on-chip reference source.
A binary weighted current network is formed by cascading the current division stages (see Fig. 2),
Theinterchanging pulses are generated by an on-chip oscillator and a 4-bit shift register. Thebinary
currents are switched to the current output (pin 22) via diode-transistor switching stages; therefore,
the voltage on the output pin must be V ± 10 mV. The output current can be converted into a
voltage by means of a summing amplifier.
Figure 3 represents the data input format, and an application circuit is given in Fig. 4.
SHIFTREGISTER
2 3<? 9
hj '2j13J
__1—_/_____L___J0009 9<?o<? 0099 9
11
t >\
H \W
S S , S S
HJ*
2 I
-;i¥ m^
A31+A411
«*
^ tu
I A| I + A2 !
Fig. 1a Circuit diagram of one divider stage. Fig. 1b Waveforms showing output
currents !), I2 and I3 of Fig. 1a.
288 November 1982
^/"
DEVELOPMENT SAMPLE DATA
&
u-no
Zo
COCO
3F-t
Q.
>os*or
GOOl
Q.00
CO
z
Ien
TDA1540D
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltages
with respect to GND (pin 6)
at pin 4 Vpi max. 12 V
at pin 7 V|\n max. -12 V
at pin 1 1 Vpg2 max. -20 V
at pin 4 with respect to pin 1 1 Vpi _VN2 max - 32 V
at pin 7 with respect to pin 11 Vf\j-| —V(y|2 —1 to + 20 V
Total power dissipation Ptot max. 600 mWStorage temperature range Tstg —55to+125°COperating ambient temperature range TamD —25 to + 80 °C
CHARACTERISTICS (see application circuit Fig. 4)
Tamb = 25 °C; at typical supply voltages; unless otherwise specified
parameter symbol min. typ. max. unit
Supply voltages
with respect to GND (pin 6)
at pin 4 VP1 3 5 7 Vat pin 7 V|\I1 -4,7 -5 -7 Vat pin 1 1 VN2 -16,5 -17 -18 V
Supply currents
at pin 4*l P1
- 12 14 mAat pin 7 'N1
- -20 -24 mAat pin 1
1
! N2 - -11 -13 mA
Power dissipation
Total power dissipation ptot - ' 350 410 mW
Temperature
Operating ambient temperature range Tamb -20 + 70 °C
* When the output current is Vzlpg (J4 full scale output current).
2S$c November 1982
14-bit DAC with 85 dB S/N ratio TDA1540D
<<
a.
S
ZLU
sa.
O_lin
>iuQ
parameter symbol min. typ. max. unit
Data input DATA (pin 1)
Input voltage HIGH V|H 2,0 - 7,0 V
Input voltage LOW V|L - 0,8 V
Input current HIGH at V|h lH - - 50 *iA
Input current LOW at V| l -l|L - - 0,2 mAMaximum input bit rate BR max 12 - - Mbits/s
Latch enable input LE (pin 2)
Clock input CP (pin 28)
Input voltage HIGH V|H 2,0 - 7,0 V
Input voltage LOW VfL - 0,8 V
Input current HIGH at V|h hH - - 50 MAInput current LOW at V||_ -'IL
- - 0,2 mAMaximum clock frequency fCPmax 12 - - MHz
Oscillator (pins 8 and 9)
Oscillator frequency
at Cs-g = 820 pF ^osc 100 160 200 kHz
Analogue output lout (pin 22)
Output voltage compliance v c -10 - + 10 mVFull scale current 'FS 3,8 4,0 4,2 mAZero scale current ±izs - - 100 nA
Full scale temperature coefficient
Tamb = -20 to + 70 °C TCFS _ ± 30 x 10-6 _ K-1
Settling time to ± VzLSB
all bits on or off tcs 0,5 _ MS
Signal-to-noise ratio* S/N 80 85 - dB
Signal-to-noise ratio within 20 Hz and 20 kHz of a 1 kHz full scale sinewave, generated at a- sample
rate of 44 kHz.
vrNovember 1982 :
2S*t
TDA1540D
_yv
DATA -
CP -
LE-
¥ Hr820pF
(1%)
11 10 8 9
TDA1540D
!? 13 14 18 19 20 21 23 24 25
ref3
(0.6*l|| |
|«{>« Cauer-type
ref2 1* T meta'- film
resistors
filter
1111111111IT T^TrLp7
T'nl >*]«> nF]io„FJnFJnF^ S!^ W5 W ^ W> W) WX VK vm
PINNING
Fig. 4 Application circuit.
'1 DATA data input
2 LE latch enable input
3 Vrefl voltage reference
4 VP1 positive supply
5 i.e.* frequency compensation
on-chip operational amplifier
6 GND ground
7 VN1 negative supply
8
9
OSG1OSC2
oscillator capacitor
10 Vref2 voltage reference
11 VN2 negative supply
12 C1I
decoupling binary
13 C2 \ weighted current
14 C3 J sources
15 •refl|
16 'ref2 current reference sources
17 'ref3
18 C419 C5 I
decoupling binary weighted
20 C6 I current sources
21 C7I
22 'out analogue output
23 C8I
decoupling binary
24 C9 \ weighted current
25 C10 J sources
26 i.e.* voltage reference
27 i.e.* voltage reference
28 CP clock pulse input
DATA \T_ u 2s]cp
LE \T 2?] i.e.
Vrefl [T 26] i.c.
Vpi|T 25] C10
i.c. [~S~ 24] C9
GND |~6~23] C8
VNl[T 22] lou ,
oscifa"TDA1640D
2T]C7
OSC2[F 20] C6
vref2 fTo" "J9~|C5
VN2QT ji]c4
ci [u3zU
l,ei3
C2 [Ti" ji] Iref2
csfTT J3 'reft
7286851
Fig. 5 Pinning diagram.
* i.e.: internally connected.
292 November 1982^r
TDA3081
SEVEN-TRANSISTOR ARRAY
GENERAL DESCRIPTION
The TDA3081 is a bipolar integrated circuit consisting of seven common-emitter n-p-n transistors. Thetransistors are capable of driving loads up to 100 mA. This makes them particularly suited for driving
light-emitting diodes and seven-segment displays. The transistor geometry is such that it reaches its
maximum current gain at quite low currents, making the devices also suitable for small-signal applications.
QUICK REFERENCE DATA
Collector-base voltage (open emitter)
Collector-emitter voltage (open base)
Collector current (d.c.)
Power dissipation
each transistor
total
vCBO max. 18 V
VcEO max. 18 V
>C max. 100 mA
P max. 500 mWptot max. 750 mW
B1 CI B2 C2 B3 C3 B4 C4 B5 C5 B6 C6 B7 C7
—fTRl I—fTR2 I—fTR3 >—|tR4 L_(tR 5 l_(jr6 <—TtR7
^1 ^1 ^1 ^ ^1 ^ ^1
?
ci [~T
C2f~2~
B2pT
C3fl~
s r?"
B3[T
C4pT
B4|T
Fig. 1 Circuit diagram.
ITIB
|
B1
Til E
~u\ C7
TJ] B7
Ti] c6
77] B8
To] B5
~9~| C6
Fig. 2 Pinning diagram.
PACKAGE OUTLINE
16-lead Dl L; plastic (SOT-38Z).
^rJanuary 1983 293
TDA308t
RATINGS
"Limiting values in accordance with the Absolute Maximum Systems
Each transistor
Collector-emitter voltage (open base)
Collector-base voltage (open emitter)
Collector-substrate voltage (open base and emitter)
Emitter-base voltage (open collector)
Collector current (d.c.)
Base current (d.c.)
Power dissipation
each transistor
total (see also Fig. 3)
Storage temperature range
Operating ambient temperature range
(IEC134)
VCEO max. 18 V
vCBO max. 18 V
Vcso max. 18 V
VEBO max. 6 V
'C max. 100 mA
'B max. 20 mA
P max. 500 mWptot max. 750 mWTstg
-50 to + 1 25 °C
Tamb -40 to +125 °C
7Z72851.1
ptot
mWI
500
n
T.mb I "CI
Fig. 3 Power derating curve.
OPERATING NOTE
As each collector forms a parasitic diode with the substrate, the substrate has to be connected to a
voltage which is lower than any collector voltage. To minimize parasitic coupling between the tran-
sistors, this voltage should be signal ground.
January 1983^\r
Seven-transistor array TDA3081
CHARACTERISTICS
Tamb = 25 °C unless otherwise specified
parameter symbol min. typ. max. unit
Collector-emitter breakdown voltage
at Iq = 1 mA; lg = v(BR)CEO 32 - - V
Collector-substrate breakdown voltage
at lc = 1 mA; lg =0 v(BR)CS0 50 75 - V
Collector-base breakdown voltage
at lc = 100mA;Ie =0 v(BR)CBO 50 75 - V
Emitter-base breakdown voltage
at l E = 100mA;Ic = v(BR)EBO 6,5 7,2 7,8 V
D.C. current gain
I e =350mA;Vce = 5V "FE 75 - 525
l E =20mA;VCE = 5V hFE 47 - 365
Saturation voltage
at lc = 5mA;lB = 0,5 mA vCEsat - 200 400 mV
at lc = 50 mA; lg = 5 mA vCEsat - 400 840 mV
~\fJanuary 1983 296
TDA3083TDA3083D
FIVE-TRANSISTOR ARRAY
GENERAL DESCRIPTION
The TDA3083 is a bipolar integrated circuit consisting of five n-p-n transistors. The transistors are
capable of driving loads up to 100 mA. This makes them particularly suited for driving light-emitting
diodes and seven-segment displays. The transistor geometry is such that it reaches its maximum current
gain at quite low currents, making the devices also suitable for small-signal applications.
The transistors are partly matched, i.e. TR1 and TR2 form a matched pair, TR3 and TR4 also, and TR2and TR5 likewise.
QUICK REFERENCE DATA
Collector-base voltage (open emitter)
Collector-emitter voltage (open base)
Collector current (d.c.)
Power dissipation
each transistor
total
vCBO max. 18 V
VCEO max. 18 V
"C max. 100 mA
P max. 500 mWPfnt max. 750 mW
B1 C1 B2 C2 B3 C3 B4 C4 B5 C5
16 1 3 2 6 7 10 9 13 14
L-Kr, ^R2 ^R3 ^R4 ^ R5
J^ 15 4 8 11 12
I
S El E2 E3 E4 E5
7Z8 6803
Fig. 1 Circuit diagram.
ci (T
C2[T
B2pT
E2|~4~
s[T
B3|~T
C3|T
E3[T
TDA3083TDA3083D
Ts~| B1
g E ,
"m| C5
7JT|b5
T£[e5
]TjE4
To] B4
T)C4
Fig. 2 Pinning diagram.
PACKAGE OUTLINE
TDA3083 : 1 6 lead D I L; plastic (SOT-38Z)
.
TDA3083D: 16-lead mini-pack; plastic (SO-16;SOT-109A).
^\rJanuary 1983 297
TDA3083TDA3083D
RATINGS
Limiting values in accordance with the Absolute Maximum System
Each transistor
Collector-emitter voltage (open base)
Collector-base voltage (open emitter)
Collector-substrate voltage (open base and emitter)
Emitter-base voltage (open collector)
Collector current (d.c.)
Base current (d.c.)
Power dissipation
each transistor
total (see also Fig. 3)
Storage temperature range
Operating ambient temperature range
IEC134)
vCEO max. 18 V
vCBO max. 18 V
vCSO max. 18 V
vEBO max. 6 V
'C max. 100 mA
•b max. 20 mA
p max. 500 mWptot max. 750 mWTstg -50 to + 125 °C
Tamb -40 to + 125 °C
ptot
(mW) ^ vv
\N\
\ ~<1>
AnV
VI
^s\
•Tamb (°C»
(1) Derating curve for TDA3083D (SO-16;SOT-109A) mounted on a ceramic substrate of
50 x 50 x 0,7 mm with heatsink compound: Rtn j.a = 90 K/W; without heatsink compound:Rthj-a = 12° K/W typical. Mounted on a printed-circuit board of 50 x 50 x 1,5 mm: Rth
i a=
180 K/W.J
Fig. 3 Power derating curves.
OPERATING NOTE
As each coMector forms a parasitic diode with the substrate, the substrate has to be connected to a
voltage which is lower than any collector voltage. To minimize parasitic coupling between the tran-
sistors, this voltage should be signal ground.
298 January 1983^\r
Five-transistor array TDA3083TDA3083D
CHARACTERISTICS
Tamb = 25 °C unless otherwise specified
parameter symbol min. typ. max. unit
Collector-emitter breakdown voltage
at Iq = 1 mA; lg = v(BR)CEO 32 - - V
Collector-substrate breakdown voltage
at lc = 1 mA;l|= = v(BR)CSO 50 75 - V
Collector-base breakdown voltage
at lc = 100mA;Ie =0 v(BR)CBO 50 75 - V
Emitter-base breakdown voltage *
at lg = 100 mA; Ic = v(BR)EBO 6,5 7,2 7,8 V
D.C. current gain
Ie=350|*A;Vce = 5 V "FE 75 - 525
l E = 20mA;VCE = 5 V "FE 47 - 365
Saturation voltage
at lc = 5 mA; Iq = 0,5 mA vCEsat - 200 400 mVat Irj = 50 mA; lfj = 5 mA vCEsat - 400 840 mV
Input offset voltage at Vqe = 5 V; Irj = 1 mAany two transistors V|0 - 1 - mVmatched pairs V|0 - 0,5 - mV
Input offset current at Vqe = 5 V; Iq = 1 mAany two transistors ho - 2 - MAmatched pairs ho - 0,5 - /"A
Breakdown of the emitter-base junction causes degeneration of the current gain of the transistor.
\r"January 1983 299
DEVELOPMENT SAMPLE DATAThis information is derived from development samples
made available for evaluation. It does not necessarily
imply that the device will go into regular production.
JK.TEA1017
13-BIT SERIES-PARALLEL CONVERTER
GENERAL DESCRIPTION
The TEA1017 is a bipolar integrated circuit intended to drive displays, triacs and relays. The data is
serially shifted into the device and is stored in 13 latches that drive the outputs.
Features
• TTL and CMOS compatible inputs
• Outputs drive load in both directions
• Power-on reset makes outputs floating
• Wide supply voltage rangeV(
7
6
'
L
CONTROLLOGIC
ENSHG ' 3
C2
5niFN SRG14
>C1/-»
h r4
h rid m 2D I
1' 7
2
[2] 2D I2
! V1
TEA1017
|131 2D M3] v8
h|14|
3
Fig. 1 Block diagram. The block marked SRG14 is a 14-bit shift register, the block marked SRG13is an array of 13 latches.
QUICK REFERENCE DATA
Supply voltage range
Output current, each output
Clock frequency
Operating ambient temperature range
VCc 5 to 18 V
•ol; -'oh typ- 80 mA
^CLB max - 50 kHz
Tamb -20 to +80 °C
PACKAGE OUTLINE
18-lead OIL; plastic (SOT-102HE).
~\rFebruary 1983 301
TEA1017
•-. \
FUNCTIONAL INSCRIPTION
The control logic performs a key function in this device. It checks whether the input information has
the correct format: a DLEN signal that has been HIGH for 14 clock pulses, and a DATA signal with its
first bit LOW! When the format is found to be correct, the 1 5th clock pulse makes the control logic
generate a signal that loads the content of the first 13 bits of the shift register into 13 latches. These
drive the output stages.
Supply Vqc (pin 7)
The supply current of the TEA1017 is regulated internally. This permits the circuit to be used over a
very wide range of supply voltages, viz. 5 to 18 V, with little variation of supply current.
The circuit has a power-on reset arrangement that resets the circuit and brings the outputs in a high-
impedance state.
The power-on reset ends When a complete set of information has been received and is transferred to
the latches, i.e. at the 15th HIGH-to-LOW transition of the clock pulse.
DATA input (pin 4)
The circuit requires input information on the DATA input consisting of 14 bits, the first bit being LOW.This Information should be synchronous with the clock pulse. Data is loaded into the shift register at
the HIGH-to-LOW transitions of the clock pulse.
Data line enable input DLEN (pin 5)
A HIGH level on the DLEN input enables the shift register. This HIGH level should have a duration of
14 clock pulses (see Fig. 3). After the DLEN input has returned to LOW the subsequent (15th) clock
pulse1
transfers the content of the shift register to the latches and from there to the outputs.
Clock input CLB (pin 6)
• The shift register shifts at the HIGH-to-LOW transitions of the clock pulse. The clock signal may be a
continuously running clock or a clock burst of 1 5 clock pulses.
Outputs Q1 to Q13
The outputs are capable of supplying a load current in both directions, i.e. they can drive a load to the
supply (Vcfj) or to ground (Vee>- A load current to ground increases the supply current Irjrj by the
same amount.
t—: \r302 February 1983
13-bit series-parallel converter TEA1017
PINNING
Q2 [~T u li"|Q3
01 [T T7[04
veeQT l¥lQ5
DATA [T lF|06
DLEN [T TEA1017 TT| Q7
CLBfs" iTjoa
vcc[T T7|09
Q13fj" TT|qio
< Q12J~9" To] Q11
< 7Z80319
HI-J0.
5< Fig. 2 Pinning di agram.
HZLU
s RATINGSo_l Limiting values in accordance with tr
UJ
>mQ
Supply voltage
Input voltage ramje, all inputs
1 Q2 output 2
2 Q1 output 1
3 VEE common
4 DATA data input
5 DLEN data line enable input
6 CLB clock input
7 vCc positive supply
8 Q13 output 13
9 Q12 output 12
10 Q11 output 1
1
11 Q10 output 10
12 Q9 output 9
13 Q8 output 8
14 Q7 output 7
15 Q6 output 6
16 Q5 output 5
17 Q4 output 4
18 Q3 output 3
vccV|
Output current, all outputs
HIGH -l0HLOW l0L
Total power dissipation
Storage temperature range
Operating ambient temperature range
rtot
Tstg
Tamb
max. 18 V
-0,3toVcc +0,3-V
max. 150 mAmax. 150 mAmax. 1,4 W
' -40 to + 150 °C
-20 to +80 °C
February 1983 3P3
TEA1017
CHARACTERISTICS
Vcc = 5 to 18 V; Tamb = 25 °C unless otherwise specified
parameter symbol min. typ. max. unit
Supply (pin 7)
Supply current
during normal operation, unloaded
at VCC = 5 Vat Vqc " 18v
ice
'CC
- 45
5060
70
mAmA
during power-on reset, unloaded
atVCC = 5Vat VCc = 18 V
'cc
•cc
- 1,5
5
2
7
mAmA
Clock input CLB (pin 6)
Input voltage
HIGHLOW
V|HVlL
2 -
0,4
VV
Input current
HIGHatVCLBH = 2VLOWatVCLBL = °.4V
l|H
-l(L
- - 10
10
ma
Clock pulse duration
HIGHLOW
lwH*wL
10
10 _ _MS
MS
DATA input (pin 4)
Input voltage
HIGHLOW
V|HVlL
2 -
0,4
VV
Input current
HIGHatVDATAH = 2VLOW at VDATAL = 0,4 V
l|H
-l|L
- 10
10
MAMA
Data line enable input DLEN (pin 5)
Input voltage
HIGHLOW
V|HV| L
2 -
0,4
VV
Input current
•HIGHatVDLENH = 2VLOWatVDLENL = 0,4V
l|H
-"IL
- 10
10
MAmA
Outputs Q1 to Q13
Output voltage during normal operation
HIGH at -l0H = 80 mALOW at Iql = 80 mA
V HVOL
VCC -1.5 -1
VV
Output current during power-on reset
HIGHLOW
-'ohlOL
- - 10
10
MAma
304 February 1983'~\r
13»bit series-parallel converter TEA1017
I KT\ M^FY^H^H^H^HgQ
7?80321
Fig. 3 Timing diagram.
<Q
o.
S3HZIII
so.
o-IUJ
>UJQ
^/^February 1983 306
TEA1039
CONTROL CIRCUIT FOR SWITCHED-MODE POWER SUPPLY
GENERAL DESCRIPTION
The TEA1039 is a bipolar integrated circuit intended for the control of a switched-mode power supply.
Together with an external error amplifier and a voltage regulator (e.g. a regulator diode) it forms a
complete control system. The circuit is capable of directly driving the SMPS power transistor in small
SNIPS systems.
It has the following features:
• Suited for frequency and duty factor regulation.
Suited for flyback converters and forward converters.
Wide frequency range.
Adjustable input sensitivity.
Adjustable minimum frequency or maximum duty factor limit.
Adjustable overcurrent protection limit.
Supply voltage out-of-range protection.
Slow-start facility.
QUICK REFERENCE DATA
Supply voltage
Supply current
Output pulse repetition frequency range
Output current LOW
Operating ambient temperature range
Vfx nom. 14 V
Iqc max. T3 mAf 1 Hz to 100 kHz
Iql max - 1 A
Tamb -25 to + 125 °C
PACKAGE OUTLINE
9-lead SIL; plastic (SOT-1 10B).
August 1982 307
—zfN0,37 V— *V<
n$>
>
-0,25I R
SAWTOOTHGENERATOR
VCC OUT OF RANGE
^K^^c^F
^£>
3^2V-
2,2 V-
5,9 V -
~Q.25I RX -
-0-25iRX -
-0,6IRX -
VCC OUT OF RANGE -
VOLTAGEAND
CURRENTSTABILIZER
T7 • 4
C BX 7Z85W4
Hm>ow
Fig. 1 Block diagram.
Control circuit for SMPS TEA1039
ro ^J oli ii i i
—
ii—
i
j ) TEA1039
12 3 4 5 6 7 8 9
j{ \
J I \S I L
PINNING
1 CM overcurrent protection input
2 L!M limit setting input
3 FB feedback input
4 RX external resistor connection
5 CX external capacitor connection
6 M mode input
7 VEE common
8 Q output
9 VCC positive supply connection
CM LIM FB RX CX M V EE Q Vcc
7Z8S672
Fig. 2 Pinning diagram.
FUNCTIONAL DESCRIPTION
The TEA1039 produces pulses to drive the transistor in a switched-mode power supply. These pulses
may be varied either in frequency (frequency regulation mode) or in width (duty factor regulation
mode).
The usual arrangement is such that the transistor in the SMPS is ON when the output of the TEA1039is HIGH, i.e. when the open-collector output transistor is OFF. The duty factor of the SMPS is the time
that the output of the TEA1039 is HIGH divided by the pulse repetition time.
Supply Vqc <P in 9)
The circuit is usually supplied from the SMPS that it regulates. It may be supplied either from its
primary d.c. voltage or from its output voltage. In the latter case an auxiliary starting supply is
necessary.
The circuit has an internal Vqq out-of-range protection. In the frequency regulation mode the oscillator
is stopped; in the duty factor regulation mode the duty factor is made zero. When the supply voltage
returns within its range, the circuit is started with the slow-start procedure.
When the circuit is supplied from the SMPS itself, the out-of-range protection also provides an
effective protection against any interruption in the feedback loop.
Mode input M (pin 6)
The circuit works in the frequency regulation mode when the mode input M is connected to ground
(Vee, pin 7). In this mode the circuit produces output pulses of a constant width but with a variable
pulse repetition time.
The circuit works in the duty factor regulation mode when the mode input M is left open. In this modethe circuit produces output pulses with a variable width but with a constant pulse repetition time.
\/TAugust 1982 309
TEA1039
FUNCTIONAL DESCRIPTION (continued)
Oscillator resistor and capacitor connections RX and CX (pins 4 and 5)
The output pulse repetition frequency is set by an oscillator whose frequency is determined by an
•external capacitor C5 connected between the CX connection (pin 5) and ground (VgE, Pi" 7), and an
eVtema) resistor R4 connected between the RX connection (pin 4) and ground. The capacitor C5 is
charged by an internal current source, whose current level is determined by the resistor R4. In the
frequency regulation mode these two external components determine the minimum frequency; in the
duty factor regulation mode they determine the working frequency (see Fig. 4). The output pulse
repetition frequency varies less than 1% with the supply voltage over the supply voltage range.
In the frequency regulation mode the output is LOW from the start of the cycle until the voltage on
the capacitor reaches 2 V. The capacitor is further charged until its voltage reaches the voltage on either
the feedback input FB or the limit setting input LIM, provided it has exceeded 2,2 V. As soon as the
capacitor voltage reaches 5,9 V the capacitor is discharged rapidly to 1,3 V and a new cycle is initiated
(see Figs 5 and 6).
For voltages on the FB and LIM inputs lower than 2,2 V, the capacitor is charged until this voltage is
reached; this sets an internal maximum frequency limit.
In the duty factor regulation mode the capacitor is charged from 1 ,3 V to 5,9 V and discharged again at
a constant rate. The output is HIGH until the voltage on the capacitor exceeds the voltage on the
feedback input FB; it becomes HIGH again after discharge of the capacitor (see Figs 7 and 8). An
internal maximum limit is set to the duty factor of the SMPS by the discharging time of the capacitor.
Feedback input FB (pin 3)
the feedback input compares the input current with an internal current source whose current level is
set by the external resistor R4. In the frequency regulation mode, the higher the voltage on the FB input,
the longer the external capacitor C5 is charged, and the lower the frequency will be. In the duty factor
regulation mode external capacitor C5 is charged and discharged at a constant rate, the voltage on the
FB input now determines the moment that the output will become LOW. The higher the voltage on
the FB input, the longer the output remains HIGH, and the higher the duty factor of the SMPS.
Limit setting input LIM (pin 2)
In the frequency regulation mode this input sets the minimum frequency, in the duty factor regulation
mode it sets the maximum duty factor of the SMPS. The limit is set by an external resistor R2
connected from the LIM input to ground (pin 7) and by an internal current source, whose current level
is determined by external resistor R4.
A slow-start procedure is obtained by connecting a capacitor between the LIM input and ground. In the
frequency regulation mode the frequency slowly decreases from fmax to the working frequency. In the
difty factor regulation mode the duty factor slowly increases from zero to the working duty factor.
Overcurrent protection input CM (pin 1
)
A voltage pn the CM input exceeding 0,37 V causes an immediate termination of the output pulse. In
the duty factor regulation mode the circuit starts again with the slow-start procedure.
Output Q (pin 8)
The output is an open-collector n-p-n transistor, only capable of sinking current. It requires an external
resistor to drive an n-p-n transistor in the SMPS (see Figs 9 and 10).
The output is protected by two diodes, one to ground and one to the supply.
At high output currents the dissipation in the output transistor may necessitate a heatsink. See the
power derating curve (Fig. 3).—\r310' August 1982
Control circuit for SMPS TEA1039
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply vdltage range, voltage source
Supply current range, current source
Input voltage range, all inputs
Input current range, all inputs
Output voltage range
Output current range
output transistor ON
output transistor OFF
Storage temperature range
Operating ambient temperature range (see Fig. 3)
Power dissipation (see Fig. 3)
vCc -0,3 to +20 V
ice -30 to +30 mAV| -0,3 to +6 V
'I—5 to +5 mA
V8-7 -0,3 to +20 V
>8 to 1 A
'8 -100 to+ 50 mATstg -55 to + 150 °C
Tamb -25 to + 125 °C
ptot max. 2 W
Fig. 3 Power derating curve.
*\fAugust 1982 311
TEA1039
CHARACTERISTICS
Vcq = 14 V; Tarnb= 25 °C unless otherwise specified
symbol min. typ. max. unit
Supply Vcc (Pin 9)
Supply voltage, operating Vcc 11 14 20 V
Supply current
atVCc=11 V ice — 7,5 11 mA
at VCC = 20 V ice- 9 12 mA
variation with temperatureAlcc/'CC
AT- -0,3 - %/K
Supply voltage, internally limited
at ICC = 30 mA vcc 23,5 — 28,5 V
variation with temperature AVCC/AT - 18 - mV/K
Low supply threshold voltage VcCmin 9 10 11 V
variation with temperature AVCC/AT - -5 - mV/K
High supply threshold voltage VcCmax 21 23 24,6 V
variation with temperature AVccMT - 10 — mV/K
Feedback input FB (pin 3)
Input voltage for duty factor = 0;
M input open V3-7 — 0,3 V
Internal reference current -'FB - 0,5
1
RX - mA
Internal resistor Rg
Rg
- 130 - kfi
Limit setting input LIM (pin 2)
,Threshold voltage V2-7 - 1
- V
Internal reference current —'LIM - 0,25 l RX - mA
Overcurrent protection input CM (pin 1
)
Threshold voltage V1-7 300 370 420 mV
variation with temperature AV^y/AT - 0,2 - mV/K
Propagation delay, CM input to output tPHL - 500 — ns
312 August 19^2~\f
Control circuit for SMPS TEA1039
CHARACTERISTICS (continued)
symbol min. typ. max. unit
Oscillator connections RX and CX (pins 4
and 5)I
Voltage at RX connection
at -14 = 0,15 to 1 mAvariation with temperature
V4-7
AV4.7/AT
6,2 7,2
2,1
8,1 VmV/K
Lower sawtooth level v Ls 1,3 - VThreshold voltage for output H to L
transition in F mode Vft 2 _ V
Threshold voltage for maximumfrequency in F mode Vfm 2,2 _ V
Higher sawtooth level Vhs 5,9 - VInternal capacitor charging current,
CX connection -'ex 0,25 1
1
IX - mAOscillator frequency (output pulse
repetition frequency) *0 1 10s Hz
Minimum frequency in F mode,initial deviation Af/f -10 10 %
variation with temperatureAf/f
AT 0,034 - %/K
Maximum frequency in F mode,initial deviation Af/f -20 + 20 % ' '
variation with temperatureAf/f
AT-0,16 - %/K
Output LOW time in F mode,
initial deviation At/t -25 + 25 %
variation with temperatureAt/t
AT 0,2 - %/K
Pulse repetition frequency in D mode,initial deviation Af/f -10 10 %
variation with temperatureAf/f
AT 0,034 - %/K
Minimum output LOW time in D modeatC5 = 3,6nF lOLmin 1 — MS
variation with temperatureAt/t
AT' 0,2 - %/K
Output Q (pin 8)
Output voltage LOW at \q = 100 mA V8-7 0,8 1,2 Vvariation with temperature AV8.7/AT 1,5 - mV/K
Output voltage LOW at lg = 1 A V8-7 1,7 2,1 Vvariation with temperature AV8.7/AT -1,4 - mV/K
February 1983 313
TEA1039
100
80
820pF 390pF
f
(kHz)
ys
1,2 nF
1,8nF
2,7nF
3,9 nF
5,6 nF
6,8 nF
20,4 r F
40 60 80 100
R4(kS2)
Fig. 4 Minimum pulse repetition frequency in the frequency regulation mode, and working pulse
repetition frequency in the duty factor regulation mode, as a function of external resistor R4 connectedbetween RX and ground with external capacitor C5 connected between CX and ground as a parameter.
31* August 19^2
Control circuit for SMPS TEA1039
-j| 5,9 V
Fig. 5 Timing diagram for the frequency regulation mode showing the voltage on external capacitor
C5 connected between CX and ground and the output voltage as a function of time for three com-binations of input signals, a: The voltages on inputs FB or LIM are between 2,2 V and 5,9 V. Thecircuit is in its normal regulation mode, b: The voltage on input FB or input LIM is lower than 2,2 V.
The circuit works at its maximum frequency, c: The voltages on inputs FB and LIM are higher than
5,9 V. The circuit works at its minimum frequency.
C5»7Z85669 2,7 nF
tOLmin
(lis)A>
ay
At
7b
820 pF
390 pF
20 40 50R4(kSJ)
Fig. 6 Minimum output pulse repetition time Tm jn (curves a) and minimum output LOW time
toLmin (curves b) in the frequency regulation mode as a function of external resistor R4 connectedbetween RX and ground with external capacitor C5 connected between CX and ground as a parameter.
Abjjuit 1982 315
TEA1039
J V5,9 V
„| 7Z85667
Fig. 7 Timing diagram for the duty factor regulation mode showing the voltage on external capacitor
C5 connected between CX and ground and the output voltage as a function of time for two combina-
tions of input signals, a: The voltages on inputs FB or LIM are below 5,9 V. The circuit is in its normal
regulation range, b: The voltages on inputs FB and LIM are higher than 5,9 V. The circuit produces its
minimum output LOW time, giving the maximum duty factor of the SNIPS.
1.6
)Lmin
7Z85670
(us)
1,2
0,8
0,4
C5(nFI
Fig. 8 Minimum output LOW time tQLmin m tne duty factor regulation mode as a function of external
capacitor C5 connected between CX and ground. In this mode the minimum output LOW time is
independent of R4 for values of R4 between 4 kQ, and 80 kft.
316 August J|82^\r
Control circuit for SMPS
,
J VTEA1039
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NOTES