UNIT IIGATE LEVEL MINIMIZATION

1. THE MAP METHOD, FOUR VARIABLE K-MAP, FIVE-VARIABLE K-MAP

Introduction to Karnaugh Maps

1. The Karnaugh map (or K-map) is a visual way of detecting redundancy in the SOP.2. The K-map can be easily used for circuits with 2, 3, or 4 inputs.3. It consists of an array of cells, each representing a possible combination of inputs.4. The cells are arranged to that each cell’s input combination differs from adjacent cells by

only a single bit. 5. This is called Gray code ordering – it ensures that physical neighbors are the array and are

logical neighbors as well. (In other words, neighboring bit patterns are nearly the same, differing by only 1 bit).

Consider the following arrangements of cells:

2-input 3-input

a’b’ a’b a’ b’ c’ a’b’c a’b c a’ b c’00 01 000 001 011 010

a b’ a b a b’ c’ a b’ c a b c a b c’10 11 100 101 111 110

4-input

a’b’c’d’ a’b’c’d a’b’cd a’b’cd’0000 0001 0011 0010

a’bc’d’ a’bc’d a’bcd a’bcd’0100 0101 0111 0110

abc’d’ abc’d abcd abcd’1100 1101 1111 1110

ab’c’d’ ab’c’d ab’cd ab’c@d’1000 1001 1011 1010

The cells are arranged as above, but we write them empty, like this:

Note that the numbers are not in binary order, but are arranged so that only a single bit changes between neighbors. This one-bit change applies at the edges, too. So cells in the same row on the left and right edges of the array also only differ by one bit.

Note: The value of a particular cell is found by combining the numbers at the edges of the row and column.

Also, in general, it is easier to order the inputs to a K-map so that they can be read like a

binary number. (Show example.)So, we have this grid. What do we do with it?

We put 1's in all the cells that represent minterms in the SOP. (In other words, we find the 1's in the truth table output, and put 1's in the cells corresponding to the same inputs.)Let’s do this in relation to the 2-input multiplexer example

If there are two neighboring 1's in the grid, it means that the input bit change between the two cells has no effect on the output, and thus there is redundancy. This leads to a basic strategy.

Basic Strategy:

Group adjacent 1's together in square or rectangular groups of 2, 4, 8, or 16, such that the total number of groups and isolated 1's is minimized, while using as large groups as possible. Groups may overlap, so that a particular cell may be included in more than one group.

S A B Y0 0 0 0 0 0 1 00 1 0 10 1 1 11 0 0 01 0 0 11 1 0 01 1 1 1

Applying this to the multiplexer example:

So, considering the best option above (i), notice the following:B changes but the output doesn’t, so B is redundant in this group (See comment 1, below). A changes but the output doesn’t, so A is redundant in this group (See comment 2, below).

So, we write out Boolean expressions for each group, leaving out the redundant elements. That is, for each group, we write out the inputs that don’t change.The multiplexer example, with two groups, gives us two terms, Y = S@B + S’@AWhich is the same as what we achieved through using Boolean algebra to reduce the circuit.So, we can summarize this process into a basic set of rules:

Rules for K-Maps:

1. Each cell with a 1 must be included in at least one group. 2. Try to form the largest possible groups. 3. Try to end up with as few groups as possible. 4. Groups may be in sizes that are powers of 2 5. Groups may be square or rectangular only (including wrap-around at the grid edges). ****No diagonals or zig-zags can be used to form a group.

The larger a group is, the more redundant inputs there are:

A group of 1 has no redundant inputs. A group of 2 has 1 redundant input. A group of 4 has 2 redundant inputs. A group of 8 has 3 redundant inputs. A group of 16 has 4 redundant inputs.

The following simple examples illustrate rule 6 above

EXAMPLE:

2-input Example

A B Y

0 0 1

10 1

01 1

11 0

Direct from truth table: Y = A’B’ + A’B + AB’

3-input Example

A B C Y

0 0 0 0

0 10 0

1 00 1

1 10 1

0 01 1

0 11 0

1 01 1

1 11 1

Direct from truth table: Y = A’BC’ + A’BC + AB’C’ + ABC’ + ABC

4-input Example

A B C D Y

0 0 0 0 1

0 0 10 0

0 1 00 1

0 1 10 0

1 0 00 0

1 0 10 1

1 1 00 0

1 1 10 1

0 0 01 1

0 0 11 0

0 1 01 1

0 1 11 0

1 0 01 0

1 0 11 1

1 1 01 1

1 1 11 1

USE A K-MAP TO REDUCE THE FOLLOWING 4-INPUT CIRCUIT:

A B C D Y

0 0 0 0 1

0 0 10 0

0 1 00 1

0 1 10 0

1 0 00 1

1 0 10 1

1 1 00 1

1 1 10 1

0 0 01 1

0 0 11 0

0 1 01 1

0 1 11 0

1 0 01 1

1 0 11 1

1 1 01 1

1 1 11 1

Five variable k- map:

Five variable k-map can have 25 =32 possible combinations of input variable as A’B’C’D’E’, A’B’C’D’E,--------ABCDE with minterms m0, m1-----m31 respectively in SOP & A’+B’+C’+D’+E’, A’+B’+C’+D’+E,---------- A+B +C +D +E with maxterms M0,M1, ----------- M31 respectively in POS form. It has 25=32 squares or cells of the k-map are divided into 2 blocks of 16 squares each.

The left block represents minterms from m0 to m15 in which A is a 0, and the right block represents minterms from m16 to m31 in which A is 1.The 5-variable k-map may contain 2-squares, 4-squares , 8-squares , 16-squares or 32-squares involving these two blocks. Squares are also considered adjacent in these two blocks, if when superimposing one block on top of another, the squares coincide with one another.

Grouping s is

Ex: F=Σm(0,1,4,5,6,13,14,15,22,24,25,28,29,30,31) is SOPPOS is F=πM(2,3,7,8,9,10,11,12,16,17,18,19,20,21,23,26,27)

The real minimal expression is the minimal of the SOP and POS forms.The reduction is done as

1. There is no isolated 1s2. M12 can go only with m13. Form a 2-square which is read as A‘BCD‘

3. M0 can go with m2,m16 and m18 . so form a 4-square which is read as B‘C‘E‘4. M20,m21,m17 and m16 form a 4-square which is read as AB‘D‘5. M2,m3,m18,m19,m10,m11,m26 and m27 form an 8-square which is read as C‘d6. Write all the product terms in SOP form. So the minimal expression isFmin= A‘BCD‘+B‘C‘E‘+AB‘D‘+C‘D(16 inputs)

In the POS k-map ,the reduction is done as:1. There are no isolated 0s

M8 M28 M30 Sum terms in POS form. So the minimal expression in POS is Fmin= A‘BCD‘+B‘C‘E‘+AB‘D‘+C‘D

Don’t care combinations:

For certain input combinations, the value of the output is unspecified either because the input combinations are invalid or because the precise value of the output is of no consequence. The combinations for which the value of experiments are not specified are called don‘t care combinations are invalid or because the precise value of the output is of no consequence. The combinations for which the value of expressions is not specified are called don‘t care combinations or Optional Combinations, such expressions stand incompletely specified. The output is a don‘t care for these invalid combinations.

Ex: In XS-3 code system, the binary states 0000, 0001, 0010,1101,1110,1111 are unspecified. & never occur called don‘t cares.A standard SOP expression with don‘t cares can be converted into a standard POS form by keeping the don‘t cares as they are & writing the missing minterms of the SOP form as the maxterms of the POS form vice versa.

Don‘t cares denoted by ‗X‘ or ‗φ‘

Ex: f=Σm(1,5,6,12,13,14)+d(2,4)

Or f=π M(0,3,7,9,10,11,15).πd(2,4)SOP minimal form fmin= BC’+B’D +A’C’DPOS minimal form fmin=(B+D)(A’ +B)(C’ +D’)

2. NAND and NOR ImplementationThe implementation of a logic expression such that each one of the inputs has to pass through

only two gates to reach the output is called Two-level implementation.

Both SOP , POS forms result in two-level logic Two level implementation can be with AND, OR gates or only NAND or with only NOR gates Boolean expression with only NAND gates requires that the function be in SOP form.

Function F= AB+CD(A) AND-OR logic(B) NAND-NAND logic F=AB+CD= AB+CD =AB .CD

AND-OR Logic NAND LogicTwo –level implementation using AND-OR and NAND logic the implementation of the form:F=XY‘+X‘Y+Z using AND-OR logic and NAND- NAND logic is

Two –level implementation using AND-OR and NAND logic

The implementation of Boolean expressions with only NOR gates requires that the function be in the form of POS form.Implementation of the function (A+B)(C‘+D‘)

Two –level implementation using OR-AND and NOR logic

Two –level implementation using OR-AND and NOR logic

Questions

1. Minimize the following Boolean function using k-map and realize using NAND Gates F(A, B, C, D)= Σm(0, 2, 4, 6, 8, 10, 12, 14).

2. Minimize the following Boolean function using k-map and realize using NOR GatesF(A, B, C, D)= Σm(0, 2, 7,6, 8, 11, 15, 14).

3. Minimize the following Boolean function using k-map and realize using NAND GatesF(A, B, C)= Σm(0, 2, 3, 4, 6,) and realize using NAND Gates

4. Simplify the Boolean function F(W,X,Y,Z)=(1,3,7,11,15) that has don’t care conditions d(W,X,Y,Z)= (0,2,5)

5. Find the minterms of the following expressions and plot each in a map1) XY+YZ+XY’Z 2) WXY+X’Z’+W’XY

6. Simplify the following functions using five variable K-maps F(A,B,C,D,E)=∑(0,1,4,5,16,17,21,25,29)

7. Simplify the following functions in 1) F(A,B,C,D)= π(1,3,5,7,13,15,) 2) F(A,B,C,D)= π(0,1,2,3,4,10,11)

QUINE-MCCLUSKEY METHOD (TABULATION METHOD)Quine- Mccluskey Method:

It also known as Tabular method. It is more systematic method of minimizing expressions of even larger number of variables. It is suitable for hand computation as well as computation by machines i.e., programmable. . The procedure is based on repeated application of the combining theorem.PA+P =P (P is set of literals) on all adjacent pairs of terms, yields the set of all PI‘s from which a minimal sum may be selected.

EXAMPLE

QUESTIONS1. Simplify the Boolean function by using tabulation method

F(a,b,c,d)=Σ m (0,1,2,5,6,7,8,9,10,14)

2. Simplify the following Boolean function using Tabulation method

Y(A,B,C,D) = Σm(1,3,5,8,9,11,15)

3. Simplify the following Boolean function using Tabulation method

Y(A,B,C,D,E,F,G) = Σm(20,28,38,39,52,60,102,103,127)

4. Simplify the following Boolean function using Tabulation method

Y(A,B,C,D,E)= Σm(6,9,13,18,19,25,27,29,41,45,57,61)

3. NON DEGENERATE FORMSIt will be instructive from a theoretical point of view to find out how many two-level combinations of gates are possible. We consider four types of gales: AND, OR, NAND and NOR. If we assign one type of gate for the first level and one type for the second level. We find that there are 16 possible combinations of two-level forms. Eight of these combinations are said to be degenerate forms because they degenerate to a single operation. This can be seen from a circuit with AND gates in the first level and an AND gate in the second level. The output of the circuit is merely the AND function of all input variables. The remaining eight nondegenerate forms produce an implementation in sum-of-products form or product-of-sums form. The eight nondegenerate forms are as follows: AND-OR OR- AND NAND-NAND NOR-NOR NOR-OR NAND-AND OR-NAND AND-NOR

AND-OR-INVERT ImplementationThe two forms NAND-AND and AND-NOR are equivalent and can be treated together. The AND-NOR form resembles the AND-OR form. but with an inversion done by the bubble in the output of the NOR gate. It implements the function F ~ (AB + CD + E)'

By using the alternative graphic symbol for the NOR gate. we obtain the diagram of Fig. (b).. The circuit of Fig.(c) is a NAND-AND form

OR-AND-INVERT Implementation

The OR- NAND and NOR-OR forms perform the OR- AND-INVERT function. It implements the function F = [(A + B)(C + D)E]'By using the alternative graphic symbol for the NAND gate, we obtain the diagram of Fig.(b). The circuit in (c) is obtained by moving the small circles from the inputs of the second-level gate to the outputs of the first-level gates.

The Exclusive OR (X-OR) gate:It has 2 inputs& only 1 output. It assumes output as 1 when input is not equal called anti-

coincidence gate or inequality detector.

0

Logic Symbol

Proof: Truth Table

The high outputs are generated only when odd number of high inputs is present. This is why x-or function also known as odd function.

The X-OR gate using AND-OR-NOT gates:

A B0 0 00 1 11 0 11 1 0

X-OR gate as an Inverter:

By connecting one of two input terminals to logic 1 & feeding the sequence to be inverted to other terminal

X-OR gate using NAND gates only:

X-OR gate using NOR gates only:

Parity Generator using x-or gates:

QUESTIONS:

1. Implement the following Boolean function F, using the two-level forms of logic (a ) NAND-AND (b) AND-NOR, (c) OR-NAND, and (d) NOR-OR: F(A, B, C, D} = m (0,4.8.9, 10, 11, 12, 14)

2. Implement the following Boo lean expression with exclusive-O R and AND gates: F = AB'CD' + A'BCD' + AB'C'D + A'BC 'D

3. Show that the dual of the exclusive-OR is also its complement