the end of commodity memory · the first 40 years of dram 4 bits bits per unit units 1975 1995 2015...
TRANSCRIPT
The 3rd Wave: Hyper Performance and the End of Commodity Memory
David Chapman VP Marketing
An Introduction…
Feeling Warm?
3
http://hairpinturnsahead.typepad.com/.a/6a0133ec7b075a970b01bb07aa594c970d-pi
The First 40 Years of DRAM
4
Bits
Bits per Unit
Units
1975 1995 2015 + 53%/Yr
1975 1995 2015
1975 1995 2015
The Bandwidth
Era
The Price per Bit
Era
The First Transformation
5
Units
1975 1995 2015
DRAM Data Bandwidth
6
http://tech4gizmos.com/70/
Cache Gone Wild
7
http://images.anandtech.com/reviews/cpu/intel/nehalem/part3/totalcache.png
The Long Boil
8
1995 2015
DRAM
Fast SRAM M
arke
t Sha
re
Slow SRAM
Volatile RAM Hierarchy
9
On-Die SRAM
Fast SRAM
Slow SRAM
DRAM
1000x 100x
10x
1x
DRAM Vendor Base
10
> 30 DRAM Vendors
3 DRAM Vendors
1985 2015
Bits Shrink – Die Grow
11
http://www.intechopen.com/books/advances-in-solid-state-circuit-technologies/dimension-increase-in-metal-oxide-semiconductor-memories-and-transistors
Die Size (mm2)
Bit Cell Size (µm2)
10K
1K
100
10
1
0.1
0.01 1K 256K 16K 64M 4M 1G 16G
25% 40% 90%
Array Efficiency
12
1970 1990 2010
Arr
ay E
ffici
ency
On-Die Routing Dominates
13
The Gap
14
http://image.slidesharecdn.com/2010-10-02introtomicroprocessors1-120907074913-phpapp01/95/2010-1002-intro-to-microprocessors1-17-728.jpg?cb=1347004218
Not Dead Yet
15
http://megaodd.com/wp-content/uploads/2015/01/70ae5__FoodsEatenAlive07-650x401.jpg
The Bandwidth
Era
The Price per Bit Era
The Next 20 Years
16
1975 1995 2015 2035
Higher Density? More Bandwidth? Lower Latency? Higher Trans Rate? Lower Cost? Lower Power?
Bandwidth is NOT the Problem
17
“The problem isn’t memory bandwidth — it’s memory latency and memory power consumption.”
Forget Moore’s law: Hot and slow DRAM is a major roadblock to exascale and beyond By Joel Hruska on July 14, 2014 @ http://www.extremetech.com
http://www.extremetech.com/computing/185797-forget-moores-law-hot-and-slow-dram-is-a-major-roadblock-to-exascale-and-beyond
Higher Density? More Bandwidth? Lower Latency? Higher Trans Rate? Lower Cost? Lower Power?
The Bandwidth
Era
The Price per Bit Era
The Next 20 Years
18
1975 1995 2015 2035
Low Power
Micron HMC
19
http://www.extremetech.com/computing/167368-hybrid-memory-cube-160gbsec-ram-starts-shipping-is-this-the-technology-that-finally-kills-ddr-ram
https://www.semiwiki.com/forum/content/1610-3d-memories.html
http://www.anandtech.com/show/4819/intel-and-micron-develop-hybrid-memory-cube-stacked-dram-is-coming
http://wiley-vch.e-bookshelf.de/products/reading-epub/product-id/2418826/title/handbook+of+3d+integration.html?lang=en
Clocking Stalls
20
http://deliveryimages.acm.org/10.1145/2140000/2133822/figs/f7.jpg
Hynix HBM
21
http://www.eetasia.com/ART_8800714409_499486_NT_874cb9d4.HTM
http://wccftech.com/nvidia-pascal-gpu-17-billion-transistors-32-gb-hbm2-vram-arrives-in-2016/
Intel Knight’s Landing HPC Processor
22
http://www.eweek.com/servers/us-blocks-intel-from-supplying-chips-for-chinese-supercomputers.html
http://www.pcper.com/news/General-Tech/Learn-bit-more-about-Knights-Landing
http://electroiq.com/insights-from-leading-edge/2014/06/iftle-198-intel-to-commercialize-micron-hmc-3d-stacked-memory-in-hpc-processor-gs-nanotech-announces-3dic-plans-statschippac-suitors-named/
http://news.cecb2b.com/info/20150326/3082445.shtml
High Performance “Near” Memory
23
http://cdn.wccftech.com/wp-content/uploads/2015/03/Intel-Knights-Landing-Processor_Adams-Rack.jpg
http://forums.anandtech.com/showthread.php?t=2388600
Bandwidth?
24
http://images.anandtech.com/doci/8217/MCDRAM.jpg
Multi Channel Memory • Reduces Trace Lengths • Reduces Power • Reduces Latency • Supports Multi Threading • Supports Multi-Core • Increases Bandwidth • Increases Transaction Rate
25
Conventional 3D Packaging
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• Die Stacking
• Preserves traditional RAM problems
• Adds stacking costs
Di3D™: Dis-Integrated 3D™
27
Tezzaron Stacks Wafers
28
Side
Vie
w
< 0.
5 m
m
Dis-Integrated DiRAM4 Architecture
29
The Bit Layer(s) (Memory Cells &
Access Transistors)
The Control Layer (Sense Amps, etc.)
The I/O Layer
Dis-Integrated DiRAM4 Architecture
30
Isometric View
Highest Transistors
Density Possible
≈ 150 femtometer Silicon Process
1st bonding: F-to-F
1st bonding: F-to-F
1st bonding: F-to-F
1st bonding: F-to-F
2nd bonding : B-to-B
2nd bonding : B-to-B
3rd bonding : B-to-B
True Architectural 3D Micron HMC Die Stack
Hynix HBM Die Stack
Tezzaron TSV-free Wafer Bonding
DiRAM4 Performance Advantage
32
2 x
Den
sityg
fPa
ge C
ycle
50%
Dat
a B
andw
idthg
4
x
fW
orst
Cas
e La
tenc
y 50
%
Tran
sact
ion
Rat
eg
70 x
Tezzaron Best-in-class competitive 3D offering
3rd Wave RAM • High Signal Count • Intimate Interface • High Trans Rate • Low Latency • High Power Density • Much Smarter • Non-commodity
Ending the Long Boil
34
1995 2015
DRAM
Fast SRAM
Mar
ket
Shar
e Slow
SRAM
100x RAM
3D NVM
10x RAM
1x RAM
Crossing the Chasm…
35
FPGA
HPC
Networks
Expect FPGA Early Adopters ü Performance driven ü Quick to market ü Small volumes ü High value
SyoPort™ Tagging Hub DTH1 4 Ports SIO DDR x64 Each 512 Add/Data
Wires
Maintenance Port
JTAG (ARM)
DiRAM4 64C64 64 Ports SIO DDR x32 Each 4096 Data Wires
JTAG DiRAM4
JTAG (ARM)
JTAG DTH1
TDI TMS TCK TRST# TDO
JTAG Internal
Maintenance Port
SPI SPI
16 SIO Ports
16 SIO Ports
16 SIO Ports
16 SIO Ports
x64 SIO Port
x64 SIO Port
x64 SIO Port
x64 SIO Port
TDO TMS TCK
TRST# TDI
JTAG External
I2C External
SDA SCL
I2C Internal
SDA SCL
Ayrees SyoPort-P BGA Module
MHUB-1
Cntl I/O-1
Bits 0 Bits 1 Bits 2 Bits 3 Bits 4 Bits 5 Bits 6 Bits 7 Bits 8 Bits 9
Bits 10 Bits 11 Bits 12 Bits 13 Bits 14 Bits 15
BGA Package Substrate http://www.etech-web.com/bga-reballing.htm
Volatile RAM Hierarchy
37
On-Die SRAM
3D Multi-Channel
RAM
DRAM
1000x 100x
10x
1x
DRAM Replacement 0.1x
Back to Normal
38
http://i.dailymail.co.uk/i/pix/2015/01/29/25298CC300000578-0-image-a-14_1422544485309.jpg
