text book: silicon vlsi technology fundamentals practice...

Introduction - Chapter 1

Text Book:Silicon VLSI Technology

Fundamentals Practice andFundamentals, Practice and Modeling

Authors: J D Plummer M D DealAuthors: J. D. Plummer, M. D. Deal, and P. B. Griffin

SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin

© 2000 by Prentice HallUpper Saddle River NJ


INTRODUCTION - Chapter 1

• This course is basically about silicon chip fabrication• This course is basically about silicon chip fabrication, the technologies used to manufacture ICs.

• We will place a special emphasis on computer simulation tools to help understand these processes and as design toolsand as design tools.

• These simulation tools are more sophisticated inThese simulation tools are more sophisticated in some technology areas than in others, but in all areas they have made tremendous progress in recent



years.

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Evolution of IC FabricationEvolution of IC Fabrication

1960 d 1990 i t t d i it• 1960 and 1990 integrated circuits.• Progress due to: Feature size reduction - 0.7X/3 years (Moore’s Law).

Increasing chip size - ≈ 16% per year.“Creativity” in implementing functions.



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y p g


Semiconductor Progress

• Decreasing: feature size (line widths line spacing• Decreasing: feature size (line widths, line spacing, layer depth, layer-to-layer tolerances), power per active component, operating voltage

• Increasing: chip size, wafer size, circuit density, circuit complexity speed and reliabilitycircuit complexity, speed, and reliability

• Economics: virtuous economic and developmentEconomics: virtuous economic and development cycle



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Device Scaling Over Time100µm

Feature Size

Cell dimensions10µmEra of Simple Scaling

1µm

0.1µm130 nm in 2002

Scaling + Innovation(ITRS)

Atomic dimensions

10nm Transition Region18 nm in 2018

Invention

Atomic dimensions

0.1nm

1nm Quantum Effects Dominate

Atomic Dimensions

• The era of “easy” scaling is over. We are now in a period wheretechnology and device innovations are required. Beyond 2020, new

1960 1980 2000 2020 2040 Year



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currently unknown inventions will be required.


Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018

Technology Node (half pitch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm

MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm

DRAM Bits/Chip (Sampling) 256M 512M 1G 4G 16G 32G 64G 128G 128G

MPU Transistors/Chip (x106) 550 1100 2200 4400 8800 14,000

Min Supply Voltage (volts) 1.8-2.5 1.5-1.8 1.2-1.5 0.9-1.2 0.8-1.1 0.7-1-0 06-0.9 0.5-0.8 0.5-0.7 Min Supply Voltage (volts) 1.8 2.5 1.5 1.8 1.2 1.5 0.9 1.2 0.8 1.1 0.7 1 0 06 0.9 0.5 0.8 0.5 0.7

ITRS at http://public.itrs.net/ (2003 version + 2004 update) – on class website.• Assumes CMOS technology dominates over entire roadmap.gy p• 2 year cycle moving to 3 years (scaling + innovation now required).

• 1990 IBM demo of Å scale “lithography”.• Technology appears to be capable of making structures much smaller than



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currently known device limits.


Intel – From Sand to Silicon

• http://www.intel.com/pressroom/kits/chipmaking/

A quick video of IC fabrication– A quick video of IC fabrication



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Linewidth vs. Fab Cost

100000 10

10000

100000) 1

10

)

Fab Cost ($M)

Linewidth (nm)

100

1000

Fab

Cos

t ($M

)

0 1

1

Line

wid

th (u

m)

1

10

0.01

0.1

100mm 150mm 200mm 300mm 450mm11975 1980 1985 1990 1995 2000 2005 2010 2015 2020 2025

0.01

Advantages and Challenges Associated with the Introduction of 450mm Wafers :A position paper report submitted by the ITRS Starting Materials Sub-TWG, June 2005.



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y g ,http://public.itrs.net/papers.html


Moore’s LawOn April 19, 1965 Electronics Magazine published a paper by Gordon Moore in which he made a prediction about the

i d i d h h b h ff f l dsemiconductor industry that has become the stuff of legend.

“The number of transistors incorporated in a chipwill approximately double every 24 months.”pp y y

Known as Moore's Law, his prediction has enabled widespread proliferation of technology worldwide, and today h b h th d f id t h l i l hhas become shorthand for rapid technological change.



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http://www.intel.com/pressroom/kits/events/moores_law_40th/index.htm?iid=tech_mooreslaw+body_presskit


Historical Perspective

• Invention of the bipolar transistor - 1947, Bell Labs.

• Shockley’s “creative failure” methodology

N

P

N

P

N N

• Grown junction transistor technology of the 1950s

N

P N NP



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N


HistoryHistory• Bardeen, Brattain and Shockley

– Point Contact Transistor in 1947 at Bell Laboratory– Followed by the bipolar transistor

• Integrated Circuit DevelopmentIntegrated Circuit Development– Jack Kilby demonstrated in 1958

• Texas InstrumentsRobert Noyce similar time frame with Silicon– Robert Noyce similar time frame with Silicon

• Fairchild Semiconductor



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Physical Devices

NPN d PNP Bi l J ti T i t• NPN and PNP Bipolar Junction Transistors • Field Effect Transistors (FET)

– Metal-Oxide-Semiconductor FET (MOSFET)Metal Oxide Semiconductor FET (MOSFET)– Junction FET (JFET)

• Others:– PN Junction– Resistor– Capacitorp– Photo-Diode and Photo-Transistor



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N

In

N

In • Alloy junction technology of the 1950s.

NNP

P

N PN

N

P

N

N

• Double diffused transistor technology of the 1950s.

N

PN

N

P



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N


N P

N

Si O2

• The planar process (Hoerni -

N

N

P N

• The planar process (Hoerni -Fairchild, late 1950s).

• First “passivated” junctions.

P

N

N

P



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Photolithographyg p y• Basic lithography process

– Apply photoresistpp y p– Patterned exposure– Remove photoresist regions

Etch wafer Light– Etch wafer– Strip remaining photoresist

Photoresist

Mask

Substrate

Film deposition Photoresist application

Deposited Film

Exposure

Etch mask



15Development Etching Resist removal


Planar Integrated Circuit• Patterning of multiple photoresist patterns and

processing steps create a planar integrated circuit– P regions– N regions– Metal Contact Holes Analog BJT– Metal Pattern

Vsource Ground

EmitterBase

Collector

P N PNP

Resistor Resistor



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N


Planar Digital IC• Complimentary Metal-Oxide-Semiconductor (CMOS)

– N-channel MOS Field Effect Transistors NMOSP channel MOS Field Effect Transistors PMOS– P-channel MOS Field Effect Transistors PMOS

Mask Layers:llP-well

N-wellP+N+G

PNP+ P+ N+ N+

GateContactL1 L1-L2 viaL2

P WellN Well

PMOS NMOS

L2L2-L3 viaL3 Thickness

Substrate: >500 um



P 17

Subst ate: 500 uActive Layer: < 1 um


Multiple Metal Layers

• Metal Planarization i d f lti lrequired for multiple

metal layers– Metal Depositionp– Patterning– Fill Dielectric

Planarization– Planarization– Contact vias– Contact Deposition



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Silicon Technology Leadership and the New Scaling ParadigmMark Bohr, Intel Senior Fellow, Logic Technology DevelopmentApril 18, 2007


Computer Simulation Tools (TCAD)

• Most of the basic technologies in silicon chipMost of the basic technologies in silicon chip manufacturing can now be simulated.

• Simulation is now used for:– Designing new processes and devices.– Exploring the limits of semiconductor devices and

technology (R&D).gy ( )– “Centering” manufacturing processes.– Solving manufacturing problems (what-if?)



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• Simulation of an advanced local oxidation process.

• Simulation of• Simulation of photoresist exposure.



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NEXT TIME:NEXT TIME: BASIC DEVICE PHYSICS



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Challenges For The Future• Having a “roadmap” suggests that the future is well defined and there are

few challenges to making it happenfew challenges to making it happen.

• The truth is that there are enormous technical hurdles to actually achievingthe forecasts of the roadmap. Scaling is no longer enough.

• 3 stages for future development:

“Technology Performance Boosters” InventionSili idSilicide

PolyGate

SidewallSpacer

GateDi l t i

Gate

Source Drain• Spin-based devices

M l l d i

Substrate

Silicide

RchanSource DrainS/D Ext S/D Ext

Dielectric

???Source Drain • Molecular devices

• Rapid single flux quantum• Quantum cellular automata• Resonant tunneling devices• Single electron devices

Materials/process innovationsNOW

Beyond Si CMOSIN 15 YEARS??

Substrate g



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NOWDevice innovations

IN 5-15 YEARS

IN 15 YEARS??


Broader Impact of Silicon Technology

Tip on Stage Individual Actuator Part of 12 x 12 arrayCornell University

0 0 0 5V

-1.0

-0.5

0.0 -0.75V

-1.5V

-1.25V

-1V

-0.5V

Source Drain

SiO2

2 5

-2.0

-1.5

I ds(A

)

-2.25V-2V

-1.75VGateSiO2

-3.0x10-6

-2.5

-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0

V (V)

-2.5V Stanford, Cornell

• Many other applications e.g. MEMs and many new device structures e.g. carbont b d i ll b i ili t h l f f b i ti



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VD(V)nanotube devices, all use basic silicon technology for fabrication.


Summary of Key Ideas• ICs are widely regarded as one of the key components of the information age.

• Basic inventions between 1945 and 1970 laid the foundation for today's silicon industry.

• For more than 40 years, "Moore's Law" (a doubling of chip complexity every 2-3 years) has held true.

• CMOS has become the dominant circuit technology because of its low DC• CMOS has become the dominant circuit technology because of its low DC power consumption, high performance and flexible design options. Future projections suggest these trends will continue at least 15 more years.

• Silicon technology has become a basic “toolset” for many areas of science andengineering.

• Computer simulation tools have been widely used for device, circuit and system Computer simulation tools have been widely used for device, circuit and system design for many years. CAD tools are now being used for technology design.

• Chapter 1 also contains some review information on semiconductor materials i d t d i Th t i ill b f l i l t h t f th t t



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semiconductor devices. These topics will be useful in later chapters of the text.

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